JPH01134956A - Assembly of semiconductor device - Google Patents

Assembly of semiconductor device

Info

Publication number
JPH01134956A
JPH01134956A JP62292007A JP29200787A JPH01134956A JP H01134956 A JPH01134956 A JP H01134956A JP 62292007 A JP62292007 A JP 62292007A JP 29200787 A JP29200787 A JP 29200787A JP H01134956 A JPH01134956 A JP H01134956A
Authority
JP
Japan
Prior art keywords
sheet
ceramic
assembly
pellet
ceramic sheet
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62292007A
Other languages
Japanese (ja)
Inventor
Susumu Iizaka
飯坂　進
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP62292007A priority Critical patent/JPH01134956A/en
Publication of JPH01134956A publication Critical patent/JPH01134956A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16195—Flat cap [not enclosing an internal cavity]

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Dicing (AREA)

Abstract

PURPOSE:To make possible a significant reduction in manhour, an increase in a fine processing and a low cost by a method wherein the assembly and sealing of pellet, which have been performed by individual packages, are disposed simultaneously by a multitude of packages. CONSTITUTION:Electrodes are formed on the surface of a ceramic sheet 1 with penetrated holes bored therein along scribing lines by such a means as printing or deposition. A second green sheet 3 with a plurality of element housing windows 7 bored therein is prepared. The sheet 3 is superposed on the sheet 1 to sinter integrally and a multilayer ceramic sheet is formed. The electrode side of IC pellets 4 is faced downward and a face down bonding is performed on the electrodes 2 on the sheet 1.A cap sheet 5 is superposed and bonded on the sheet through a glass or the like. The 3-layer ceramic sheet is cut by laser scribing conforming to scribing lines and is separated into individual products, each including an IC. Thereby, a significant reduction in manhour, an increase in a fine processing and a low cost become possible.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、半導体装置の組立、封止技術に関するもので
、特にＬＣＣ（Ｌｅａｄｌｅｓｓ　　ＣｈｉｐＣａｒｒ
ｉｅｒ）に代表されるセラミックタイプ面付けＩＣのマ
ルチ組立及び封止作業の大幅な合理化技術に関するもの
である。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to assembly and sealing technology for semiconductor devices, and in particular to LCC (Leadless Chip Carr).
The present invention relates to a technology that significantly streamlines the multi-assembly and sealing work of ceramic-type surface-mounted ICs, such as those represented by IER.

〔従来の技術〕[Conventional technology]

セラミックタイプの面付けＩＣについては本出願人によ
るＬＣＣパッケージの他に、京セラ（株）、鳴海製陶（
株）などによるセラミックパッケージが製造販売されて
いる。これらは個々のセラミックペースに半導体チップ
を搭載し、キャップ部材を被せて個別に組立封止を行っ
ている。Regarding ceramic type surface-mounted ICs, in addition to LCC packages by the applicant, Kyocera Corporation and Narumi Seito (
Ceramic packages are manufactured and sold by companies such as Co., Ltd. These are made by mounting semiconductor chips on individual ceramic pastes, covering them with cap members, and individually assembling and sealing them.

〔発明が解決しようとする問題〕[Problem that the invention seeks to solve]

セラミックパッケージＩＣは、パッケージを形成するセ
ラミック製のペース、キャップが１つ１つの単品（１ヶ
取り）として形成されており、半導体装置組立の後工程
ではそのノ・ンドリンクが通常のリードフレームを用い
たプラスチックパッケージ半導体製品に比較して難かし
く、作業ＳＴが高くなっている。さらに単品のペース、
キャップは高価であり、原価低減の妨げとなりている。In a ceramic package IC, each ceramic paste and cap that forms the package is formed as a single item (one piece), and in the post-process of semiconductor device assembly, the non-links are attached to a normal lead frame. Compared to the plastic packaged semiconductor products used, it is difficult and the work ST is high. Furthermore, the page for single items,
Caps are expensive and are an impediment to cost reduction.

本発明の目的は、このようなセラミックパッケージＩＣ
の組立にマルチ組立方式を採用することＫよっ【、大幅
な作業ＳＴの低減、部品材料費の低減を図ることにある
。The object of the present invention is to provide such a ceramic packaged IC.
By adopting a multi-assembly method for assembly, the aim is to significantly reduce work ST and parts material costs.

本発明の前記ならび罠そのほかの目的と新規な％徴は、
本明細書の記述および添付図面からあきらかになるであ
ろう。The above and other objects and novel features of the present invention are as follows:
It will become clear from the description of this specification and the accompanying drawings.

〔問題点を解決するための手段〕[Means for solving problems]

上記目的は、スクライブラインにそって透孔なあけたセ
ラミックのシートの表面に電極を印刷、蒸着などの手段
で形成し、この上にペレットをボンディングする部位に
キャビティとなる複数の窓孔なあけたセラミックシート
を重ねて焼結することにより一体化した多層セラミック
シートを用い、各窓孔な通して半導体ペレットを電極上
に接続し、キャップ部材を重ねて封止した後、多層のシ
ートをレーザスクライブして個々のペレットを含むセラ
ミック封正体に分離すること罠より達成される。The above purpose is to form electrodes by printing, vapor deposition, etc. on the surface of a ceramic sheet with perforations along the scribe line, and to make a plurality of window holes to form cavities in the area where the pellet is to be bonded. Using a multilayer ceramic sheet that is integrated by stacking and sintering ceramic sheets, a semiconductor pellet is connected to the electrode through each window hole, and after sealing by stacking a cap member, the multilayer sheet is heated using a laser beam. Scribing and separation into ceramic enclosures containing individual pellets is accomplished by trapping.

〔作用〕[Effect]

上記手段によればペレットをキャビティの窓孔に落とし
込むだけで、ペレットと、外部電極との位置合わせがで
き、多数の半導体装置の組立封止が同時に能率よく行う
ことが可能であり、また、部品材料費の低減を図ること
ができる。According to the above method, the pellet can be aligned with the external electrode simply by dropping the pellet into the window hole of the cavity, and it is possible to efficiently assemble and seal a large number of semiconductor devices at the same time. Material costs can be reduced.

〔実施例〕〔Example〕

第１図乃至第８図は本発明の実施例を示すものであり、
以下各工程にしたがって説明する。1 to 8 show embodiments of the present invention,
Each step will be explained below.

＋１１　　まず、第１図に示すようにスクライプライン
６にそりてスルーホール（透孔）８をマトリックス配列
し【あけた第１のグリーンシート（ペース）１を用意し
、スルーホール８の内面を含み、シートの表裏面にスル
ーホール印刷によって内部電極、外部電極パターン２を
印刷する。一方、複数の素子収納用窓（キャビティ）７
をあげた第２のグリーンシート（フレーム）３を用意す
る。さらにキャップ用のシート５を用意する。+11 First, as shown in FIG. , internal electrode and external electrode patterns 2 are printed on the front and back surfaces of the sheet by through-hole printing. On the other hand, multiple element storage windows (cavities) 7
Prepare a second green sheet (frame) 3 with . Furthermore, a sheet 5 for a cap is prepared.

（２）　　第２図に示すように第１のグリーンシート１
の上に第２のグリーンシート３を重ねて一体に焼結し、
多層のセラミックシート（第３図）を形成する。(2) First green sheet 1 as shown in Figure 2
Layer the second green sheet 3 on top and sinter it together,
A multilayer ceramic sheet (Figure 3) is formed.

（３）　　第３図に示すようにＩＣペレット４の電極（
バンプ電極）側を下向きにしてシート上の電極２にフェ
イス・ダウンボンディングをする。このとき各窓孔７は
位置決め枠になり、かつ、第４図に示すように各枠内に
ペレットが収納された状態になる。(3) As shown in Figure 3, the electrodes of the IC pellet 4 (
Perform face down bonding to electrode 2 on the sheet with the bump electrode) side facing downward. At this time, each window hole 7 becomes a positioning frame, and pellets are housed in each frame as shown in FIG. 4.

（４１上からキャップシート５を重ねてガラス等を介し
て封着する。(Lay the cap sheet 5 on top of 41 and seal it with glass or the like in between.

（５）最後第５図に示すようにスクライプラインに合わ
せてレーザースクライブにより３層のセラミックシート
を切断し、第６図〜第７図に示すように個々のＩＣを含
む半導体製品に分離する。(5) Finally, as shown in FIG. 5, the three-layer ceramic sheet is cut by laser scribing along the scribe line, and separated into semiconductor products including individual ICs as shown in FIGS. 6 and 7.

本実施例によれば、組立から封止乃至選別段階までマル
チ組立法忙より行うことができ、これまでの個々のパッ
ケージによる組立法に比して工数は約５分の１に低減す
ることができる。また、グリーンシート状態での適用に
より、印刷パターンの微細化（０，１龍以下）対応が可
能となり、パッケージの厚さも１．　Ｏｎ以下の淳さに
薄くすることが可能となる素材の価格圧ついても個別の
ベース・キャップに比して低価格となる。According to this embodiment, the steps from assembly to sealing to sorting can be performed using multiple assembly methods, and the number of man-hours can be reduced to about one-fifth compared to the conventional assembly method using individual packages. can. In addition, by applying it in the form of a green sheet, it is possible to support finer printing patterns (0.1 dragon or less), and the thickness of the package can be reduced to 1. Even if the price of the material that can be made thinner and thinner than On is lower, the price will be lower than that of individual base caps.

以上本発明者によってなされた発明を実施例にもとづい
き具体的に説明したが、本発明は上記実施例に限定され
るものではな（、その要旨を逸脱しない範囲で下記のよ
うに種々変更可能であることはいうまでもない。Although the invention made by the present inventor has been specifically explained based on examples, the present invention is not limited to the above examples (and can be modified in various ways as described below without departing from the gist of the invention. Needless to say, it is.

１１１　　実施例では、スクライプラインにそったスル
ーホールはペースシートにのみ設けたが、中層のシート
、キャップのシートにも同様にスルーホールをあけてお
いてもよい。第８図はこのような場合の３層のシートを
使用し、レーザスクライブによって得られた１つのＩＣ
を含むセラミックパッケージ製品例を示すものである。111 In the embodiment, the through holes along the scribe line were provided only in the pace sheet, but the through holes may also be made in the middle layer sheet and the cap sheet. Figure 8 shows one IC obtained by laser scribing using a three-layer sheet in such a case.
This figure shows an example of a ceramic package product including:

この場合、３１藷のパッケージを裏返えすことなくスク
ライプラインを確認してレーザスクライブを行うことが
できる。In this case, the scribe line can be checked and laser scribed can be performed without turning over the package.

（２）実施例ではバンプ付ペレットを使用してフェイス
ダウン・ボンディングにより電極に接続する場合の例に
ついて説明したが、フェイスダウンによらず、ペレット
の上向き電極とシートの電極との間をワイヤボンディン
グにより接続してもよ（、ボンディング工程をのぞけば
同様の効果が得られる。(2) In the example, an example was explained in which a pellet with bumps is used to connect to an electrode by face-down bonding, but instead of face-down, wire bonding is used between the upward facing electrode of the pellet and the electrode of the sheet. The same effect can be obtained except for the bonding process.

（３１実施例ではマ）　ＩＪソックス状シートの形を示
したが、１列多連のシートを用い連続組立法を行うこと
も可能である。(In the 31st embodiment, the shape of the IJ sock-like sheet is shown.) However, it is also possible to carry out a continuous assembly method using multiple sheets in one row.

〔発明の効果〕〔Effect of the invention〕

本発明によれば、従来、個々のパッケージで行っていた
ペレット組立・封止を多数のパッケージで同時に処理す
ることができることにより、工数の大幅な低減、微細加
工化、低価格が可能となるという効果を有する。According to the present invention, pellet assembly and sealing, which was conventionally done for individual packages, can be done simultaneously for many packages, making it possible to significantly reduce man-hours, microfabricate, and lower costs. have an effect.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本発明の一実施例を示すものであって、組立前
のセラミックグリーンシートの各層のシートの斜視図で
ある。 第２図乃至第６図は本発明による組立プロセスの各工程
のシート及び半導体ペレットの断面図である。 第７図及び第８図はシートを切りはなした個々のセラミ
ックパッケージ半導体装置の斜視図である。 １・・・第１のセラミック・シート（ペース）、２・・
・電極、３・・・第２のセラミック・シート（中間層）
、４・・・半導体ペレット、６・・・スクライブライン
、７・・・窓孔（キャビティ）、８・・・スルーホール
（透孔）。 第　　１　　回 第　　２　　図 第　　３　　図 ／ 第　　４　　図FIG. 1 shows an embodiment of the present invention, and is a perspective view of each layer of ceramic green sheets before assembly. 2 to 6 are cross-sectional views of sheets and semiconductor pellets at each step of the assembly process according to the present invention. 7 and 8 are perspective views of individual ceramic packaged semiconductor devices with sheets cut away. 1... first ceramic sheet (pace), 2...
・Electrode, 3... second ceramic sheet (intermediate layer)
, 4... Semiconductor pellet, 6... Scribe line, 7... Window hole (cavity), 8... Through hole (through hole). 1st session 2nd figure 3rd/4th figure

Claims (1)

【特許請求の範囲】 １、スクライブ・ラインにそって透孔を配列した第１の
セラミックシートの表面上に上記透孔内面を含めて電極
層を形成し、この上に複数の窓孔を有する第２のセラミ
ックシートを重ねて一体に形成し、各窓孔を通して半導
体ペレットを上記電極層に接続し、この上にキャップと
なるシートを重ねて半導体ペレットを封止したのち、重
ねられたシートをレーザスクライブすることにより個々
のペレットを含むセラミック封止半導体装置に分離する
ことを特徴とする半導体装置の組立方法。 ２、上記半導体ペレットをフェイスダウン・ボンディン
グにより電極に接続する特許請求の範囲第１項に記載の
半導体装置の組立方法。[Claims] 1. An electrode layer is formed on the surface of a first ceramic sheet in which through holes are arranged along the scribe line, including the inner surface of the through holes, and a plurality of window holes are formed on the electrode layer. A second ceramic sheet is stacked to form an integral structure, a semiconductor pellet is connected to the electrode layer through each window hole, a cap sheet is stacked on top of this to seal the semiconductor pellet, and the stacked sheets are then 1. A method for assembling a semiconductor device, which comprises separating into ceramic-sealed semiconductor devices including individual pellets by laser scribing. 2. The method for assembling a semiconductor device according to claim 1, wherein the semiconductor pellet is connected to an electrode by face-down bonding.
JP62292007A 1987-11-20 1987-11-20 Assembly of semiconductor device Pending JPH01134956A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62292007A JPH01134956A (en) 1987-11-20 1987-11-20 Assembly of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62292007A JPH01134956A (en) 1987-11-20 1987-11-20 Assembly of semiconductor device

Publications (1)

Publication Number Publication Date
JPH01134956A true JPH01134956A (en) 1989-05-26

Family

ID=17776322

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62292007A Pending JPH01134956A (en) 1987-11-20 1987-11-20 Assembly of semiconductor device

Country Status (1)

Country Link
JP (1) JPH01134956A (en)

Cited By (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5729437A (en) * 1994-06-22 1998-03-17 Seiko Epson Corporation Electronic part including a thin body of molding resin
EP0997934A2 (en) * 1998-08-26 2000-05-03 Elliott Industries Limited An electronic component package assembly and method of manufacturing the same
WO2000076038A1 (en) * 1999-06-04 2000-12-14 Bandwidth9, Inc. Hermetically sealed semiconductor laser device
US6268236B1 (en) 1999-03-30 2001-07-31 Mitsubishi Denki Kabushiki Kaisha Method of manufacturing a semiconductor device having a package structure, and semiconductor device manufactured thereby
NL1016334C2 (en) * 2000-10-05 2002-04-08 Boschman Tech Bv A laser cutting method for a composite integrated circuit structure includes measuring the radiation emitted during cutting with a light-sensitive element and adjusting the power of the laser when a material transition is detected
JP2002118191A (en) * 2000-10-10 2002-04-19 Sanyo Electric Co Ltd Semiconductor device and method of manufacturing the same
WO2002029853A3 (en) * 2000-10-05 2002-08-08 Boschman Tech Bv Method for cutting a composite structure comprising one or more electronic compnents using a laser
FR2839812A1 (en) * 2002-05-17 2003-11-21 Atmel Grenoble Sa Method for collective manufacture of components for optical filtering, and wafer comprising such components
EP1120823A3 (en) * 2000-01-28 2004-01-02 NEC Compound Semiconductor Devices, Ltd. Semiconductor device substrate and method of manufacturing semiconductor device
DE19964316B4 (en) * 1999-03-30 2006-11-23 Mitsubishi Denki K.K. Semiconductor device manufacturing method for e.g. GaAs FET involves sticking chips to substrate, sticking lid to substrate and separating chips along adjoining areas
US7288758B2 (en) 1998-11-25 2007-10-30 Rohm And Haas Electronic Materials Llc Wafer-level optoelectronic device substrate
DE19856331B4 (en) * 1998-12-07 2009-01-02 Robert Bosch Gmbh Method for encasing electronic components
US20110291529A1 (en) * 2009-02-25 2011-12-01 Masashi Numata Bonded glass cutting method, package manufacturing method, package, piezoelectric vibrator, oscillator, electronic device, and radio-controlled timepiece

Cited By (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5729437A (en) * 1994-06-22 1998-03-17 Seiko Epson Corporation Electronic part including a thin body of molding resin
EP0997934A2 (en) * 1998-08-26 2000-05-03 Elliott Industries Limited An electronic component package assembly and method of manufacturing the same
EP0997934A3 (en) * 1998-08-26 2002-09-04 Elliott Industries Limited An electronic component package assembly and method of manufacturing the same
US7348550B2 (en) 1998-11-25 2008-03-25 Rohm And Haas Electronic Materials Llc Optoelectronic component with front to side surface electrical conductor
US7288758B2 (en) 1998-11-25 2007-10-30 Rohm And Haas Electronic Materials Llc Wafer-level optoelectronic device substrate
US7291833B2 (en) 1998-11-25 2007-11-06 Rohm And Haas Electronic Materials Llc Optoelectronic component
US7355166B2 (en) 1998-11-25 2008-04-08 Rohm And Haas Electronic Materials Llc Optoelectronic component having electrical connection and formation method thereof
DE19856331B4 (en) * 1998-12-07 2009-01-02 Robert Bosch Gmbh Method for encasing electronic components
US6268236B1 (en) 1999-03-30 2001-07-31 Mitsubishi Denki Kabushiki Kaisha Method of manufacturing a semiconductor device having a package structure, and semiconductor device manufactured thereby
US6621161B2 (en) 1999-03-30 2003-09-16 Mitsubishi Denki Kabushiki Kaisha Semiconductor device having a package structure
DE19959938C2 (en) * 1999-03-30 2002-10-31 Mitsubishi Electric Corp Manufacturing method of a semiconductor device having a package structure
DE19964316B4 (en) * 1999-03-30 2006-11-23 Mitsubishi Denki K.K. Semiconductor device manufacturing method for e.g. GaAs FET involves sticking chips to substrate, sticking lid to substrate and separating chips along adjoining areas
WO2000076038A1 (en) * 1999-06-04 2000-12-14 Bandwidth9, Inc. Hermetically sealed semiconductor laser device
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