JPH01133828U - - Google Patents
Info
- Publication number
- JPH01133828U JPH01133828U JP3084388U JP3084388U JPH01133828U JP H01133828 U JPH01133828 U JP H01133828U JP 3084388 U JP3084388 U JP 3084388U JP 3084388 U JP3084388 U JP 3084388U JP H01133828 U JPH01133828 U JP H01133828U
- Authority
- JP
- Japan
- Prior art keywords
- latch circuits
- circuit
- data
- signal
- output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 3
Landscapes
- Multi Processors (AREA)
- Information Transfer Systems (AREA)
Description
第１図は本考案の原理構成を示す図、第２図は
本考案の一実施例を示す回路図、第３図は本考案
の一実施例のタイムチヤート、第４図は本考案の
デコータの真理値表、第５図は従来の一実施例を
示す回路図、第６図は従来の一実施例のタイムチ
ヤート、を示す。
図中、１〜Ｎはラツチ回路、１０はロードタイ
ミング回路、２０は選択回路、である。
Fig. 1 is a diagram showing the principle configuration of the invention, Fig. 2 is a circuit diagram showing an embodiment of the invention, Fig. 3 is a time chart of an embodiment of the invention, and Fig. 4 is a decoder of the invention. 5 is a circuit diagram showing a conventional embodiment, and FIG. 6 is a time chart of a conventional embodiment. In the figure, 1 to N are latch circuits, 10 is a load timing circuit, and 20 is a selection circuit.
Claims (1)
個のラツチ回路（１〜Ｎ）と、クロツク信号とロ
ード信号が入力され前記のＮ個のラツチ回路（１
〜Ｎ）をロードするタイミングを制御するロード
タイミング回路１０と、前記のＮ個のラツチ回路
（１〜Ｎ）の出力を制御する選択回路２０とを備
え、前記Ｎ個のラツチ回路（１〜Ｎ）に記憶され
たデータを制御信号により順次選択をして直列に
出力することを特徴とするデータ直列出力回路。 N for storing data D0 to Dn −1 of parallel signals
The clock signal and load signal are input to the N latch circuits (1 to N).
~N); and a selection circuit 20 that controls the outputs of the N latch circuits (1~N). 1. A data serial output circuit characterized in that the data stored in the circuit (1) are sequentially selected by a control signal and output in series.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3084388U JPH01133828U (en) | 1988-03-07 | 1988-03-07 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3084388U JPH01133828U (en) | 1988-03-07 | 1988-03-07 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01133828U true JPH01133828U (en) | 1989-09-12 |
Family
ID=31256257
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3084388U Pending JPH01133828U (en) | 1988-03-07 | 1988-03-07 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01133828U (en) |
-
1988
- 1988-03-07 JP JP3084388U patent/JPH01133828U/ja active Pending
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPH01133828U (en) | ||
| JPH01151500U (en) | ||
| JPH03115450U (en) | ||
| JPH01162392U (en) | ||
| JPH01120677U (en) | ||
| JPS6347625U (en) | ||
| JPS60102690U (en) | Radiation measuring instrument noise prevention circuit | |
| JPS63149643U (en) | ||
| JPH0319972U (en) | ||
| JPH0218149U (en) | ||
| JPS6324795U (en) | ||
| JPH0260331U (en) | ||
| JPS63118653U (en) | ||
| JPS6251598U (en) | ||
| JPS6364129U (en) | ||
| JPS62164422U (en) | ||
| JPH01108629U (en) | ||
| JPH01151630U (en) | ||
| JPH036325U (en) | ||
| JPH0486346U (en) | ||
| JPS60164244U (en) | analog input device | |
| JPS6151546U (en) | ||
| JPS59166191U (en) | Clock with lighting indicator lamp | |
| JPH01149129U (en) | ||
| JPH01175023U (en) |