JPH01133354A - Semiconductor integrated circuit and manufacture thereof - Google Patents
Semiconductor integrated circuit and manufacture thereofInfo
- Publication number
- JPH01133354A JPH01133354A JP29241887A JP29241887A JPH01133354A JP H01133354 A JPH01133354 A JP H01133354A JP 29241887 A JP29241887 A JP 29241887A JP 29241887 A JP29241887 A JP 29241887A JP H01133354 A JPH01133354 A JP H01133354A
- Authority
- JP
- Japan
- Prior art keywords
- lower electrode
- region
- conductivity type
- thin film
- dielectric thin
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims description 12
- 238000004519 manufacturing process Methods 0.000 title claims description 11
- 239000010408 film Substances 0.000 claims abstract description 28
- 238000009792 diffusion process Methods 0.000 claims abstract description 22
- 239000010409 thin film Substances 0.000 claims abstract description 20
- 238000000151 deposition Methods 0.000 claims abstract description 4
- 238000000034 method Methods 0.000 claims description 29
- 239000003990 capacitor Substances 0.000 claims description 19
- 239000000758 substrate Substances 0.000 claims description 14
- 238000002955 isolation Methods 0.000 claims description 11
- 239000012535 impurity Substances 0.000 claims description 7
- 229910052581 Si3N4 Inorganic materials 0.000 abstract description 6
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 abstract description 5
- 229910052782 aluminium Inorganic materials 0.000 abstract description 5
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 abstract description 4
- 229910052698 phosphorus Inorganic materials 0.000 abstract description 4
- 239000011574 phosphorus Substances 0.000 abstract description 4
- 229910052710 silicon Inorganic materials 0.000 abstract description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 3
- 239000010703 silicon Substances 0.000 abstract description 3
- 238000005121 nitriding Methods 0.000 abstract 1
- 238000000059 patterning Methods 0.000 abstract 1
- 238000004886 process control Methods 0.000 abstract 1
- 230000015572 biosynthetic process Effects 0.000 description 7
- 238000010438 heat treatment Methods 0.000 description 7
- 150000004767 nitrides Chemical class 0.000 description 7
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 5
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 4
- 229910052796 boron Inorganic materials 0.000 description 4
- 238000000926 separation method Methods 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 238000000605 extraction Methods 0.000 description 3
- 230000003321 amplification Effects 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 230000006866 deterioration Effects 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 238000003199 nucleic acid amplification method Methods 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 229910052787 antimony Inorganic materials 0.000 description 1
- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical compound [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 229920006395 saturated elastomer Polymers 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
- 235000012431 wafers Nutrition 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Landscapes
- Semiconductor Integrated Circuits (AREA)
- Bipolar Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
（イ）産業上の利用分野
本発明はイオン注入法による抵抗素子を組み込んだ半導
体集積回路の、ＮＰＮ）ランジスタのｈ■制御を容易な
らしめた製造方法に間する。DETAILED DESCRIPTION OF THE INVENTION (A) Field of Industrial Application The present invention provides a manufacturing method that facilitates the h-control of an NPN transistor in a semiconductor integrated circuit incorporating a resistance element formed by ion implantation.
（ロ）従来の技術
バイポーラ型ＩＣは、フレフタとなる半導体層表面にベ
ース・エミッタを２重拡散して形成した縦型のＮＰＮト
ランジスタを主体として構成されている。その為、前部
ＮＰＮトランジスタを製造するベース及びエミッタ拡散
工程は必要不可欠の工程であり、コレクタ直列抵抗を低
減する為の高濃度埋込層形成工程やエピタキシャル層成
長工程、各素子を接合分離する為の分離領域形成工程や
電気的接続の為の電極形成工程等と並んでバイポーラ型
ＩＣを製造するのに欠かせない工程（基本工程）である
。(b) Conventional technology A bipolar IC is mainly composed of a vertical NPN transistor formed by doubly diffusing a base and an emitter on the surface of a semiconductor layer serving as a flip-flop. Therefore, the base and emitter diffusion process for manufacturing the front NPN transistor is an essential process, as well as the high concentration buried layer formation process and epitaxial layer growth process to reduce the collector series resistance, and the junction isolation of each element. This is an indispensable process (basic process) for manufacturing bipolar ICs, along with the isolation region formation process for electrical connection and the electrode formation process for electrical connection.
一方、回路的な要求から他の素子、例えばＰＮＰトラン
ジスタ、抵抗、容量、ツェナーダイオード等を同一基板
上に組み込みたい要求がある。この場合、工程の簡素化
という点から可能な限り前記基本工程を流用した方が好
ましいことは言うまでもない。しかしながら、前記ベー
ス及びエミッタ拡１１に工程はＮＰＮトランジスタの特
性を最重要視して諸条件が設定される為、前記基本工程
だけでは集積化が困難な場合が多い。そこで、基本的な
ＮＰＮ ）ランジスタの形成を目的とせず、他の素子を
組み込む為もしくは他素子の特性を向上することを目的
として新規な工程を追加することがある。例えば前記エ
ミッタ拡散によるカソード領域とでツェナーダイオード
のツェナー電圧を制御するアノード領域を形成する為の
Ｐ１拡散工程、ベース領域とは比抵抗が異る抵抗領域を
形成する為のＲ拡散工程やインプラ抵抗形成工程、ＭＯ
Ｓ型よりも大きな容量が得られる窒化膜容量を形成する
為の窒化膜形成工程、ＮＰＮ トランジスタのコレクタ
直列抵抗を更に低減する為のコレクタ低抵抗領域形成工
程等がそれであり、全てバイポーラＩＣの用途や目的及
びコスト的な面から検討して追加するか否かが決定され
る工程（オブション工程）である。On the other hand, due to circuit requirements, there is a demand for incorporating other elements such as PNP transistors, resistors, capacitors, Zener diodes, etc. on the same substrate. In this case, it goes without saying that it is preferable to utilize the basic steps as much as possible in terms of process simplification. However, since the process conditions for the base and emitter expansion 11 are set with the utmost importance placed on the characteristics of the NPN transistor, it is often difficult to integrate the base and emitter expansion 11 using only the basic process. Therefore, a new process may be added not for the purpose of forming a basic NPN transistor, but for the purpose of incorporating other elements or improving the characteristics of other elements. For example, the P1 diffusion process to form an anode region that controls the Zener voltage of the Zener diode with the cathode region by the emitter diffusion, the R diffusion process to form a resistance region with a different resistivity from the base region, and the implant resistance. Forming process, M.O.
These include the nitride film formation process to form a nitride film capacitor that provides a larger capacitance than S-type, and the collector low resistance region formation process to further reduce the collector series resistance of NPN transistors, all of which are used for bipolar ICs. This is a step (optional step) in which it is decided whether or not to add it after consideration from the viewpoint of purpose, cost, and cost.
上記オブション工程を利用して形成したＭＩＳ型容量を
第３図に示す、同図において、（１）はＰ型半導体基板
、（２）はＮ型エピタキシャル層、（３）はＮ０型埋込
層、（４）はＰ＋型分離領域、（５）はアイランド、（
６）はエミッタ拡散によるＮ＋型の下部電極領域、（７
）は高誘電率絶縁体としてのシリコン窒化膜（Ｓｉ、Ｎ
４）、（８）はアルミニウム材料から成る上部電極、（
９）は酸化膜、（１０）は電極である。尚、窒化膜を利
用したＭＩＳ型容量としては、例えば特開昭６０−２４
４０５６号公報に記載されている。The MIS type capacitor formed using the above optional process is shown in Figure 3. In the figure, (1) is a P-type semiconductor substrate, (2) is an N-type epitaxial layer, and (3) is an N0-type buried layer. , (4) is a P+ type isolation region, (5) is an island, (
6) is an N+ type lower electrode region by emitter diffusion, (7
) is a silicon nitride film (Si, N
4), (8) are upper electrodes made of aluminum material, (
9) is an oxide film, and (10) is an electrode. Incidentally, as an MIS type capacitor using a nitride film, for example, Japanese Patent Application Laid-Open No. 60-24
It is described in Publication No. 4056.
（ハ）発明が解決しようとする問題点
しかしながら、従来のＭＩＳ型容量は下部電極としてＮ
ＰＮ トランジスタのエミッタ拡散工程を利用している
為、エミッタ領域形成用のＮ型不純物をデボした後に窒
化膜を形成し、その後でＮ型不純物のドライブインを行
わなければならない。(c) Problems to be solved by the invention However, the conventional MIS type capacitor uses N as the lower electrode.
Since the emitter diffusion process of a PN transistor is used, a nitride film must be formed after N-type impurities for forming an emitter region are deposited, and then the N-type impurities must be driven in.
すると、窒化膜のデポ時に使用する８００°Ｃ前後の熱
処理がエミッタ領域を再拡散させる為、ＮＰＮトランジ
スタのｈ□（電流増幅率）のばらつきが大きく、ｈａｔ
のフントロールが難しい欠点があった。Then, the heat treatment at around 800°C used when depositing the nitride film re-diffuses the emitter region, resulting in large variations in the h□ (current amplification factor) of the NPN transistor.
It had the disadvantage that it was difficult to hunt down.
また、窒化膜の形成に必要なオブション工程を追加した
か否かでエミッタ領域の熱処理条件を変更する必要があ
る為、機種別の工程管理が必要であり、管理の共通化が
できない欠点があった。In addition, it is necessary to change the heat treatment conditions for the emitter region depending on whether or not an optional process necessary for forming the nitride film is added, so process management is required for each model, and there is a drawback that management cannot be standardized. Ta.
（ニ）問題点を解決するための手段
本発明は衛士した欠点に鑑みてなされ、ＭＩＳ型容量を
組み込んだ半導体集積回路の製造方法において、アイラ
ンド表面にＮＰＮ）ランジスタのエミッタ拡散に先立っ
てＭＩＳ型容量の下部電極領域（２６）と誘電体薄膜（
２８）を形成し、その後ＮＰＮトランジスタのエミッタ
拡散を行うと共に、下部電極領域（２６）にオーミック
コンタクトする下部電極（３０）を櫛歯状に配設したこ
゛とを特徴とする。(d) Means for Solving the Problems The present invention has been made in view of the serious drawbacks, and in a method of manufacturing a semiconductor integrated circuit incorporating an MIS type capacitor, the MIS type capacitor is The lower electrode area of the capacitor (26) and the dielectric thin film (
28) is formed, and then the emitter of the NPN transistor is diffused, and a lower electrode (30) is arranged in a comb-like shape to make ohmic contact with the lower electrode region (26).
（ホ）作、用
本発明によれば、下部電極としてエミッタ拡散を利用せ
ずエミッタ領域（３０）形成前に形成した領域を使用し
、窒化膜をデポした後にエミッタ拡散を行うので、エミ
ッタ領域（３０）形成以後のＮＰＮトランジスタのｈａ
ｔに影響する熱処理工程を排除することができる。(E) Operation and Use According to the present invention, the region formed before forming the emitter region (30) is used as the lower electrode without using emitter diffusion, and the emitter diffusion is performed after depositing the nitride film. (30) ha of NPN transistor after formation
A heat treatment step that affects t can be eliminated.
また、下部電極領域（２６）の形成をプロセスの前半に
配置した為、下部電極領域（２６）表面の不純物濃度が
低下して下部電極（３０）の取出し抵抗が増大するもの
の、本願によれば下部電極（３０）を櫛歯状に配設した
ので下部電極（３０）の取出し抵抗を減じることができ
る。Furthermore, since the formation of the lower electrode region (26) is arranged in the first half of the process, the impurity concentration on the surface of the lower electrode region (26) decreases and the extraction resistance of the lower electrode (30) increases. Since the lower electrode (30) is arranged in a comb-teeth shape, the resistance to take out the lower electrode (30) can be reduced.
（へ）実施例
以下、本発明の一実施例を図面を参照しながら詳細に説
明する。(F) Example Hereinafter, an example of the present invention will be described in detail with reference to the drawings.
第１図Ａ及び第１図Ｂは本発明の半導体集積回路を示し
、（２１）はＰ型シリコン基板、（２２）は基板（２１
）表面に設けたＮ′″型の埋込層、（２３）は基板（２
１）全面の上に積層して形成したＮ型エピタキシャル層
、（２４）はエピタキシャル層（２３）を貫通するＰ＋
型の分離領域、（２５）は分離領域（２４）によってエ
ピタキシャル層（２３）を島状に形成したアイランド、
（２６）はアイランド（２５）表面に形成したＰ型又は
Ｎ型のＭＩＳ型容量の下部電極領域、（２７）はエピタ
キシャル層（２３）表面を覆うシリコン酸化膜（ＳｉＯ
＊）、（２８）は露出させた下部電極領域（２６）の表
面に堆積して形成したシリコン窒化膜（ｓｉｓＮａ）か
ら成る誘電体薄膜、（２９）は下部電極領域（２６）の
表面に設けたアルミニウム層から成る上部電極、（３０
）は下部電極領域（２６）とコンタクトホール（３１）
を介してオーミックコンタクトする下部電極である。1A and 1B show the semiconductor integrated circuit of the present invention, (21) is a P-type silicon substrate, (22) is a substrate (21).
) N′″ type buried layer provided on the surface, (23) is the substrate (2
1) N-type epitaxial layer laminated on the entire surface, (24) is a P+ layer that penetrates the epitaxial layer (23)
The isolation region of the mold (25) is an island in which the epitaxial layer (23) is formed into an island shape by the isolation region (24);
(26) is the lower electrode region of the P-type or N-type MIS type capacitor formed on the surface of the island (25), and (27) is the silicon oxide film (SiO2) covering the surface of the epitaxial layer (23).
*), (28) is a dielectric thin film made of a silicon nitride film (sisNa) deposited on the surface of the exposed lower electrode region (26), and (29) is a dielectric thin film formed on the surface of the lower electrode region (26). upper electrode consisting of a layer of aluminum (30
) are the lower electrode area (26) and the contact hole (31)
This is the lower electrode that makes ohmic contact through the .
下部電極領域（２６）は−例として分離領域（２４）形
成工程を利用したものを示しである０分離領域（２４）
は高不純物濃度拡散によって形成するものの、かなり深
く拡散する為とプロセスの前半に形成する為に表面濃度
が低下してしまう、すると、従来例の様にエミッタ拡散
を使用したものよりは下部電極の取出し抵抗が増大し、
ＭＩＳ型容量の電圧依存性、周波数依存性、ヒステリシ
ス特性共に劣化してしまう、その為、本願の特徴とする
如く下部電極（３０）を櫛歯状に配設することで下部電
極（３０）の取出し抵抗を減少させ、緒特性の劣化を防
止する。The lower electrode region (26) is an example of the isolation region (24) forming process.
Although it is formed by high impurity concentration diffusion, the surface concentration decreases because it is diffused quite deeply and because it is formed in the first half of the process. Removal resistance increases,
The voltage dependence, frequency dependence, and hysteresis characteristics of the MIS type capacitor deteriorate. Therefore, by arranging the lower electrode (30) in a comb-like shape as a feature of the present application, the lower electrode (30) can be improved. Reduces extraction resistance and prevents deterioration of cable characteristics.
そして本願の構造によれば、分離領域（２４）を利用し
てＭＩＳ型容量の下部電極領域（２６）を形成すること
によってエミッタ拡散の前に誘電体薄膜（２８）のデポ
ジットを行うことが可能になる。According to the structure of the present application, by forming the lower electrode region (26) of the MIS type capacitor using the isolation region (24), it is possible to deposit the dielectric thin film (28) before emitter diffusion. become.
以下、本願の製造方法を第２図Ａ乃至第２図Ｆを用いて
説明する。Hereinafter, the manufacturing method of the present application will be explained using FIGS. 2A to 2F.
先ず第２図Ａに示す如く、Ｐ型のシリコン半導体基板（
２１）の表面にアンチモン（Ｓｂ）又はヒ素（Ａｓ）等
のＮ型不純物を選択的にドープしてＮ＋型埋込層（２２
）を形成し、基板（２１）全面に厚さ５〜１０μのＮ型
のエピタキシャル層（２３）を積層する。First, as shown in FIG. 2A, a P-type silicon semiconductor substrate (
The surface of the N+ type buried layer (22) is selectively doped with N type impurities such as antimony (Sb) or arsenic (As).
), and an N-type epitaxial layer (23) with a thickness of 5 to 10 μm is laminated on the entire surface of the substrate (21).
次に第２図Ｂに示す如く、基板（２１）表面からボロン
（Ｂ）を選択的に拡散することによって、埋込層（２２
）を夫々取囲むようにエピタキシャル層（２３）を貫通
するＰ＋型の分離領域（２４）を形成する０分離領域（
２４）で囲まれたエピタキシャル層（２３）が夫々の回
路素子を形成する為のアイランド（２５）となる。と同
時に、分離領域（２４）拡散工程のボロン（Ｂ）をアイ
ランド（２５）表面の埋込層（２２）に対応する領域に
も拡散し、エピタキシャル層（２３）表面から埋込層（
２２）に到達する下部電極領域（２６）を形成する。下
部電極領域（２６）の底部は全て埋込層（２２）と接す
る様に形成し、埋込層（２２）によって下部電極領域（
２６）を基板（２１）の接地電位から電気的に絶縁する
。その為、ＭＩＳ型容量は電気的に独立するので、回路
構成上の制約が無い。分離領域（２４）の拡散は飽和拡
散で行うが、エピタキシャル層（２３）を貫通させるの
で下部電極領域（２６）の表面濃度は１０’″ａｔＯＩ
ＩＩＳ−ｃＩＴＩ−ｆｆｉ前後となる。Next, as shown in FIG. 2B, by selectively diffusing boron (B) from the surface of the substrate (21), the buried layer (22
) to form P+ type isolation regions (24) penetrating the epitaxial layer (23) so as to surround the
The epitaxial layer (23) surrounded by 24) becomes an island (25) for forming each circuit element. At the same time, boron (B) from the separation region (24) diffusion process is also diffused into the region corresponding to the buried layer (22) on the surface of the island (25), and the buried layer (22) is diffused from the surface of the epitaxial layer (23).
A lower electrode region (26) is formed that reaches 22). The entire bottom of the lower electrode region (26) is formed so as to be in contact with the buried layer (22), and the lower electrode region (26) is formed so as to be in contact with the buried layer (22).
26) is electrically insulated from the ground potential of the substrate (21). Therefore, since the MIS type capacitor is electrically independent, there are no restrictions on the circuit configuration. The separation region (24) is diffused by saturated diffusion, but since it penetrates the epitaxial layer (23), the surface concentration of the lower electrode region (26) is 10'''atOI.
It will be around IIS-cITI-ffi.
次に第２図Ｃに示す如く、下部電極領域（２６）を形成
したアイランド（２５）とは別のアイランド（２５）の
表面にボロン（Ｂ）を選択的にイオン注入又は拡散する
ことによってＮＰＮトランジスタのベースとなるベース
領域（３２）を形成する。この時下部電極領域（２６）
表面にもボロン（Ｂ）を拡散すれば、下部電極領域（２
６）の表面濃度を向上することができる。Next, as shown in FIG. 2C, boron (B) is selectively ion-implanted or diffused into the surface of an island (25) different from the island (25) on which the lower electrode region (26) is formed. A base region (32) that will become the base of the transistor is formed. At this time, the lower electrode area (26)
If boron (B) is also diffused on the surface, the lower electrode region (2
6) The surface concentration can be improved.
次に第２図りに示す如く、エピタキシャル層（２３）表
面に形成した熱酸化又はＣＶＤ酸化膜（２７）を選択的
にエツチング除去して下部電極領域（２６）表面の一部
を露出させ、エピタキシャル層（２３）全面に常圧ＣＶ
Ｄ法等の技術を用いて膜厚数百〜千般百人のシリコン窒
化膜（ｓｉｓＮａ）を堆積させる。シリコン窒化膜はシ
リコン酸化膜よりも高い誘電率を示すので、大容量を形
成することが可能である。そして、前記シリコン窒化膜
表面に周知のレジストパターンを形成し、ＲＷＥ等のド
ライエッチ技術を利用して前記露出した下部電極領域（
２６）の表面を覆う誘電体薄膜（２８）を形成する。そ
の後、誘電体薄膜（２８）を覆う様にＣＶＤ法による酸
化膜（２７）を堆積させる。Next, as shown in the second diagram, the thermal oxidation or CVD oxide film (27) formed on the surface of the epitaxial layer (23) is selectively etched away to expose a part of the surface of the lower electrode region (26), and Normal pressure CV on the entire layer (23)
Using a technique such as the D method, a silicon nitride film (sisNa) is deposited to a thickness of several hundred to several hundred. Since a silicon nitride film exhibits a higher dielectric constant than a silicon oxide film, it is possible to form a large capacitance. Then, a well-known resist pattern is formed on the surface of the silicon nitride film, and a dry etching technique such as RWE is used to form the exposed lower electrode region (
A dielectric thin film (28) is formed to cover the surface of (26). Thereafter, an oxide film (27) is deposited by CVD so as to cover the dielectric thin film (28).
次に第２図Ｅに示す如く、今度はＮＰＮトランジスタの
ベース領域（３２）表面とアイランド（２５）表面の酸
化膜（２７）を開孔し、この酸化膜（２７）をマスクと
してリン（Ｐ）を選択拡散することによりＮ′″型のエ
ミッタ領域（３３）とフレフタコンタクト領域（３４）
を形成する。Next, as shown in FIG. 2E, holes are opened in the oxide film (27) on the surface of the base region (32) and the surface of the island (25) of the NPN transistor, and using this oxide film (27) as a mask, ) by selectively diffusing the
form.
次に第２図Ｆに示す如く、酸化膜（２７）上にネガ又は
ポジ型のフォトレジストによるレジストパターンを形成
し、ウェット又はドライエツチングによって誘電体薄膜
（２８）上の酸化膜（２７）を除去し、さらに酸化膜（
２７）の所望の部分に電気的接続の為のコンタクトホー
ル（３１）を開孔する。そして、エピタキシャルＪｆｆ
ｌ（２３）全面に周知の蒸着又はスパッタ技術によりア
ルミニウム層を形成し、このアルミニウム層を再度バタ
ーニングすることによって所望形状の電極（３５）と誘
電体薄膜（２８）上の上部電極（２９）及び下部電極（
３０）を形成する。Next, as shown in FIG. 2F, a resist pattern of negative or positive photoresist is formed on the oxide film (27), and the oxide film (27) on the dielectric thin film (28) is removed by wet or dry etching. Remove the oxide film (
27) A contact hole (31) for electrical connection is opened in a desired portion. And epitaxial Jff
An aluminum layer is formed on the entire surface of l (23) by a well-known vapor deposition or sputtering technique, and this aluminum layer is patterned again to form an electrode (35) of a desired shape and an upper electrode (29) on the dielectric thin film (28). and the lower electrode (
30).
衛士した本願の製造方法によれば、ＭＩＳ型容量の下部
電極領域（２６）として分離領域（２４）の拡散工程に
よって形成した拡散領域を使用したので、誘電体薄膜（
２８）の製造工程をエミッタ拡散工程の前に配置するこ
とができる。すると、エミッタ領域（３３）形成用のリ
ン（Ｐ）のデポジットからリン（Ｐ）のドライブインの
前にＭＩＳ型容量形成の為の熱処理を配置する必要が無
く、デポジットによってリン（Ｐ）が初期拡散された状
態から即ＮＰＮトランジスタのす、（’Ｍ流増幅率）コ
ントロールの為の熱処理（ドライブイン）工程を行うこ
とができる。その為、ＮＰＮトランジスタのｈ□のばら
つきが少く、ＭＩＳ型容量を組み込んだことによるｈＦ
Ｉコントロールの難しさを解消できる。また、ＭＩＳ型
容量を組み込む組み込まないにかかわらずエミッタ領域
（３３）の熱処理条件を一本化することができるので、
機種別の工程管理が極めて容易になる。According to the manufacturing method of the present application, since the diffusion region formed by the diffusion process of the isolation region (24) is used as the lower electrode region (26) of the MIS type capacitor, the dielectric thin film (
The manufacturing step 28) can be placed before the emitter diffusion step. Then, there is no need to perform heat treatment for forming the MIS type capacitor from the phosphorus (P) deposit for forming the emitter region (33) to the phosphorus (P) drive-in, and the phosphorus (P) is initialized by the deposit. A heat treatment (drive-in) process for controlling the NPN transistor ('M current amplification factor) can be performed immediately from the diffused state. Therefore, there is little variation in h□ of NPN transistors, and hF by incorporating MIS type capacitance
It can solve the difficulty of I-control. Furthermore, the heat treatment conditions for the emitter region (33) can be unified regardless of whether MIS type capacitance is incorporated.
Process management by model becomes extremely easy.
本願の下部電極領域（２６）は様々な実施態様をとる０
例えば上下分離技術を使用したもの、上下分離技術の上
側の拡散領域だけを使用したもの、−ベース領域（３２
）より深く高不純物濃度でツェナーダイオードのアノー
ド形成用のＰ＋型拡散領域を使用したもの、エピタキシ
ャル層（２３）表面から埋込層（２２）まで達するＮＰ
Ｎ トランジスタのコレクタ抵抗低減を目的としたＮ型
のコレクタ低抵抗領域を使用したもの等である。いずれ
もエミッタ拡散の前に行うので、その表面濃度はエミッ
タ領域（３３）よりも低下してしまう。The lower electrode region (26) of the present application takes various embodiments.
For example, one using upper and lower separation technology, one using only the upper diffusion region of upper and lower separation technology, - base region (32
) using a P+ type diffusion region for forming the anode of a Zener diode with a deeper impurity concentration, NP reaching from the surface of the epitaxial layer (23) to the buried layer (22)
These include those using an N-type collector low resistance region for the purpose of reducing collector resistance of an N transistor. Since both are performed before emitter diffusion, the surface concentration thereof will be lower than that of the emitter region (33).
（ト）発明の詳細
な説明した如く、本発明によればＭＩＳＪＩ容縫をオプ
ションデバイスとして追加したことによるＮＰＮ トラ
ンジスタのｈＦＦのばらつきが僅と無い、ＮＰＮトラン
ジスタのｈＦえのコントロールが極めて容易な半導体集
積回路の製造方法を提供できる利点を有する。また、Ｍ
ＩＳ型容量を組み込んだ機種とそうでない機種とでエミ
ッタ領域（３３）の処理条件を一本化できるので、機種
別の工程管理を簡略化でき、さらには異る機種のウェハ
ーを同一拡散炉内で熱処理するといった多機種少量生産
が可能となる利点をも有する。(g) As described in detail, according to the present invention, by adding MISJI as an optional device, there is little variation in hFF of NPN transistors, and the hF of NPN transistors can be extremely easily controlled. It has the advantage of providing a method for manufacturing integrated circuits. Also, M
Processing conditions for the emitter area (33) can be unified for models with IS-type capacitance and models without, simplifying process management for each model, and even allowing wafers of different models to be placed in the same diffusion furnace. It also has the advantage of being able to produce a wide variety of products in small quantities by heat treatment.
そして本願によれば、下部電極（３０）を櫛歯状とする
ことにより下部電極（３０）の取出し抵抗を低減したの
で、下部電極領域（２６）として表面濃度がエミッタ領
域（３３）より低い拡散領域を使用したにもかかわらず
、ＭＩＳ型容量の特性劣化を防止できる利点をも有する
。According to the present application, the extraction resistance of the lower electrode (30) is reduced by forming the lower electrode (30) into a comb-like shape, so the lower electrode region (26) has a lower surface concentration than the emitter region (33). It also has the advantage that deterioration of the characteristics of the MIS type capacitor can be prevented even though the area is used.
第１図Ａ及び第１図Ｂは夫々本発明を説明する為の平面
図及びＡＡ線断面図、第２図Ａ乃至第２図Ｆは夫々本発
明の製造方法を説明する為の断面図、第３図は従来例を
説明する為の断面図である。
（２１）は半導体基板、 （２６）は下部電極領域、〈
２８〉は誘電体薄膜、 （２９）は上部電極、 （３０
）は下部電極である。1A and 1B are a plan view and a sectional view taken along line AA, respectively, for explaining the present invention, and FIGS. 2A to 2F are sectional views, respectively, for explaining the manufacturing method of the present invention, FIG. 3 is a sectional view for explaining a conventional example. (21) is the semiconductor substrate, (26) is the lower electrode region,
28〉 is a dielectric thin film, (29) is an upper electrode, (30
) is the bottom electrode.
Claims (2)
ピタキシャル層と、前記基板表面に形成した逆導電型の
埋込層と、この埋込層を夫々取囲むようにエピタキシャ
ル層を分離する一導電型の分離領域と、該分離領域によ
って複数個形成したアイランドと、このアイランド表面
に縦型バイポーラトランジスタのエミッタ拡散に先立っ
て形成した一導電型又は逆導電型のＭＩＳ型容量の下部
電極領域と、該下部電極領域を覆う様に前記エミッタ拡
散に先立って堆積して形成した誘電体薄膜と、前記誘電
体薄膜の表面にオーミックコンタクトするＭＩＳ型容量
の下部電極と、前記誘電体薄膜を挾んで前記下部電極領
域と対向するように前記誘電体薄膜上に配設した上部電
極とを具備し、前記下部電極を櫛歯状に配設したことを
特徴とする半導体集積回路。(1) An epitaxial layer of the opposite conductivity type formed on a semiconductor substrate of one conductivity type, a buried layer of the opposite conductivity type formed on the surface of the substrate, and the epitaxial layers are separated so as to surround each of the buried layers. an isolation region of one conductivity type, a plurality of islands formed by the isolation region, and a lower electrode of an MIS type capacitor of one conductivity type or an opposite conductivity type formed on the surface of this island prior to emitter diffusion of a vertical bipolar transistor. a dielectric thin film deposited prior to the emitter diffusion to cover the lower electrode region, a lower electrode of an MIS type capacitor in ohmic contact with the surface of the dielectric thin film, and a dielectric thin film deposited to cover the lower electrode region; A semiconductor integrated circuit comprising an upper electrode disposed on the dielectric thin film so as to sandwich and face the lower electrode region, and the lower electrode is disposed in a comb-like shape.
込層を形成する工程、 前記基板の上に逆導電型のエピタキシャル層を形成する
工程、 前記エピタキシャル層を分離して複数個のアイランドを
形成する工程、 １つのアイランド表面にＭＩＳ型容量の下部電極となる
一導電型又は逆導電型の下部電極領域を形成する工程、 前記下部電極領域表面の一部の領域を露出し、前記ＭＩ
Ｓ型容量の誘電体薄膜を堆積して櫛歯状に形成する工程
、 前記誘電体薄膜を形成した後、逆導電型の不純物を選択
的に拡散することによって縦型バイポーラトランジスタ
の逆導電型のエミッタ領域を形成する工程、 全面に導電体膜を形成し、前記誘電体薄膜の上に前記Ｍ
ＩＳ型容量の上部電極を、前記下部電極領域表面には前
記下部電極領域とオーミックコンタクトする電極を櫛歯
状に配設する工程とを具備することを特徴とする半導体
集積回路の製造方法。(2) a step of forming a buried layer of an opposite conductivity type in a desired region of a semiconductor substrate of one conductivity type; a step of forming an epitaxial layer of an opposite conductivity type on the substrate; and a step of separating the epitaxial layer into a plurality of layers. a step of forming a lower electrode region of one conductivity type or an opposite conductivity type to serve as a lower electrode of a MIS type capacitor on the surface of one island; exposing a part of the surface of the lower electrode region; Said MI
A step of depositing a dielectric thin film of S-type capacitance to form a comb-teeth shape, after forming the dielectric thin film, selectively diffusing impurities of the opposite conductivity type to form the reverse conductivity type of the vertical bipolar transistor. Step of forming an emitter region: forming a conductive film on the entire surface, and forming the M on the dielectric thin film.
A method for manufacturing a semiconductor integrated circuit, comprising the step of disposing an upper electrode of an IS type capacitor in a comb-teeth shape on the surface of the lower electrode region in ohmic contact with the lower electrode region.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62292418A JP2725773B2 (en) | 1987-11-19 | 1987-11-19 | Semiconductor integrated circuit and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62292418A JP2725773B2 (en) | 1987-11-19 | 1987-11-19 | Semiconductor integrated circuit and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH01133354A true JPH01133354A (en) | 1989-05-25 |
| JP2725773B2 JP2725773B2 (en) | 1998-03-11 |
Family
ID=17781531
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62292418A Expired - Fee Related JP2725773B2 (en) | 1987-11-19 | 1987-11-19 | Semiconductor integrated circuit and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2725773B2 (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6486056B2 (en) * | 1998-05-18 | 2002-11-26 | Lsi Logic Corporation | Process for making integrated circuit structure with thin dielectric between at least local interconnect level and first metal interconnect level |
| US6974744B1 (en) | 2000-09-05 | 2005-12-13 | Marvell International Ltd. | Fringing capacitor structure |
| US6980414B1 (en) | 2004-06-16 | 2005-12-27 | Marvell International, Ltd. | Capacitor structure in a semiconductor device |
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|---|---|---|---|---|
| JPS5656681A (en) * | 1979-10-01 | 1981-05-18 | Trw Inc | Mos condenser |
| JPS58159367A (en) * | 1982-03-17 | 1983-09-21 | Matsushita Electronics Corp | Mos capacitor device |
| JPS60166155U (en) * | 1984-04-11 | 1985-11-05 | 三洋電機株式会社 | Junction type capacitor |
| JPS6113656A (en) * | 1984-06-28 | 1986-01-21 | Toshiba Corp | Manufacture of semiconductor device |
-
1987
- 1987-11-19 JP JP62292418A patent/JP2725773B2/en not_active Expired - Fee Related
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5656681A (en) * | 1979-10-01 | 1981-05-18 | Trw Inc | Mos condenser |
| JPS58159367A (en) * | 1982-03-17 | 1983-09-21 | Matsushita Electronics Corp | Mos capacitor device |
| JPS60166155U (en) * | 1984-04-11 | 1985-11-05 | 三洋電機株式会社 | Junction type capacitor |
| JPS6113656A (en) * | 1984-06-28 | 1986-01-21 | Toshiba Corp | Manufacture of semiconductor device |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6486056B2 (en) * | 1998-05-18 | 2002-11-26 | Lsi Logic Corporation | Process for making integrated circuit structure with thin dielectric between at least local interconnect level and first metal interconnect level |
| US6974744B1 (en) | 2000-09-05 | 2005-12-13 | Marvell International Ltd. | Fringing capacitor structure |
| US9017427B1 (en) | 2001-01-18 | 2015-04-28 | Marvell International Ltd. | Method of creating capacitor structure in a semiconductor device |
| US6980414B1 (en) | 2004-06-16 | 2005-12-27 | Marvell International, Ltd. | Capacitor structure in a semiconductor device |
| US7116544B1 (en) | 2004-06-16 | 2006-10-03 | Marvell International, Ltd. | Capacitor structure in a semiconductor device |
| US7578858B1 (en) | 2004-06-16 | 2009-08-25 | Marvell International Ltd. | Making capacitor structure in a semiconductor device |
| US7988744B1 (en) | 2004-06-16 | 2011-08-02 | Marvell International Ltd. | Method of producing capacitor structure in a semiconductor device |
| US8537524B1 (en) | 2004-06-16 | 2013-09-17 | Marvell International Ltd. | Capacitor structure in a semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2725773B2 (en) | 1998-03-11 |
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