JPH01133164A - Power supply circuit for memory testing device - Google Patents
Power supply circuit for memory testing deviceInfo
- Publication number
- JPH01133164A JPH01133164A JP62289452A JP28945287A JPH01133164A JP H01133164 A JPH01133164 A JP H01133164A JP 62289452 A JP62289452 A JP 62289452A JP 28945287 A JP28945287 A JP 28945287A JP H01133164 A JPH01133164 A JP H01133164A
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- Prior art keywords
- power supply
- test
- control signal
- voltage control
- signal
- Prior art date
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- 238000012360 testing method Methods 0.000 title claims abstract description 119
- 238000010248 power generation Methods 0.000 claims description 7
- 238000000034 method Methods 0.000 claims 1
- 239000003990 capacitor Substances 0.000 abstract description 10
- 238000010586 diagram Methods 0.000 description 4
- 230000004044 response Effects 0.000 description 3
- 230000002950 deficient Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 238000011835 investigation Methods 0.000 description 1
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Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、メモリ試験装置の電源回路に関し、特に、試
験を実行していない間も試験中とは別に電圧設定した電
源を被試験メモリに供給することができるメモリ試験装
置の電源回路に関する。[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a power supply circuit for a memory test device, and in particular, the present invention relates to a power supply circuit for a memory test device, and in particular, the present invention provides a power supply circuit that supplies a memory under test with a power supply set at a voltage different from that during a test even when a test is not being performed. The present invention relates to a power supply circuit for a memory testing device that can be supplied.
メモリ試験装置は被試験メモリの良否を判定する単純な
機能を有するものであり、その被試験メモリに対して、
１回毎の試験が終了もしくは中断されると電源が断たれ
、次の試験開始もしくは継続時に電源が再投入される。Memory test equipment has a simple function of determining the quality of the memory under test, and
When each test is completed or interrupted, the power is turned off, and the power is turned on again when the next test is started or continued.
電源が再投入されると、被試験メモリは以前の状態を保
持しているとは限らないため、初期化されるのが通常で
ある。When the power is turned on again, the memory under test does not necessarily retain its previous state, so it is normally initialized.
一方、被試験メモリの調査、特に不良状態を詳細に調査
する場合においては、例えば試験中に不良を検出した時
点で試験を一時停止して、その後に検出された不良状態
を多種多様な試験で詳しく調査したいという要求が生じ
る。この際には、１回毎の試験の終了もしくは中断とそ
の後の試験の開始もしくは継続の間で、被試験メモリの
状態を保持させるような電源を供給する電源回路が必要
である。第２図は、このような電源回路の一例を示すブ
ロック図である。第２図において、電源電圧制御信号選
択部１は、試験電圧制御信号ａと停止電圧制御信号すと
、試験実行中信号Ｃが入力され、試験実行中信号Ｃが試
験実行中の状態の場合は、試験電圧制御信号ａを電源電
圧制御信号ｄとして出力し、試験実行中信号Ｃが試験実
行中ではない状態の場合は、停止電圧制御信号すを電源
電圧制御信号ｄとして出力する。電源発生部３は、電源
電圧制御信号選択部１が、前述のように選択して出力す
る電源電圧制御信号ｄを入力され、これにより設定され
る電圧を有する被試験メモリ電源を被試験メモリ４に与
える。したがって、この従来のメモリ試験装置の電源回
路は、被試験メモＵ ４の試験を実行中には試験実行中
信号Ｃを試験実行中の状態にして、試験電圧制御信号ａ
で設定される電源電圧を被試験メモリ４に対して供給し
、被試験メモリ４の試験を実行していない間は試験実行
中信号Ｃを試験実行中ではない状態にして、停止電圧制
御信号すで設定される電源電圧を被試験メモリ４に対し
て供給する。これにより、被試験メモリの試験を実行し
ていない間も試験中とは別に電圧設定した電源を被試験
メモリに供給するようにして、複数回の断続的な一連の
試験を実行する際の試験中断の間でも被試験メモリの内
部状態を変化させずに保持できる。On the other hand, when investigating the memory under test, especially when investigating defective states in detail, for example, when a defective state is detected during the test, the test is paused, and then the detected faulty state is examined using a wide variety of tests. A request arises for a detailed investigation. In this case, a power supply circuit is required that supplies power to maintain the state of the memory under test between the end or interruption of each test and the start or continuation of a subsequent test. FIG. 2 is a block diagram showing an example of such a power supply circuit. In FIG. 2, the power supply voltage control signal selection unit 1 receives the test voltage control signal a and the stop voltage control signal, and then receives the test execution signal C, and when the test execution signal C is in the test execution state, , outputs the test voltage control signal a as the power supply voltage control signal d, and outputs the stop voltage control signal S as the power supply voltage control signal d when the test execution signal C indicates that the test is not being executed. The power supply generation section 3 receives the power supply voltage control signal d selected and outputted by the power supply voltage control signal selection section 1 as described above, and selects the memory under test power supply having the voltage set by the power supply voltage control signal d to the memory under test 4. give to Therefore, the power supply circuit of this conventional memory test device sets the test execution signal C to the test execution state while testing the memo under test U4, and sets the test voltage control signal a to the test execution state.
Supply the power supply voltage set by The power supply voltage set in is supplied to the memory under test 4. As a result, even when the memory under test is not being tested, a power supply with a different voltage setting is supplied to the memory under test. The internal state of the memory under test can be maintained unchanged even during interruption.
上述した従来のメモリ試験装置の電源回路、例えば第２
図に示されるようなメモリ試験装置の電源回路において
、試験実行中信号Ｃの状態により電源電圧制御信号ｄが
試験電圧制御信号ａと停止電圧制御信号すとの２値間で
切り替えられている。The power supply circuit of the conventional memory test device described above, for example, the second
In the power supply circuit of the memory test device as shown in the figure, the power supply voltage control signal d is switched between two values, a test voltage control signal a and a stop voltage control signal S, depending on the state of the test execution signal C.
このため、被試験メモリ４に供給される被試験メモリ電
源の電源電圧は、電源電圧制御信号ｄの切り替え時、急
激に変化する。これにより、被試験メモリ４の電源供給
端子の入力特性との整合の不具合などがあると、電源供
給電圧に乱れが生じて、期待されるような滑らかな電源
供給電圧の変動が行われずに被試験メモリ４の内部状態
を変化させてしまったり、過電圧により被試験メモリ４
を破損してしまう場合があるという欠点がある。Therefore, the power supply voltage of the memory under test power supply supplied to the memory under test 4 changes rapidly when the power supply voltage control signal d is switched. As a result, if there is a problem in matching the input characteristics of the power supply terminal of the memory under test 4, the power supply voltage will be disturbed, and the power supply voltage will not fluctuate as smoothly as expected. The internal state of the test memory 4 may be changed, or the memory under test 4 may be damaged due to overvoltage.
The disadvantage is that it may damage the
本発明の目的は、このような欠点を除去し、電源電圧制
御信号選択部に入力される試験実行中信号の状態の変化
に際して、被試験メモリの内部状態を変化させたり、ま
た被試験メモリを破損したりすることを防止できるメモ
リ試験装置の電源回路を提供することにある。It is an object of the present invention to eliminate such drawbacks, and to change the internal state of the memory under test when the state of the test execution signal input to the power supply voltage control signal selection section changes, or change the state of the memory under test. An object of the present invention is to provide a power supply circuit for a memory test device that can prevent damage.
本発明は、被試験メモリに電源を供給するメモリ試験装
置の電源回路において、
試験電圧制御信号と停止電圧制御信号と試験実行中信号
が入力され、前記試験実行中信号が試験実行中の状態の
ときには前記試験電圧制御信号を、試験実行中でない状
態のときには前記停止電圧制御信号を、電源電圧制御信
号として出力する電源電圧制御信号選択手段と、
前記電源電圧制御信号選択手段から出力される電源電圧
制御信号の変化をゆるやかにする手段と、ゆるやかにさ
れた前記電源電圧制御信号が入力され、これに従った電
源電圧を発生して前記被試験メモリに電源供給を行う電
源発生手段とを有することを特徴としている。The present invention provides a power supply circuit of a memory test device that supplies power to a memory under test, in which a test voltage control signal, a stop voltage control signal, and a test execution signal are input, and the test execution signal indicates the state in which the test is being executed. power supply voltage control signal selection means for outputting the test voltage control signal at times and the stop voltage control signal when the test is not being executed as a power supply voltage control signal; and a power supply voltage output from the power supply voltage control signal selection means. The device has a means for making the change in the control signal gentle, and a power generation means that receives the softened power supply voltage control signal and generates a power supply voltage in accordance with the power supply voltage control signal to supply power to the memory under test. It is characterized by
次に、本発明の実施例について図面を参照して説明する
。Next, embodiments of the present invention will be described with reference to the drawings.
第１図は、本発明の一実施例を示すブロック図である。FIG. 1 is a block diagram showing one embodiment of the present invention.
このメモリ試験装置の電源回路は、被試験メモリ４に電
源を供給するものであり、電源電圧制御信号選択部１と
、コンデンサ２と、電源発生部３とで構成される。The power supply circuit of this memory testing apparatus supplies power to the memory under test 4 and is composed of a power supply voltage control signal selection section 1, a capacitor 2, and a power generation section 3.
このような構成のメモリ試験装置の電源回路において、
電源電圧制御信号選択部１は、試験電圧制御信号ａと停
止電圧制御信号すと試験実行中信号Ｃが入力され、試験
実行中信号Ｃが試験実行中の状態の場合は、試験電圧制
御信号ａを電源電圧制御信号ｄとして出力端子１１から
出力し、試験実行中信号Ｃが試験実行中ではない状態の
場合は、停止電圧制御信号すを電源電圧制御信号ｄとし
て出力端子１１から出力する。In the power supply circuit of the memory test equipment with this configuration,
The power supply voltage control signal selection unit 1 receives the test voltage control signal a, the stop voltage control signal, and the test execution signal C, and when the test execution signal C is in the test execution state, the test voltage control signal a is input. is outputted from the output terminal 11 as the power supply voltage control signal d, and when the test execution signal C is in a state where the test is not being executed, the stop voltage control signal S is outputted from the output terminal 11 as the power supply voltage control signal d.
コンデンサ２は、電源電圧制御信号選択部１の出力端子
１１とグランドとの間に接続されて、電源電圧制御信号
選択部１の出力端子１１から出力される電源電圧制御信
号ｄの電圧変化をゆるやかにする。すなわち、コンデン
サ２は、２値的に変化する電源電圧制御信号ｄをアナロ
グ信号として電源発生部３に出力する。The capacitor 2 is connected between the output terminal 11 of the power supply voltage control signal selection section 1 and the ground, and gently changes the voltage of the power supply voltage control signal d output from the output terminal 11 of the power supply voltage control signal selection section 1. Make it. That is, the capacitor 2 outputs the binary-varying power supply voltage control signal d to the power supply generating section 3 as an analog signal.
電源発生部３は、コンデンサ２によって電圧変化をゆる
やかにされた電源電圧制御信号ｄを、入力端子１２に入
力され、この電源電圧制御信号ｄにより設定される電圧
を有する被試験メモリ電源を被試験メモリ４に与える。The power supply generating section 3 inputs a power supply voltage control signal d whose voltage change is made gentle by the capacitor 2 to an input terminal 12, and generates a memory power supply under test having a voltage set by the power supply voltage control signal d. Give it to memory 4.
次に、本実施例の動作について説明する。Next, the operation of this embodiment will be explained.
被試験メモリ４の試験を実行している場合、試験実行中
信号Ｃは、試験実行中の状態となっている。これにより
、電源電圧制御信号選択部１は、試験電圧制御信号ａを
電源電圧制御信号ｄとして、出力端子１１から出力して
いる。この電源電圧制御信号ｄにより、電源発生部３は
、試験電圧制御信号ａで設定される電源電圧を有する電
源を、被試験メモリ４に供給している。When the memory under test 4 is being tested, the test execution signal C is in the test execution status. Thereby, the power supply voltage control signal selection section 1 outputs the test voltage control signal a as the power supply voltage control signal d from the output terminal 11. In response to this power supply voltage control signal d, the power generation section 3 supplies the memory under test 4 with a power supply having a power supply voltage set by the test voltage control signal a.
ここで、試験を一時停止する場合、試験実行中信号Ｃは
、試験実行中でない状態となる。これにより、電源電圧
制御信号選択部１は、入力されている試験電圧制御信号
ａ、停止電圧制御信号すから、停止電圧制御信号すを選
択して、出力端子１１より出力する。これにより、電源
電圧制御信号ｄは、試験電圧制御信号ａから停止電圧制
御信号すに切り替えられるが、この切り替えにより発生
する電圧の変化は、コンデンサ２によりゆるやかにされ
る。このゆるやかにされた電源電圧制御信号ｄは、電源
発生部３の入力端子１２に入力される。Here, when the test is temporarily stopped, the test execution signal C becomes a state where the test is not being executed. As a result, the power supply voltage control signal selection unit 1 selects the stop voltage control signal S from the input test voltage control signal a and the stop voltage control signal and outputs it from the output terminal 11. As a result, the power supply voltage control signal d is switched from the test voltage control signal a to the stop voltage control signal S, but the change in voltage caused by this switching is made gradual by the capacitor 2. This softened power supply voltage control signal d is input to the input terminal 12 of the power generation section 3.
この信号により、電源発生部３は、停止電圧制御信号す
で設定される電圧を有する電源を被試験メモリ４に供給
するが、このとき発生する電圧の変化は、ゆるやかにさ
れた電源電圧制御信号ｄにより、ゆるやかとなる。In response to this signal, the power supply generator 3 supplies the memory under test 4 with a power supply having the voltage already set by the stop voltage control signal, but the voltage change that occurs at this time is caused by the gradual power supply voltage control signal. d makes it gentle.
再び試験を始める場合も同様となる。すなわち、試験実
行中信号Ｃは、試験実行中の状態となり、電源電圧制御
信号選択部１は、試験電圧制御信号ａを出力する。これ
により、電源電圧制御信号ｄは、試験電圧制御信号ａに
切り替えられるが、この切り替えにより発生する電圧の
変化は、コンデンサ２によりゆるやかにされる。このゆ
るやかにされた電源電圧制御信号ｄは、電源発生部３に
入力される。この信号により、電源発生部３は、試験電
圧制御信号ａで設定される電圧を有する電源を被試験メ
モリ４に供給するが、このとき発生する電圧の変化は、
コンデンサ２でゆるやかにされた電源電圧制御信号ｄに
より、ゆるやかとなる。The same applies when starting the test again. That is, the test execution signal C is in a test execution state, and the power supply voltage control signal selection section 1 outputs the test voltage control signal a. As a result, the power supply voltage control signal d is switched to the test voltage control signal a, but the change in voltage caused by this switching is made gradual by the capacitor 2. This moderated power supply voltage control signal d is input to the power supply generation section 3. In response to this signal, the power supply generator 3 supplies the memory under test 4 with a power supply having the voltage set by the test voltage control signal a, but the change in voltage that occurs at this time is
The power supply voltage control signal d made gentle by the capacitor 2 makes it gentle.
このようにして本実施例は、電源発生部２の入力端子１
２と接地端子間にコンデンサ２を並列接続することによ
り電源電圧制御信号ｄの電圧変化をゆるやかにして、電
源発生部３からの被試験メモリ電源供給の変化をゆるや
かにすることにより、被試験メモリ４の電源供給端子の
人力特性との整合を容易にしている。In this way, in this embodiment, the input terminal 1 of the power generation section 2
By connecting a capacitor 2 in parallel between 2 and the ground terminal, the voltage change of the power supply voltage control signal d is made gradual, and the change in the power supply to the memory under test from the power generation section 3 is made gentle. This facilitates matching with the human power characteristics of the power supply terminal of No. 4.
以上説明したように、本発明によれば、被試験メモリに
対し複数回の断続的な一連の試験などを実行する場合で
も、被試験メモリに対する電源供給電圧の変化をゆるや
かにすることにより、被試験メモリの電源供給端子の入
力特性との整合の不具合のために被試験メモリの内部状
態を変化させたり、被試験メモリを破損してしまうよう
な電源供給電圧の変化における乱れを防止できる効果が
ある。As described above, according to the present invention, even when performing a series of intermittent tests on the memory under test, the power supply voltage to the memory under test is gradually changed. This has the effect of preventing disturbances in power supply voltage changes that could change the internal state of the memory under test or damage the memory under test due to a mismatch with the input characteristics of the power supply terminal of the test memory. be.
第１図は本発明の一実施例を示すブロック図、第２図は
従来のメモリ試験装置の一例を示すブロック図である。
■・・・電源電圧制御信号選択部
２・・・コンデンサ
３・・・電源発生部
４・・・被試験メモリ
ａ・・・試験電圧制御信号
ｂ・・・停止電圧制御信号
Ｃ・・・試験実行中信号
ｄ・・・電源電圧制御信号FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 is a block diagram showing an example of a conventional memory testing device. ■...Power supply voltage control signal selection section 2...Capacitor 3...Power supply generation section 4...Memory under test a...Test voltage control signal b...Stop voltage control signal C...Test Execution signal d...power supply voltage control signal
Claims (1)
電源回路において、 試験電圧制御信号と停止電圧制御信号と試験実行中信号
が入力され、前記試験実行中信号が試験実行中の状態の
ときには前記試験電圧制御信号を、試験実行中でない状
態のときには前記停止電圧制御信号を、電源電圧制御信
号として出力する電源電圧制御信号選択手段と、 前記電源電圧制御信号選択手段から出力される電源電圧
制御信号の変化をゆるやかにする手段と、ゆるやかにさ
れた前記電源電圧制御信号が入力され、これに従った電
源電圧を発生して前記被試験メモリに電源供給を行う電
源発生手段とを有することを特徴とするメモリ試験装置
の電源回路。(1) When a test voltage control signal, a stop voltage control signal, and a test execution signal are input to the power supply circuit of the memory test equipment that supplies power to the memory under test, and the test execution signal is in the state that the test is being executed. power supply voltage control signal selection means for outputting the test voltage control signal and the stop voltage control signal as a power supply voltage control signal when a test is not being executed; and power supply voltage control output from the power supply voltage control signal selection means. The method further comprises: a means for making the change of the signal gradual; and a power generation means that receives the softened power supply voltage control signal and generates a power supply voltage in accordance with the power supply voltage control signal to supply power to the memory under test. Power supply circuit for memory test equipment featuring features.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62289452A JPH01133164A (en) | 1987-11-18 | 1987-11-18 | Power supply circuit for memory testing device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62289452A JPH01133164A (en) | 1987-11-18 | 1987-11-18 | Power supply circuit for memory testing device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01133164A true JPH01133164A (en) | 1989-05-25 |
Family
ID=17743447
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62289452A Pending JPH01133164A (en) | 1987-11-18 | 1987-11-18 | Power supply circuit for memory testing device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01133164A (en) |
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| US11214032B2 (en) | 2016-06-16 | 2022-01-04 | Packsize Llc | Box template production system and method |
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-
1987
- 1987-11-18 JP JP62289452A patent/JPH01133164A/en active Pending
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| US11731385B2 (en) | 2011-11-10 | 2023-08-22 | Packsize Llc | Converting machine |
| US11247789B2 (en) | 2014-12-29 | 2022-02-15 | Packsize Llc | Method of converting sheet material into a custom packaging template |
| US11214032B2 (en) | 2016-06-16 | 2022-01-04 | Packsize Llc | Box template production system and method |
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| US11286073B2 (en) | 2017-03-06 | 2022-03-29 | Packsize Llc | Box erecting method and system |
| US11738897B2 (en) | 2017-03-06 | 2023-08-29 | Packsize Llc | Box erecting method and system |
| US11446891B2 (en) | 2017-06-08 | 2022-09-20 | Packsize Llc | Tool head positioning mechanism for a converting machine, and method for positioning a plurality of tool heads in a converting machine |
| US11173685B2 (en) | 2017-12-18 | 2021-11-16 | Packsize Llc | Method for erecting boxes |
| US11667096B2 (en) | 2018-04-05 | 2023-06-06 | Avercon BVBA | Packaging machine infeed, separation, and creasing mechanisms |
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| US11634244B2 (en) | 2018-06-21 | 2023-04-25 | Packsize Llc | Packaging machine and systems |
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| US11642864B2 (en) | 2018-09-05 | 2023-05-09 | Packsize Llc | Box erecting method and system |
| US11752725B2 (en) | 2019-01-07 | 2023-09-12 | Packsize Llc | Box erecting machine |
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