JPH01125929A - Pattern formation of photoresist - Google Patents
Pattern formation of photoresistInfo
- Publication number
- JPH01125929A JPH01125929A JP62284499A JP28449987A JPH01125929A JP H01125929 A JPH01125929 A JP H01125929A JP 62284499 A JP62284499 A JP 62284499A JP 28449987 A JP28449987 A JP 28449987A JP H01125929 A JPH01125929 A JP H01125929A
- Authority
- JP
- Japan
- Prior art keywords
- photoresist
- path
- wiring
- exposure amount
- light
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 229920002120 photoresistant polymer Polymers 0.000 title claims abstract description 52
- 230000007261 regionalization Effects 0.000 title 1
- 239000004065 semiconductor Substances 0.000 claims abstract description 9
- 239000000758 substrate Substances 0.000 claims abstract description 9
- 229910052751 metal Inorganic materials 0.000 claims abstract description 6
- 239000002184 metal Substances 0.000 claims abstract description 6
- 238000000034 method Methods 0.000 claims description 19
- 230000001678 irradiating effect Effects 0.000 claims description 3
- 239000011248 coating agent Substances 0.000 claims description 2
- 238000000576 coating method Methods 0.000 claims description 2
- 239000010410 layer Substances 0.000 description 10
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 229910052782 aluminium Inorganic materials 0.000 description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 4
- 238000005530 etching Methods 0.000 description 3
- 229910052681 coesite Inorganic materials 0.000 description 2
- 229910052906 cristobalite Inorganic materials 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 229910052682 stishovite Inorganic materials 0.000 description 2
- 229910052905 tridymite Inorganic materials 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
Landscapes
- Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
- Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の目的〕
(産業上の利用分野)
本発明は、金属被膜からなる配線路が形成された半導体
基板上にフォトレジストを塗り、このフォトレジストに
光を照射し、現像することによりフォトレジストのパタ
ーンを形成するフォトレジストのパターン形成方法に関
する。[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention involves applying a photoresist onto a semiconductor substrate on which wiring paths made of a metal film are formed, and irradiating the photoresist with light. , relates to a method for forming a photoresist pattern by developing a photoresist pattern.
(従来の技術)
従来のフォトレジストのパターン形成方法を第5図に示
す二層配線間の接続穴を開ける場合を例にとって説明す
る。単結晶シリコン上にトランジスタや、キャパシタ等
の回路素子が形成された半導体基板1上にアルミニウム
からなる下層配線路2のパターンを形成し、層間絶縁膜
3を積層した後フォトレジスト4を塗布する。ここでフ
ォトマスク5を介して光6が照射されるとフォトマスク
5で覆われてい、ないところのフォトレジスト4aが感
光する(第5図(a)参照)。次に、現像が行われると
感光したフォトレジストが剥離される(第5図(b))
。続いてフォトレジスト4をマスクに層間絶縁膜3をエ
ツチングし、接続孔7を開けた後、アルミニウムを積層
しく第5図(C)参照)、上層配線路8のパターンを形
成すると二層配線パターンができあがる。(Prior Art) A conventional method of forming a photoresist pattern will be described by taking as an example the case of forming a connection hole between two-layer interconnections as shown in FIG. A pattern of lower wiring paths 2 made of aluminum is formed on a semiconductor substrate 1 in which circuit elements such as transistors and capacitors are formed on single crystal silicon, and after an interlayer insulating film 3 is laminated, a photoresist 4 is applied. When the light 6 is irradiated through the photomask 5, the photoresist 4a that is not covered by the photomask 5 is exposed to light (see FIG. 5(a)). Next, when development is performed, the exposed photoresist is peeled off (Figure 5(b)).
. Next, the interlayer insulating film 3 is etched using the photoresist 4 as a mask to open a connection hole 7, and then aluminum is laminated (see FIG. 5(C)) to form a pattern for the upper layer wiring path 8, forming a two-layer wiring pattern. is completed.
(発明が解決しようとする問題点)
このように従来のフォトレジストのパターン形成方法を
用いてフォトマスク5を介して露光する場合、下層配線
2のパターンに対してフォトマスク5の位置合せを行う
が、合せずれを考慮して接続孔7の近辺の下層配線2の
部分を第6図に示すように太らせておく必要があった。(Problems to be Solved by the Invention) When exposing through the photomask 5 using the conventional photoresist pattern forming method as described above, the photomask 5 is aligned with the pattern of the lower wiring 2. However, in consideration of misalignment, it was necessary to thicken the portion of the lower layer wiring 2 near the connection hole 7 as shown in FIG. 6.
今、仮に露光装置の解像度が1.0μm1合せずれを0
.5μmとし、下層配線2の幅(第6図に示す寸法X)
が1,0μm1間隔(第6図に示す寸法y)が1.0μ
mの場合の下層配線2のピッチ(第6図に示す寸法p)
は2.5μmとなる。この場合、接続孔7の位置は制限
され、複数の接続孔7は第6図に示すように配線長方向
に少しずつずせらせて配置しなければならない。したが
って接続孔7の配置が制限されないためには、合せずれ
余裕(0,5μm)を両側に設ける必要が有り、この場
合の下層配線2のピッチは3.0μmとなる。Now, suppose that the resolution of the exposure device is 1.0 μm, and the misalignment is 0.
.. The width of the lower layer wiring 2 is 5 μm (dimension X shown in Figure 6).
is 1.0 μm, and the interval (dimension y shown in Figure 6) is 1.0 μm.
Pitch of lower layer wiring 2 in case of m (dimension p shown in Fig. 6)
is 2.5 μm. In this case, the positions of the connection holes 7 are limited, and the plurality of connection holes 7 must be arranged so as to be shifted little by little in the wiring length direction, as shown in FIG. Therefore, in order to avoid restrictions on the arrangement of the connection holes 7, it is necessary to provide misalignment margins (0.5 .mu.m) on both sides, and in this case, the pitch of the lower layer wiring 2 is 3.0 .mu.m.
すなわち合せずれ余裕を全く設けない場合(この時の下
層配線2のピッチは2.0μm)に比べて下層配線2の
ピッチは50%の増加となる。したがって、配線面積が
LSIのチップ面積を決めているような場合には面積が
50%も増加するという問題があった。That is, the pitch of the lower layer wiring 2 is increased by 50% compared to the case where no misalignment margin is provided (the pitch of the lower layer wiring 2 at this time is 2.0 μm). Therefore, when the wiring area determines the chip area of an LSI, there is a problem in that the area increases by as much as 50%.
本発明は、配線ピッチを小さくすることのできるフォト
レジストのパターン形成方法を提供することを目的とす
る。An object of the present invention is to provide a photoresist pattern forming method that can reduce the wiring pitch.
(問題点を解決するための手段)
本発明は、金属被膜からなる配線路が形成された半導体
基板上にフォトレジストを塗り、このフォトレジストに
フォトマスクを介して光を照射し、現像することにより
フォトレジストのパターンを形成するフォトレジストの
パターン形成方法において、直接に照射される光の露光
量によってはフォトレジストは感光されないが、直接に
照射された光と金属被膜による反射光との合計露光量に
よってフォトレジストが感光されるようにフォトレジス
トに直接に照射する光の露光量を制御することを特徴と
する。(Means for Solving the Problems) The present invention involves applying a photoresist on a semiconductor substrate on which a wiring path made of a metal film is formed, and developing the photoresist by irradiating it with light through a photomask. In the photoresist pattern forming method, which forms a photoresist pattern using The method is characterized in that the exposure amount of light directly irradiated onto the photoresist is controlled so that the photoresist is exposed to light depending on the amount of light.
(作 用)
このように構成された本発明によるフォトレジストのパ
ターン形成方法において、フォトレジストに直接に照射
される光の露光量によってフォトレジストは感光されな
いが、直接に照射された光と金属被膜による反射光との
合計露光量によってフォトレジストが感光されるように
フォトレジストに直接に照射する光の露光量が制御され
る。これにより本発明によるフォトレジストのパターン
形成方法は、フォトマスクの位置合せの合せずれ余裕を
考慮する必要がなく、配線ピッチを小さくすることがで
きる。(Function) In the photoresist pattern forming method according to the present invention configured as described above, the photoresist is not exposed to light depending on the amount of light irradiated directly onto the photoresist, but the amount of light irradiated directly onto the photoresist and the metal coating are not sensitized. The amount of exposure of the light directly irradiated to the photoresist is controlled so that the photoresist is exposed to the total amount of exposure including the reflected light. As a result, in the photoresist pattern forming method according to the present invention, there is no need to consider misalignment margin for photomask alignment, and the wiring pitch can be reduced.
(実施例)
第1図ないし第4図を用いて本発明によるフォトレジス
トのパターン形成方法の一興体例を説明する。第1図(
a)において、単結晶シリコン上にトランジスタやキャ
パシタ等の回路素子が形成された半導体基板1の上面に
絶縁11!(S iO2)を積層し、回路素子間の配線
に必要な穴を開けた後、アルミニウムをスパッタリング
法により約500OA積層し、フォトエツチング技術を
用いて配線路2を形成する(図示せず)。次いでSiO
2からなる絶縁膜を500OA積層する。(Example) An example of a photoresist pattern forming method according to the present invention will be described with reference to FIGS. 1 to 4. Figure 1 (
In a), the insulation 11! After laminating (SiO2) and making holes necessary for wiring between circuit elements, approximately 500 OA of aluminum is laminated by a sputtering method, and a wiring path 2 is formed by using a photoetching technique (not shown). Then SiO
500 OA of insulating films consisting of 2 are laminated.
この時積層された絶縁膜の上面は、配線路2の影響によ
り平坦でない。積層された絶縁膜の上面を平坦にするた
めに上面に平坦化レジストを塗り、このレジストと絶縁
膜のエツチング速度が同一となるようにエツチングを行
い、配線路2のパターンが露出する直前で止める。この
時エツチング後の上面は平坦となっている。そして、更
に絶縁膜3を100OA積層する。At this time, the upper surface of the laminated insulating film is not flat due to the influence of the wiring path 2. In order to flatten the upper surface of the laminated insulating film, a flattening resist is applied to the upper surface, and etching is performed so that the etching speed of this resist and the insulating film is the same, stopping just before the pattern of wiring path 2 is exposed. . At this time, the upper surface after etching is flat. Then, an insulating film 3 of 100 OA is further laminated.
次にポジ型のフォトレジスト4を1.0μmの厚さで絶
縁膜3−上に塗布する。そして、配線路2と後述の配線
路8の開けるべき接続孔を含んだ部分(幅寸法m)が露
光されるような開口部を有するフォトマスク5を上方に
置き、紫外光6を照射する(第1図(a))。すなわち
配線路2の接続穴7が第3図に示すように配線長方向に
長さgの寸法を有するものであれば、フォトマスク5の
対応する開口部の寸法は、第2図(a)に示すように配
線長方向に長さIであって、幅寸法がmとなる。Next, a positive type photoresist 4 is applied onto the insulating film 3- to a thickness of 1.0 μm. Then, a photomask 5 having an opening such that a portion (width dimension m) including a connection hole to be opened in the wiring path 2 and a wiring path 8 (described later) is exposed is placed above, and ultraviolet light 6 is irradiated ( Figure 1(a)). That is, if the connection hole 7 of the wiring path 2 has a length g in the wiring length direction as shown in FIG. 3, the dimensions of the corresponding opening of the photomask 5 are as shown in FIG. 2(a). As shown in the figure, the length is I in the wiring length direction, and the width is m.
一方、露光量とフォトレジストの残存膜厚は、一般に第
4図のグラフ(L、 F、 Thompson eta
l、 、 Annual Review or Mat
erials 5cience 。On the other hand, the exposure amount and the remaining photoresist film thickness are generally determined by the graph in Figure 4 (L, F, Thompson et al.
l, , Annual Review or Mat
erials 5science.
Vol、6,267 (1976)より)に示すような
関係を有する。すなわち、露光量が80+J/c−以下
の場合、フォトレジストはほとんど感光せず、残存する
膜厚率は1.0であるが、露光量が80膳J/c−を越
えるとフォトレジストは急激に感光し始め、100IJ
/a−で完全に感光して残存膜厚率が零となる。したが
って第1図(a)において、フォトレジスト4に照射す
る光の露光量を80−J/C−とし、配線路2の反射効
率を50%とすると、真下に配線路2が存在するフォト
レジスト4の部分の露光量は120■J/dとなるが、
存在しない部分の露光量は80*J/c−となる。Vol. 6, 267 (1976)). In other words, when the exposure amount is 80+J/c- or less, the photoresist is hardly exposed to light and the remaining film thickness ratio is 1.0, but when the exposure amount exceeds 80J/c-, the photoresist rapidly becomes Begins to be exposed to 100IJ
At /a-, the film is completely exposed and the residual film thickness ratio becomes zero. Therefore, in FIG. 1(a), if the exposure amount of light irradiated to the photoresist 4 is 80-J/C- and the reflection efficiency of the wiring path 2 is 50%, the photoresist with the wiring path 2 directly below it. The exposure amount for part 4 is 120 J/d,
The exposure amount of the non-existing portion is 80*J/c-.
すなわち、真下に配線路2が存在する部分は完全に感光
され、存在しない部分はほとんど感光されないこととな
り、この時現像が行われると真下に配線路2が存在する
部分の残存膜厚は零で、存在しない部分の残存膜厚はほ
ぼ1.0μmとなる(第1図(b)および第2図(b)
)。In other words, the area where the wiring path 2 exists directly below is completely exposed to light, and the area where it does not exist is hardly exposed, and when development is performed at this time, the remaining film thickness in the area where the wiring path 2 exists directly below is zero. , the remaining film thickness in the non-existent part is approximately 1.0 μm (Fig. 1(b) and Fig. 2(b)).
).
現像されたフォトレジストパターンをマスクにして絶縁
膜(SiO2)3をRIE (反応性イオンエツチング
)で異方性エツチングを行うと、第1図(a)でフォト
マスクのない箇所のうち、真下に配線路2のあるところ
の絶縁膜だけが配線路2の幅で開孔されて接続孔7が形
成される。この後アルミニウムを積層し、配線パターン
を形成すると、配線路8と配線路2が接続孔7を介して
接続され、二層配線が形成される(第1図(C)および
第2図(c、))。When the insulating film (SiO2) 3 is anisotropically etched by RIE (reactive ion etching) using the developed photoresist pattern as a mask, the area directly below where there is no photomask as shown in Figure 1(a) is etched. A connection hole 7 is formed by opening a hole with the width of the wiring path 2 only in the insulating film where the wiring path 2 is located. After this, when aluminum is laminated and a wiring pattern is formed, the wiring path 8 and the wiring path 2 are connected through the connection hole 7, and a two-layer wiring is formed (Fig. 1(C) and Fig. 2(c) ,)).
以上述べたことから本実施例のフォトレジストのパター
ン形成方法によればフォトマスクの位置合せの合せずれ
余裕を考慮する必要がなく、これにより配線ピッチを小
さくすることができる。As described above, according to the photoresist pattern forming method of this embodiment, there is no need to consider the misalignment margin of photomask alignment, and thereby the wiring pitch can be reduced.
本発明によれば、配線ピνチを小さくすることのできる
フォトレジストのパターン形成方法を提供することがで
きる。According to the present invention, it is possible to provide a photoresist pattern forming method that can reduce the wiring pitch ν.
第1図は第3図に示す配線路および接続孔が形成された
半導体基板のA−A断面であって、本発明によるフォト
レジストのパターン形成方法の形成工程の一興体例を示
す断面図、第2図は第3図に示す配線路が形成された半
導体基板のB−B断面であって、本発明によるフォトレ
ジストのパターン形成方法の一興体例を示す断面図、第
3図は本発明によるフォトレジストのパターン形成方法
を用いて配線路および接続孔が形成された半導体基板の
平面図、第4因はフォトレジストの感光量と残存膜厚率
との関係を示すグラフ、第5図は従来のフォトレジスト
のパターン形成方法の形成工程の具体例を示す断面図、
第6図は従来のフォトレジストのパターン形成方法を用
いて形成された配線路および接続孔の平面図である。
1・・・半導体基板、2・・・配線路、3・・・絶縁膜
、4・・・フォトレジスト、5・・・フォトマスク、7
・・・接続孔、8・・・配線路。
出願人代理人 佐 藤 −雄
′f
(C)
銚1 図
第2図
尾3図
第4図
(C)
錦5図1 is a cross-sectional view taken along the line AA of the semiconductor substrate in which the wiring paths and connection holes shown in FIG. FIG. 2 is a BB cross section of a semiconductor substrate on which the wiring path shown in FIG. A plan view of a semiconductor substrate in which wiring paths and contact holes are formed using a resist pattern forming method.The fourth factor is a graph showing the relationship between the photoresist exposure amount and the remaining film thickness rate. A cross-sectional view showing a specific example of a forming process of a photoresist pattern forming method,
FIG. 6 is a plan view of wiring paths and connection holes formed using a conventional photoresist pattern forming method. DESCRIPTION OF SYMBOLS 1... Semiconductor substrate, 2... Wiring path, 3... Insulating film, 4... Photoresist, 5... Photomask, 7
... Connection hole, 8... Wiring path. Applicant's agent: Sato-O'f (C) Choi 1 Figure 2 Figure 3 Figure 4 (C) Brocade 5
Claims (1)
フォトレジストを塗り、このフォトレジストにフォトマ
スクを介して光を照射し、現像することによりフォトレ
ジストのパターンを形成するフォトレジストのパターン
形成方法において、直接に照射される光の露光量によっ
ては前記フォトレジストは感光されないが、前記直接に
照射された光と前記金属被膜による反射光との合計露光
量によって前記フォトレジストが感光されるように前記
フォトレジストに直接に照射する光の露光量を制御する
ことを特徴とするフォトレジストのパターン形成方法。A photoresist pattern forming method in which a photoresist is applied on a semiconductor substrate on which a wiring path made of a metal film is formed, and a photoresist pattern is formed by irradiating the photoresist with light through a photomask and developing it. In the method, the photoresist is not sensitized depending on the exposure amount of the directly irradiated light, but the photoresist is sensitized depending on the total exposure amount of the directly irradiated light and the light reflected by the metal coating. A method for forming a pattern on a photoresist, the method comprising controlling the amount of light that is directly irradiated onto the photoresist.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62284499A JPH01125929A (en) | 1987-11-11 | 1987-11-11 | Pattern formation of photoresist |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62284499A JPH01125929A (en) | 1987-11-11 | 1987-11-11 | Pattern formation of photoresist |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH01125929A true JPH01125929A (en) | 1989-05-18 |
Family
ID=17679305
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP62284499A Pending JPH01125929A (en) | 1987-11-11 | 1987-11-11 | Pattern formation of photoresist |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH01125929A (en) |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS51114087A (en) * | 1975-03-31 | 1976-10-07 | Toshiba Corp | Semiconductor |
JPS5731157A (en) * | 1980-08-01 | 1982-02-19 | Pioneer Electronic Corp | Wiring structure on circuit substrate |
JPS58119640A (en) * | 1981-12-31 | 1983-07-16 | インタ−ナショナル ビジネス マシ−ンズ コ−ポレ−ション | Method of forming photoresist pattern |
-
1987
- 1987-11-11 JP JP62284499A patent/JPH01125929A/en active Pending
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS51114087A (en) * | 1975-03-31 | 1976-10-07 | Toshiba Corp | Semiconductor |
JPS5731157A (en) * | 1980-08-01 | 1982-02-19 | Pioneer Electronic Corp | Wiring structure on circuit substrate |
JPS58119640A (en) * | 1981-12-31 | 1983-07-16 | インタ−ナショナル ビジネス マシ−ンズ コ−ポレ−ション | Method of forming photoresist pattern |
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