JPH0112218Y2 - - Google Patents
Info
- Publication number
- JPH0112218Y2 JPH0112218Y2 JP9719182U JP9719182U JPH0112218Y2 JP H0112218 Y2 JPH0112218 Y2 JP H0112218Y2 JP 9719182 U JP9719182 U JP 9719182U JP 9719182 U JP9719182 U JP 9719182U JP H0112218 Y2 JPH0112218 Y2 JP H0112218Y2
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- memories
- signal
- signals
- controls
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 230000015654 memory Effects 0.000 claims description 26
- 238000006243 chemical reaction Methods 0.000 claims description 5
- 238000010586 diagram Methods 0.000 description 4
- 230000002596 correlated effect Effects 0.000 description 1
- 230000002452 interceptive effect Effects 0.000 description 1
- 238000000034 method Methods 0.000 description 1
Landscapes
- Measurement Of Velocity Or Position Using Acoustic Or Ultrasonic Waves (AREA)
Description
【考案の詳細な説明】
本考案は、レーダやソナー等における特定のく
り返しで得られる信号を処理する回路に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a circuit that processes signals obtained through specific repetitions in radar, sonar, and the like.
従来のこの種回路は、第１図に示すごとく、入
力信号をアナログデイジタル変換回路１でデイジ
タル信号に変換し、それを書込制御回路２の制御
のもとに各第１メモリ３および第２メモリ４に順
次書き込み、書き込みの終了後、タイミング回路
５とアドレスカウンタ６の制御のもとに第１およ
び第２メモリの記憶内容を同時に読み出し、
AND回路７によつて論理積が求められる。これ
によつて入力信号の中で、レーダやソナー等の装
置の受信機内で発生するホワイトノイズや外部か
ら受信するノイズ等の相関性のないノイズや、他
船または自船の別の装置より発生する電波または
音波を受信した時の干渉波信号は除去されるので
あるが、同時にノイズとほぼ同レベルまたはノイ
ズよりやや低いレベルの希望信号であるフラクチ
エーシヨン（変動）のある信号も除去されてしま
う不都合があつた。 As shown in FIG. 1, a conventional circuit of this kind converts an input signal into a digital signal in an analog-to-digital conversion circuit 1, and converts the input signal into a digital signal under the control of a write control circuit 2. Sequentially write to the memory 4, and after the writing is completed, read out the stored contents of the first and second memories simultaneously under the control of the timing circuit 5 and address counter 6,
The AND circuit 7 calculates the logical product. This eliminates uncorrelated noise in the input signal, such as white noise generated within the receiver of equipment such as radar and sonar, and noise received from outside, as well as noise generated from other equipment on other ships or your own ship. Interfering signals that occur when radio waves or sound waves are received are removed, but at the same time, signals with fractuation (fluctuations), which are desired signals at approximately the same level as the noise or at a slightly lower level than the noise, are also removed. There was an inconvenience.
本考案は、このような従来技術の欠点を解消
し、入力信号からノイズや干渉を除去しながらも
変動のある信号は出来るだけ除去しないようにし
た信号処理回路を提供するものである。 The present invention eliminates the drawbacks of the prior art and provides a signal processing circuit that removes noise and interference from an input signal while minimizing the removal of fluctuating signals.
以下図面に示す本考案の一実施例につき詳説す
る。 An embodiment of the present invention shown in the drawings will be explained in detail below.
第２図において、第１図と同一もしくは同等の
回路には同一の符号が付されている。Ｍ１〜Ｍ３
はそれぞれ第１〜第３メモリ、７および８は
AND回路、９はOR回路、１０は入力信号端子、
１１はタイミングパルス端子、１２は出力信号端
子、１３はタイミングパルス出力端子である。 In FIG. 2, circuits that are the same as or equivalent to those in FIG. 1 are given the same reference numerals. M1~M3
are the first to third memories, 7 and 8 are respectively
AND circuit, 9 is OR circuit, 10 is input signal terminal,
11 is a timing pulse terminal, 12 is an output signal terminal, and 13 is a timing pulse output terminal.
以下第２図に示す回路の動作を、第３図の波形
図を参照しながら述べる。 The operation of the circuit shown in FIG. 2 will be described below with reference to the waveform diagram in FIG. 3.
入力信号は端子１０から入力され、アナログデ
イジタル変換回路１によつてデイジタル信号に変
換された後、書込制御回路２の制御のもとに３つ
のメモリにＭ１，Ｍ２，Ｍ３，Ｍ２，Ｍ１の順で
逐次データの書込みが行われる。第３図のイ〜ハ
にはそれぞれ第１〜第３メモリＭ１〜Ｍ３に記憶
されたデータが示されており、第１メモリＭ１と
第３メモリＭ３には記号Ｎ１およびＮ２で示され
るようなノイズ信号が含まれ、第１〜第３メモリ
Ｍ１〜Ｍ３には記号ＦおよびＦ１で示されるよう
な変動のある信号が含まれている。第１メモリＭ
１および第２メモリＭ２のデータおよび第２メモ
リＭ２と第３メモリＭ３のデータは、各メモリの
アドレスを制御するアドレスカウンタ６の制御の
もとに同時に読み出され、それぞれAND回路７
および８によつて論理積が求められる。すなわ
ち、第１、第２メモリＭ１，Ｍ２の各データの論
理積は、AND回路７によつて第３図ニに示すよ
うに相関性のない第１メモリＭ１のノイズ信号Ｎ
１および第２メモリＭ２の変動のある信号Ｆ１の
除去されたものとなる。また、第２、第３メモリ
Ｍ２，Ｍ３の各データの論理積は、AND回路８
によつて第３図ホに示すように第３メモリＭ３の
ノイズ信号Ｎ２の除去されたものが得られる。そ
してこの両AND回路７，８の出力はOR回路９に
入力されて論理和が求められ、第３図のヘに示す
ように相関性のないノイズ信号は除去されている
が、相関性のある変動のある信号Ｆ２およびＦ１
は残されている。すなわち、AND回路７，８の
どちらかに変動のある信号ＦまたはＦ１が残つて
いれば除去されることなく最終信号として得られ
ることになる。尚、タイミング回路５は、書込制
御回路２およびアドレスカウンタ６のタイミング
の制御と出力タイミングパルスの発生を行うもの
である。 The input signal is input from the terminal 10, converted into a digital signal by the analog-to-digital conversion circuit 1, and then stored in three memories M1, M2, M3, M2, and M1 under the control of the write control circuit 2. Data is written sequentially in this order. Data stored in the first to third memories M1 to M3 are respectively shown in A to C of FIG. A noise signal is included, and the first to third memories M1 to M3 include signals with fluctuations as shown by symbols F and F1. 1st memory M
The data in the first and second memories M2 and the data in the second memory M2 and third memory M3 are read simultaneously under the control of an address counter 6 that controls the address of each memory, and are read out by an AND circuit 7, respectively.
The logical AND is calculated by and 8. That is, the logical product of each data of the first and second memories M1 and M2 is processed by the AND circuit 7 into a noise signal N of the first memory M1 having no correlation, as shown in FIG. 3D.
The signal F1 with fluctuations in the first and second memories M2 is removed. Further, the AND circuit 8 performs the logical product of each data in the second and third memories M2 and M3.
As a result, as shown in FIG. 3E, the noise signal N2 of the third memory M3 is removed. The outputs of both AND circuits 7 and 8 are input to an OR circuit 9 to calculate the logical sum, and as shown in Fig. 3, uncorrelated noise signals are removed, but correlated noise signals are removed. Signals F2 and F1 with fluctuations
is left behind. That is, if a signal F or F1 with fluctuation remains in either of the AND circuits 7 and 8, it will not be removed and will be obtained as the final signal. The timing circuit 5 controls the timing of the write control circuit 2 and the address counter 6 and generates output timing pulses.
以上述べたように、互いに相関性のないノイズ
信号や干渉波信号は除去されるが、変動のある信
号は除去されずに残されるので、スキヤンコンバ
ータを利用したレーダ等において、信号を一度表
示用メモリ回路へ書込み表示するような場合、極
座標からXY座標に変換してメモリに記憶し、同
一表示メモリセルが多数回アクセスされることに
なるが、この時書込まれたデータは最終回にアク
セスされたデータが残り、表示されるものであ
る。従つて、このような装置に本考案を適用すれ
ば、変動のある信号をも除去されることなく表示
され得るものである。 As mentioned above, noise signals and interference wave signals that have no correlation with each other are removed, but signals with fluctuations are not removed and are left behind. When writing data to a memory circuit and displaying it, polar coordinates are converted to XY coordinates and stored in memory, and the same display memory cell will be accessed many times, but the data written at this time will not be accessed until the last time. The data that was created remains and is what is displayed. Therefore, if the present invention is applied to such a device, even signals with fluctuations can be displayed without being removed.
第１図は、従来の信号処理回路を示すブロツク
図、第２図は、本考案実施例を示すブロツク回路
図、および第３図は、該実施例回路の動作を説明
するための信号波形図である。
１……アナログデイジタル変換回路、２……書
込制御回路、３……第１メモリ、４……第２メモ
リ、５……タイミング回路、６……アドレスカウ
ンタ、７，８……AND回路、９……OR回路、１
０……入力信号端子、１１……タイミングパルス
端子、１２……出力信号端子、１３……出力タイ
ミングパルス。
FIG. 1 is a block diagram showing a conventional signal processing circuit, FIG. 2 is a block circuit diagram showing an embodiment of the present invention, and FIG. 3 is a signal waveform diagram for explaining the operation of the embodiment circuit. It is. DESCRIPTION OF SYMBOLS 1... Analog-digital conversion circuit, 2... Write control circuit, 3... First memory, 4... Second memory, 5... Timing circuit, 6... Address counter, 7, 8... AND circuit, 9...OR circuit, 1
0...Input signal terminal, 11...Timing pulse terminal, 12...Output signal terminal, 13...Output timing pulse.
Claims (1)
デイジタル変換回路と、該アナログデイジタル変
換回路にそれぞれ接続された第１〜第３メモリ
と、前記第１および第２メモリの記憶データの論
理積を求める第1AND回路と、前記第２および第
３メモリの記憶データの論理積を求める第2AND
回路と、前記第１および第2AND回路の出力の論
理和を求めるOR回路と、前記第１〜第３メモリ
へのデータ書込順序を制御する書込制御回路と、
前記第１〜第３メモリのアドレスを制御するアド
レスカウンタと、前記書込制御回路と前記アドレ
スカウンタのタイミングを制御し、出力タイミン
グパルスを発生するタイミング回路とを備え、入
力信号から相関性のないノイズおよび干渉波信号
を除去する一方、変動のある信号を除去しないよ
うにしたことを特徴とする信号処理回路。 an analog-to-digital conversion circuit that converts an input signal into a digital signal; first to third memories respectively connected to the analog-to-digital conversion circuit; and a first AND circuit that calculates a logical product of data stored in the first and second memories. and a second AND for calculating the logical product of the data stored in the second and third memories.
a circuit, an OR circuit for calculating the logical sum of the outputs of the first and second AND circuits, and a write control circuit that controls the order of writing data to the first to third memories;
An address counter that controls the addresses of the first to third memories, and a timing circuit that controls the timing of the write control circuit and the address counter and generates an output timing pulse, and has no correlation from the input signal. A signal processing circuit characterized in that noise and interference wave signals are removed, while fluctuating signals are not removed.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9719182U JPS593385U (en) | 1982-06-28 | 1982-06-28 | signal processing circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9719182U JPS593385U (en) | 1982-06-28 | 1982-06-28 | signal processing circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS593385U JPS593385U (en) | 1984-01-10 |
| JPH0112218Y2 true JPH0112218Y2 (en) | 1989-04-10 |
Family
ID=30231294
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9719182U Granted JPS593385U (en) | 1982-06-28 | 1982-06-28 | signal processing circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS593385U (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0437307Y2 (en) * | 1985-09-06 | 1992-09-02 |
-
1982
- 1982-06-28 JP JP9719182U patent/JPS593385U/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS593385U (en) | 1984-01-10 |
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