JPH01112772A - Mis-type semiconductor device - Google Patents
Mis-type semiconductor deviceInfo
- Publication number
- JPH01112772A JPH01112772A JP27131387A JP27131387A JPH01112772A JP H01112772 A JPH01112772 A JP H01112772A JP 27131387 A JP27131387 A JP 27131387A JP 27131387 A JP27131387 A JP 27131387A JP H01112772 A JPH01112772 A JP H01112772A
- Authority
- JP
- Japan
- Prior art keywords
- region
- germanium
- type
- channel
- drain
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 13
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical group [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims abstract description 21
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 11
- 229910052710 silicon Inorganic materials 0.000 claims description 11
- 239000010703 silicon Substances 0.000 claims description 11
- 239000000758 substrate Substances 0.000 claims description 10
- 108091006146 Channels Proteins 0.000 abstract description 32
- 229910052732 germanium Inorganic materials 0.000 abstract description 17
- 230000015572 biosynthetic process Effects 0.000 abstract description 8
- 108010075750 P-Type Calcium Channels Proteins 0.000 abstract description 5
- 230000010354 integration Effects 0.000 abstract description 4
- 230000009467 reduction Effects 0.000 abstract description 2
- 230000005465 channeling Effects 0.000 abstract 1
- 239000000969 carrier Substances 0.000 description 20
- 230000005684 electric field Effects 0.000 description 8
- 230000000694 effects Effects 0.000 description 5
- 239000013078 crystal Substances 0.000 description 4
- 238000010586 diagram Methods 0.000 description 2
- 230000006872 improvement Effects 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 102100022289 60S ribosomal protein L13a Human genes 0.000 description 1
- 101000691550 Homo sapiens 39S ribosomal protein L13, mitochondrial Proteins 0.000 description 1
- 101000681240 Homo sapiens 60S ribosomal protein L13a Proteins 0.000 description 1
- 230000001133 acceleration Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- RZTAMFZIAATZDJ-UHFFFAOYSA-N felodipine Chemical compound CCOC(=O)C1=C(C)NC(C)=C(C(=O)OC)C1C1=CC=CC(Cl)=C1Cl RZTAMFZIAATZDJ-UHFFFAOYSA-N 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 230000035935 pregnancy Effects 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
- 230000029058 respiratory gaseous exchange Effects 0.000 description 1
- 239000012808 vapor phase Substances 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Abstract
Description
【発明の詳細な説明】
〔概 要〕
ショートチャネル化されるＭＩＳ型半導体装置の構造の
改良に関し、
素子面積を拡大させずにホットキャリアの発生を防止し
得る構造の提供を目的とし、
シリコン半導体基板に形成されたＭＩＳ型半導体装置で
あって、少なくともチャネル形成領域におけるドレイン
接合の近傍領域に、ゲルマニウム原子が導入された構成
を有する。[Detailed Description of the Invention] [Summary] Regarding the improvement of the structure of an MIS type semiconductor device that is made into a short channel, the purpose of this invention is to provide a structure that can prevent the generation of hot carriers without increasing the device area. This is a MIS type semiconductor device formed on a substrate, and has a structure in which germanium atoms are introduced into at least a region near a drain junction in a channel formation region.
本発明はＭＩＳ型半導体装置、特にショートチャネル化
されるＭＩＳ型半導体装置の構造の改良に関する。The present invention relates to an improvement in the structure of an MIS type semiconductor device, and particularly to a MIS type semiconductor device that is made into a short channel.
ＬＳＩ等半導体ＩＣの大規模化に伴って生ずる動作速度
の低下を回避するために、該ＬＳＩ等に作り付けられる
ＭＩＳＦＥＴは近時急速にショートチャネル化されてき
ている。In order to avoid the reduction in operating speed that occurs with the increase in the scale of semiconductor ICs such as LSIs, MISFETs built into LSIs and the like have recently been rapidly short-channeled.
このようにＭＩＳＦＥＴがショートチャネル化された際
に、ホットキャリアの生成に起因する信頬性の低下が問
題になる。When the MISFET is made into a short channel in this way, a problem arises in that the reliability decreases due to the generation of hot carriers.
ホットキャリアの持つエネルギーの大きさは、Ｌａｃｋ
ｙ Ｅｌｅｃｔｒｏｎモデルによると、下記（１）式に
よって表される。The amount of energy possessed by hot carriers is Lack
According to the y Electron model, it is expressed by the following equation (1).
Ｅ＝ｃ４ｔｌ （１）
Ｅ：キャリアのエネルギー
ｑ：電気素量
ε：電界強度
１：キャリアの平均自由行程
ＭＩＳＦＥＴがショートチャネル化された際にも、ドレ
イン−ソース間には通常のチャネル長を有する従来のＭ
ＩＳＦＥＴと同様に５Ｖ程度の電圧ｖ０が印加される。E=c4tl (1) E: Carrier energy q: Elementary charge ε: Electric field strength 1: Mean free path of carriers Even when a MISFET is made into a short channel, it has a normal channel length between the drain and source. Conventional M
As with the ISFET, a voltage v0 of about 5V is applied.
そのために、ショートチャネルＭＩＳＦＥＴにおいては
、上記（１）式におけるドレイン接合近傍の電界強度ε
が大幅に強まり、（１１式に従ってキャリアのエネルギ
ーＥが増大したホットキャリアを生ずる。Therefore, in a short channel MISFET, the electric field strength ε near the drain junction in equation (1) above is
becomes significantly stronger, producing hot carriers whose carrier energy E increases according to Equation 11.
そして加速されて高エネルギーを持ったホットキャリア
はゲート絶縁膜中に浸入し蓄積されて、該ＭＩＳＦＥＴ
の闇値電圧Ｖいを経時的に変動さ形成される電界強度を
減少させてホットキャリアの生成を抑止するＬ Ｄ Ｄ
（Ｌｉｇｈｔｒｙ Ｄｏｐｅｄ Ｄｒａｉｎ）構造や
Ｄ”（Ｄｏｕｂｌｅ Ｄｉｆｆｕｓｅｄ Ｄｒａｉｎ）
構造が提案されている。Then, the accelerated hot carriers with high energy penetrate into the gate insulating film and accumulate in the MISFET.
The dark value voltage V is changed over time to reduce the intensity of the electric field formed and suppress the generation of hot carriers.
(Lightry Doped Drain) structure and D” (Double Diffused Drain)
structure is proposed.
第８図及び第９図はＬＤＤ構造及びＤ３構造のＭＯＳ
Ｆ ＥＴを模式的に示す側断面図である。Figures 8 and 9 show MOSs of LDD structure and D3 structure.
FIG. 2 is a side sectional view schematically showing an FET.
これらの図において、１はｐ−型シリコン基板、２はｐ
型チャネルストッパ、３はフィールド酸化膜、４はゲー
ト酸化膜、５はゲート電極、６は絶縁膜サイドウオール
、７及び１０７はｎ−型（低濃度）ドレイン領域、８及
び１０８はｎ−型（低濃度）ソース領域、９はｎ゛型（
高濃度）ドレイン領域、１０は ｎ０型（高濃度）ソー
ス領域、１１はチャネル形成領域を示す。In these figures, 1 is a p-type silicon substrate, 2 is a p-type silicon substrate, and 2 is a p-type silicon substrate.
3 is a field oxide film, 4 is a gate oxide film, 5 is a gate electrode, 6 is an insulating film sidewall, 7 and 107 are n-type (low concentration) drain regions, 8 and 108 are n-type ( 9 is an n-type (low concentration) source region;
10 is an n0 type (highly doped) source region, and 11 is a channel forming region.
しかし上記ＬＤＤ構造及びＤ″構造においては、何れも
、チャネル形成領域１１と高濃度ドレイン領域９及び高
濃度ソース領域１０との間に低濃度ドレイン領域？、１
０７及び低濃度ソース領域８、１０８等が配設されるた
めに素子面積が拡大し、該ショートチャネルＭＩＳＦＥ
Ｔを用いるＩＣの集積度が低下するという問題があった
。However, in both the LDD structure and the D″ structure, a lightly doped drain region ?
07 and low concentration source regions 8, 108, etc., the element area is expanded, and the short channel MISFE
There is a problem in that the degree of integration of ICs using T is reduced.
そこで本発明は、素子面積を拡大させずにホットキャリ
アの発生を防止し得るＭＩＳ型半導体装置の提供を目的
とする。SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide an MIS type semiconductor device that can prevent the generation of hot carriers without increasing the device area.
ｃ問題点を解決するための手段〕
上記問題点は、シリコン半導体基板に形成されたＭＩＳ
型半導体装置であって、少なくともチャネル形成領域に
おけるドレイン接合の近傍領域に、ゲルマニウム原子が
導入された本発明によるＭＩＳ型半導体装置によって解
決される。c) Means for solving the problem] The above problem is caused by the MIS formed on a silicon semiconductor substrate.
This problem is solved by the MIS type semiconductor device according to the present invention, in which germanium atoms are introduced into at least the region near the drain junction in the channel forming region.
キャリアの移動度μと平均自由行程ｌの間には、電界を
一定とした時に、下記（２）式の関係が成り立つ。When the electric field is kept constant, the following relationship (2) holds between carrier mobility μ and mean free path l.
μｗ Ｋ １１” （２）Ｋ：比例
常数
一方、キャリアの平均自由行程ｌとキャリアのエネルギ
ーＥとは前記（１１式に示されたように正比例の関係に
ある。μw K 11'' (2) K: proportionality constant On the other hand, the mean free path l of the carrier and the energy E of the carrier are in a directly proportional relationship as shown in the above equation (11).
そこで本発明においては、シリコンと比率の如何を問わ
す混晶を形成し、且つキャリアの移動度μを低下せしめ
る効果を有するゲルマニウム原子を、効果的な移動度の
低下が得られる濃度にチャネル領域へ導入してキャリア
の平均自由行程ｌを短縮し、これによって（１１式に基
づきキャリアのエネルギーＥを減少させて、ホットキャ
リアの生成を防止する。Therefore, in the present invention, germanium atoms, which form mixed crystals with silicon in any ratio and have the effect of reducing carrier mobility μ, are added to the channel region at a concentration that effectively reduces carrier mobility. is introduced to shorten the carrier mean free path l, thereby reducing the carrier energy E based on equation (11) and preventing the generation of hot carriers.
かくて本発明によればホットキャリアの生成防止のため
に低濃度のドレイン領域やソース領域を設ける必要がな
くなって素子面積が拡大が回避され、ショートチャネル
Ｍｉｓ半導体装置の高密度高集積化が図れる。Thus, according to the present invention, there is no need to provide a low concentration drain region or source region to prevent the generation of hot carriers, thereby avoiding an increase in the device area and achieving high density and high integration of short channel Mis semiconductor devices. .
以下本発明を、図示実施例により具体的に説明する。 The present invention will be specifically explained below with reference to illustrated embodiments.
第１図、第２図、第３図、第４図は本発明の第１、第２
、第３、第４の実施例の要部を示す模式側断面図、第５
図、第６図は本発明の異なる応用例の要部模式側断面図
、第７図はシリコン（Ｓｉ）−ゲルマニウム（Ｇｅ）混
晶中のキャリアの移動度を示す図である。1, 2, 3, and 4 are the first and second embodiments of the present invention.
, a schematic side sectional view showing the main parts of the third and fourth embodiments, and the fifth embodiment.
6 are schematic side sectional views of main parts of different application examples of the present invention, and FIG. 7 is a diagram showing the mobility of carriers in a silicon (Si)-germanium (Ge) mixed crystal.
全図を通じ同一対象物は同一符合で示す。Identical objects are indicated by the same reference numerals throughout the figures.
本発明の第１の実施例を示す第１図において、１はｐ−
型シリコン基板、２はｐ型チャネルストッパ、３はフィ
ールド酸化膜、４はゲート酸化膜、５はゲート電極、９
はｎ゛型（高濃度）ドレイン領域、１０はｎ１型（高濃
度）ソース領域、１１はチャネル形成領域、１２は素子
形成領域、１３はゲルマニウム導入領域を示す。In FIG. 1 showing the first embodiment of the present invention, 1 is p-
type silicon substrate, 2 is a p-type channel stopper, 3 is a field oxide film, 4 is a gate oxide film, 5 is a gate electrode, 9
10 is an n-type (high concentration) drain region, 10 is an n1-type (high concentration) source region, 11 is a channel formation region, 12 is an element formation region, and 13 is a germanium-introduced region.
同図に示す第１の実施例においては、フィールド酸化膜
３及びｐ型チャネルストッパ２によって画定された、チ
ャネル形成領域１１とｎ゛型ドレイン領域９とｎ３型ソ
ース領域１０を含む素子領域１２の全面に、ゲルマニウ
ム（Ｇｅ）が所定の高濃度に導入された深さ例えば１０
００人程度０ゲルマニウム導入領域１３が形成される。In the first embodiment shown in the figure, a device region 12 including a channel forming region 11, an n-type drain region 9, and an n3-type source region 10 is defined by a field oxide film 3 and a p-type channel stopper 2. Germanium (Ge) is introduced into the entire surface at a predetermined high concentration to a depth of, for example, 10
A germanium introduction region 13 of about 0.00 is formed.
第７図に示される５ｉ−Ｇｅ混晶中におけるキャリアの
移動度、即ち電子の移動度μ、の成分比による変化（ａ
）、及び正孔の移動度μｍの成分比による変化（ｂ）か
ら、キャリアの移動度を低下せしめる効果を顕著に生ぜ
しめるためには、混晶中のＧｅの混入比率は１０〜２０
％程度である。従って前記Ｇｅ１人領域１３のＧｅ濃度
は５ Ｘ １０” 〜Ｉ Ｘ １０”ｃｍ”３程度に制
御される。The carrier mobility, that is, the electron mobility μ, in the 5i-Ge mixed crystal shown in FIG.
), and the change (b) in the hole mobility μm depending on the component ratio.
It is about %. Therefore, the Ge concentration in the Ge single region 13 is controlled to be approximately 5 x 10" to I x 10" cm3.
なお第１図の構造を形成する際には、ゲート電極５を形
成する前に気相拡散或いはイオン注入法により素子形成
領域１２の全面にＧｅ導入領域１３が形成され、ソース
及びドレイン領域９．１０はゲート電極５の形成後に、
該ゲート電極５に整合しイオン注入法により例えば３０
００人程度０深さに形成される。In forming the structure shown in FIG. 1, before forming the gate electrode 5, a Ge introduced region 13 is formed on the entire surface of the element forming region 12 by vapor phase diffusion or ion implantation, and the source and drain regions 9. 10, after forming the gate electrode 5,
For example, 30 mm is aligned with the gate electrode 5 by ion implantation.
Formed at a depth of about 0.00 people.
第２図に示す第２の実施例は、Ｇｅ導入領域１１３がソ
ース及びドレイン領域９、ｌＯより深く例えば４０００
人程度０深さに形成された前記第１の実施例の変形例で
ある。なお、この構造の形成方法、及びゲルマニウム導
入領域１１３のＧｅ濃度は第１の実施例と同様である。In the second embodiment shown in FIG.
This is a modification of the first embodiment in which the depth is approximately zero. Note that the method for forming this structure and the Ge concentration in the germanium introduced region 113 are the same as in the first embodiment.
以上はチャネル形成領域１１の全域にゲルマニウム導入
領域が形成される例である。The above is an example in which the germanium introduced region is formed throughout the channel forming region 11.
第３図に示す第３の実施例は、ソース及びドレイン領域
９．１０の表面部からチャネル形成領域１１の端部に食
い込んで深さ１０００人程度０ゲルマニウム導入領域１
３Ａ及び１３Ｂが形成された例である。In the third embodiment shown in FIG. 3, a germanium-introduced region 1 penetrates into the end of the channel forming region 11 from the surface of the source and drain regions 9 and 10 to a depth of about 1000.
This is an example in which 3A and 13B are formed.
ホットキャリアは電界が強（なるドレイン接合の近傍で
生成するので、チャネル形成領域１１におけるドレイン
領域１０の近傍部のキャリアの移動度を低下せしめれば
ホットキャリアの発生を抑制できるので、該実施例の構
造により充分な効果を生ずる。そして更に該実施例の構
造においてはチャネル形成領域１１の全域に低移動度の
領域が形成されないので、動作速度の向上に対し前記実
施例よりも有利である。Since hot carriers are generated near the drain junction where the electric field is strong, the generation of hot carriers can be suppressed by reducing the mobility of carriers in the vicinity of the drain region 10 in the channel forming region 11. Further, in the structure of this embodiment, since a low mobility region is not formed in the entire channel forming region 11, it is more advantageous than the previous embodiment in terms of improving the operating speed.
なおこの構造を形成する際には、ゲート電極５を形成し
た後に、該ゲート電極５をマスクにして素子形成領域１
２にゲルマニウムを浅くイオン注入し、熱処理によって
該ゲルマニウムの引伸し拡散を行ってゲルマニウム導入
領域１３Ａ 、 １３Ｂをソース及びドレイン領域より
深くチャネル形成領域１１の端部に浸入させた後、通常
通りゲート電極５をマスクにして不純物をイオン注入し
ソース領域９及びドレイン領域１０を形成する。ここで
完成されたゲルマニウム導入領域１３Ａ 、１３Ｂは、
前記実施例同様、Ｇｅ９度は５ Ｘ１０２１〜Ｉ ＸＩ
Ｏ”ｃｍ−３、深さ１０００人程度０ゲ成される。また
ソース、ドレイン領域９．１０の深さは例えば３０００
人とする。Note that when forming this structure, after forming the gate electrode 5, the element formation region 1 is formed using the gate electrode 5 as a mask.
Germanium is ion-implanted into the gate electrode 5 in a shallow manner, and the germanium is stretched and diffused by heat treatment so that the germanium-introduced regions 13A and 13B penetrate deeper into the end of the channel forming region 11 than the source and drain regions. Using as a mask, impurity ions are implanted to form a source region 9 and a drain region 10. The germanium introduction regions 13A and 13B completed here are as follows:
As in the above example, Ge9 degree is 5 X1021~I XI
The source and drain regions 9 and 10 are formed to a depth of about 3,000 cm and a depth of about 3,000 cm.
Be with people.
第４図に示す第４の実施例は、チャネル形成領域１１に
おいて連通せず且つソース、ドレイン領域９．１０より
も深いゲルマニウム導入領域Ｌ１３Ａ及び１１３Ｂが形
成された上記第３の実施例の変形例である。ゲルマニウ
ム導入領域のＧｅ：ａ度は上記実施例と同様で、深さは
例えばソース、ドレイン領域９．１０より１０００人程
度深い４０００人程度０深さに形成される。The fourth embodiment shown in FIG. 4 is a modification of the third embodiment in which germanium introduced regions L13A and 113B are formed that do not communicate in the channel forming region 11 and are deeper than the source and drain regions 9 and 10. It is. The Ge:a degree of the germanium-introduced region is the same as in the above embodiment, and the depth is, for example, about 4000 deep, which is about 1000 deep from the source and drain regions 9.10.
この構造の高速化に対する利点は第３の実施例と同様で
ある。The advantages of this structure for speeding up are the same as in the third embodiment.
なおゲルマニウム導入領域１１３Ａ及び１１３Ｂはゲー
ト電極５をマスクにしてＧｅを深くイオン注入すること
によって形成される。Note that the germanium introduced regions 113A and 113B are formed by deeply ion-implanting Ge using the gate electrode 5 as a mask.
なお図示しないが、チャネル領域におけるドレイン領域
の近傍部のみに選択的にゲルマニウム導大領域を形成し
た構造においても、上記第３、第４の実施例と同様の効
果及び利点を生ずる。Although not shown, a structure in which a large germanium conductive region is selectively formed only in the vicinity of the drain region in the channel region also produces effects and advantages similar to those of the third and fourth embodiments.
以上実施例に示したような本発明の構造においては、チ
ャネル領域の少なくともドレイン接合の近傍領域を含む
領域に高濃度のゲルマニウム導入領域が形成され該領域
におけるキャリアの移動度が低減せしめられるので、シ
ョートチャネル化されドレイン接合近傍に高電界が形成
された際にもキャリアのエネルギーＥがホットキャリア
を生成するレベルまで上昇するのが抑制される。In the structure of the present invention as shown in the embodiments above, a high-concentration germanium-introduced region is formed in the region of the channel region including at least the region near the drain junction, and the carrier mobility in this region is reduced. Even when a short channel is formed and a high electric field is formed near the drain junction, the carrier energy E is suppressed from increasing to a level that generates hot carriers.
そして通常、信頼度試験として行われる通電加速試験に
おいて、闇値電圧Ｖいの変動は許容の範囲内に抑えられ
、ＬＤＤ構造及びＤ３構造と同等な信頼度寿命が得られ
ている。In an energization acceleration test that is normally performed as a reliability test, fluctuations in the dark value voltage V were suppressed within an allowable range, and a reliability life equivalent to that of the LDD structure and the D3 structure was obtained.
従って、ホットキャリアの発生を防止するために、ＬＤ
Ｄ構造及びＤ３構造のように高濃度ドレイン領域とチャ
ネル形成領域の間に低濃度のドレイン領域を介在させて
ドレイン接合近傍の電界強度を低下させる必要がなくな
り、素子面積の縮小が図れる。Therefore, in order to prevent the generation of hot carriers, the LD
Unlike the D structure and the D3 structure, there is no need to interpose a lightly doped drain region between the highly doped drain region and the channel forming region to reduce the electric field strength near the drain junction, and the device area can be reduced.
第５図はＬＤＤ構造に前記第１の実施例の構成を付加し
て、ホットキャリアの防止効果を一層高めた本発明の一
応用例である。FIG. 5 shows an application example of the present invention in which the configuration of the first embodiment is added to the LDD structure to further enhance the effect of preventing hot carriers.
図において、１はｐ−型シリコン基板、２はｐ型チャネ
ルストッパ、３はフィールド酸化膜、４はゲート酸化膜
、５はゲート電極、６は絶縁膜サイドウオール、７はｎ
−型（低濃度）ドレイン領域、８はｎ−型（低濃度）ソ
ース領域、９はｎ゛型トドレイン領域１０はｎ゛゛ソー
ス領域、１１はチャネル形成領域、１３はゲルマニウム
４人領域を示す。In the figure, 1 is a p-type silicon substrate, 2 is a p-type channel stopper, 3 is a field oxide film, 4 is a gate oxide film, 5 is a gate electrode, 6 is an insulating film sidewall, and 7 is an n-type silicon substrate.
8 is an n-type (low concentration) source region, 9 is an n-type drain region 10 is an n-type source region, 11 is a channel forming region, and 13 is a germanium quadruple region.
第６図はＤ３構造に前記第４の実施例の構成を付加して
ホットキャリアの防止効果を一層高めた本発明の他の応
用例である。FIG. 6 shows another application example of the present invention in which the configuration of the fourth embodiment is added to the D3 structure to further enhance the hot carrier prevention effect.
図中、１０７はｎ−型（低濃度）ドレイン領域、１０Ｂ
はｎ−型（低濃度）ソース領域、その他の符号は第５図
と同一対象物を示している。In the figure, 107 is an n-type (low concentration) drain region, 10B
indicates an n-type (low concentration) source region, and other symbols indicate the same objects as in FIG.
なお本発明は、実施例と反対導電型チャネルを有するＭ
ＩＳ半導体装置にも勿論適用される。Note that the present invention provides an M
Of course, the present invention is also applied to IS semiconductor devices.
以上説明のように本発明によれば、チャネル領域におけ
るキャリアの平均自由行程を短縮せしめてキャリアの電
荷を減少させ、これによってホットキャリアの発生が防
止されるので、チャネル領域のドレイン接合近傍の電界
強度を低減するための低不純物濃度ソース・ドレイン領
域を設ける必要がなくなり、素子面積の縮小が図れる。As explained above, according to the present invention, the mean free path of carriers in the channel region is shortened to reduce the charge of the carriers, thereby preventing the generation of hot carriers, so that the electric field near the drain junction of the channel region There is no need to provide low impurity concentration source/drain regions to reduce the strength, and the device area can be reduced.
従って本発明はショートチャネルＭＩＳＩＣの高集積化
に有効である。Therefore, the present invention is effective for increasing the degree of integration of short channel MISICs.
第１図、第２図、第３図、第４図は本発明の第１、第２
、第３、第４の実施例の要部を示す模式第５図、第６図
は本発明の異なる応用例の要部模式側断面図、
第７図はシリコン（Ｓｉ）−ゲルマニウム（Ｇｅ）混晶
中のキャリアの移動度を示す図、
第８図及び第９図はＬＤＤ構造及びＤ３構造のＭＯ３Ｆ
ＥＴ夕模式側断面図
である。
図において、
１はｐ−型シリコン基板、
２はｐ型チャネルストッパ、
３はフィールド酸化膜、
４はゲート酸化膜、
５はゲート電極、
６は絶縁膜サイドウオール、
７．１０７はｎ−型（低濃度）ドレイン領域、８．１０
８はｎ−型（低濃度）ソース領域、９はｎ゛型（高濃度
）ドレイン領域、
１０はｎ“型（高濃度）ソース領域、
１１はチャネル形成領域、
１２は素子形成領域、
１３．１３Ａ 、 １３Ｂ 、 １１３．１１３Ａ、
１１３Ｂはゲルマニウム導入領域
を示す。
木か軸冶１ｎ実毛移・１ｎ孕郁撲式１し・ｊ前面置県
１ 図
本１ｅＡｆｒｌＺｎ 大１ｆ！９；゛ｈｎ’Ｈｐ＃−に
’＋Ｗ−ＩＷｒ？ｎ７も Ｚ 図
本杷明カ第３〜涜例ｎ要卸櫻式側齢面日第 ３ 国
人息明め第４ｎ火扮例の参部模式計Ｉ剪ｉ図裏 ４−
回
第 ５ 図
水息明刀イ芒ｒ屯用金”１の安部模式側幼′面図躬 ６
回1, 2, 3, and 4 are the first and second embodiments of the present invention.
, FIGS. 5 and 6 are schematic side sectional views of the main parts of different application examples of the present invention, and FIG. 7 is a schematic side view showing the main parts of the third and fourth embodiments. Diagrams showing carrier mobility in mixed crystals, Figures 8 and 9 are MO3F with LDD structure and D3 structure.
ET is a schematic side sectional view. In the figure, 1 is a p-type silicon substrate, 2 is a p-type channel stopper, 3 is a field oxide film, 4 is a gate oxide film, 5 is a gate electrode, 6 is an insulating film sidewall, and 7.107 is an n-type ( low concentration) drain region, 8.10
8 is an n-type (low concentration) source region, 9 is an n'' type (high concentration) drain region, 10 is an n'' type (high concentration) source region, 11 is a channel formation region, 12 is an element formation region, 13. 13A, 13B, 113.113A,
113B indicates a germanium introduction region. Tree or axis 1n real hair transfer, 1n pregnancy wrestling ceremony 1shi, j front setting prefecture
1 Illustration book 1eAfrlZn Large 1f! 9;゛hn'Hp#-ni'+W-IWr? n7 also Z Zuhon lomeika 3rd to blasphemous example n required wholesale Sakura style side age face day 3rd kokujin shimei 4n fire example part model meter I cut i figure back 4-
No. 5 Illustration of the Abe model side of the Water Breathing Sword and the Agon and Tun Yōkin 1 6
times
Claims (1)
であって、 少なくともチャネル形成領域におけるドレイン接合の近
傍領域に、ゲルマニウム原子が導入されてなることを特
徴とするＭＩＳ型半導体装置。[Scope of Claim] An MIS type semiconductor device formed on a silicon semiconductor substrate, characterized in that germanium atoms are introduced into at least a region near a drain junction in a channel forming region.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP27131387A JPH01112772A (en) | 1987-10-27 | 1987-10-27 | Mis-type semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP27131387A JPH01112772A (en) | 1987-10-27 | 1987-10-27 | Mis-type semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01112772A true JPH01112772A (en) | 1989-05-01 |
Family
ID=17498308
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP27131387A Pending JPH01112772A (en) | 1987-10-27 | 1987-10-27 | Mis-type semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01112772A (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0311731A (en) * | 1989-06-09 | 1991-01-21 | Nippon Telegr & Teleph Corp <Ntt> | Manufacture of semiconductor device |
| JPH03119732A (en) * | 1989-09-22 | 1991-05-22 | American Teleph & Telegr Co <Att> | Neutral impurity for increasing opera- tional life of semiconductor device |
| JPH03194962A (en) * | 1989-12-22 | 1991-08-26 | Mitsubishi Electric Corp | Semiconductor device |
| US5089872A (en) * | 1990-04-27 | 1992-02-18 | North Carolina State University | Selective germanium deposition on silicon and resulting structures |
| WO2005093812A1 (en) * | 2004-03-25 | 2005-10-06 | Commissariat A L'energie Atomique | Transistor with adapted source, drain and channel materials and integrated circuit comprising same |
| JP2019510365A (en) * | 2016-01-13 | 2019-04-11 | エルファウンドリー ソチエタ レスポンサビリタ リミタータ | Manufacturing method of near infrared CMOS sensor |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6313379A (en) * | 1986-07-04 | 1988-01-20 | Nippon Telegr & Teleph Corp <Ntt> | Semiconductor device and manufacture thereof |
| JPS6313378A (en) * | 1986-07-04 | 1988-01-20 | Nippon Telegr & Teleph Corp <Ntt> | Semiconductor device and manufacture thereof |
| JPS6356952A (en) * | 1986-08-28 | 1988-03-11 | Yokogawa Electric Corp | Semiconductor resistance element |
-
1987
- 1987-10-27 JP JP27131387A patent/JPH01112772A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6313379A (en) * | 1986-07-04 | 1988-01-20 | Nippon Telegr & Teleph Corp <Ntt> | Semiconductor device and manufacture thereof |
| JPS6313378A (en) * | 1986-07-04 | 1988-01-20 | Nippon Telegr & Teleph Corp <Ntt> | Semiconductor device and manufacture thereof |
| JPS6356952A (en) * | 1986-08-28 | 1988-03-11 | Yokogawa Electric Corp | Semiconductor resistance element |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0311731A (en) * | 1989-06-09 | 1991-01-21 | Nippon Telegr & Teleph Corp <Ntt> | Manufacture of semiconductor device |
| JPH03119732A (en) * | 1989-09-22 | 1991-05-22 | American Teleph & Telegr Co <Att> | Neutral impurity for increasing opera- tional life of semiconductor device |
| JPH03194962A (en) * | 1989-12-22 | 1991-08-26 | Mitsubishi Electric Corp | Semiconductor device |
| US5089872A (en) * | 1990-04-27 | 1992-02-18 | North Carolina State University | Selective germanium deposition on silicon and resulting structures |
| WO2005093812A1 (en) * | 2004-03-25 | 2005-10-06 | Commissariat A L'energie Atomique | Transistor with adapted source, drain and channel materials and integrated circuit comprising same |
| US7566922B2 (en) | 2004-03-25 | 2009-07-28 | Commissariat A L'energie Atomique | Field effect transistor with suitable source, drain and channel materials and integrated circuit comprising same |
| JP2019510365A (en) * | 2016-01-13 | 2019-04-11 | エルファウンドリー ソチエタ レスポンサビリタ リミタータ | Manufacturing method of near infrared CMOS sensor |
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