JPH01111375A - Gate turn-off thyristor - Google Patents
Gate turn-off thyristorInfo
- Publication number
- JPH01111375A JPH01111375A JP26970687A JP26970687A JPH01111375A JP H01111375 A JPH01111375 A JP H01111375A JP 26970687 A JP26970687 A JP 26970687A JP 26970687 A JP26970687 A JP 26970687A JP H01111375 A JPH01111375 A JP H01111375A
- Authority
- JP
- Japan
- Prior art keywords
- oxide film
- width
- segment
- emitter
- longitudinal direction
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 abstract description 4
- 238000005530 etching Methods 0.000 description 16
- 239000000758 substrate Substances 0.000 description 7
- 230000015556 catabolic process Effects 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 230000007547 defect Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 239000007788 liquid Substances 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 description 1
- 238000005299 abrasion Methods 0.000 description 1
- 239000002253 acid Substances 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000007598 dipping method Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 229910017604 nitric acid Inorganic materials 0.000 description 1
- 231100000989 no adverse effect Toxicity 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
Landscapes
- Thyristors (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、交互に異なる導電型を有する内側の二つのベ
ース層と外側の二つのエミッタ層からなる隣接する四つ
の層からなり、一方の第一導電型のエミッタ層が複数の
短冊状の突出部として形成され、その間に存在する第二
導電型のベース層の表面にゲート電極が設けられるゲー
ト・ターン・オフ（以下ＧＴＯと記す）サイリスタに関
する。Detailed Description of the Invention [Field of Industrial Application] The present invention consists of four adjacent layers consisting of two inner base layers and two outer emitter layers having alternately different conductivity types; A gate turn-off (hereinafter referred to as GTO) thyristor in which a first conductivity type emitter layer is formed as a plurality of strip-shaped protrusions, and a gate electrode is provided on the surface of a second conductivity type base layer existing between them. Regarding.
上述のような短冊状メサ形ｎエミッタ構造を持つＧＴＯ
サイリスタの断面を第２図に示す。シリコン基板１０は
、ｐ形およびｎ形の二つの異なる導電領域が相接したｐ
ｎｐｎの４層からなり、一方の主面には短冊状の分離独
立したｎエミッタ層１が形成されるとともに中間層のｐ
ベース層２が露出している。ｐベース層２の他方にはｎ
ベース層３、ｐエミッタ層４が形成されている。ｎエミ
ッタとｐベース界面のｐｎ接合５が前記ｎエミッタ層１
を含む短冊状凸部 （以下セグメントと略す）の側面に
露出しており、酸化膜６によって保護されている。この
セグメントの頂部にはカソード電極７１が、ｐベース層
２の露出部にはゲート電極７２が、他方の主面側のｐエ
ミッタ層４にはアノード電極７３がそれぞれ設けられて
いる。GTO with a strip-shaped mesa-type n emitter structure as described above
A cross section of the thyristor is shown in FIG. The silicon substrate 10 has a p-type conductive region in which two different conductive regions, p-type and n-type, are in contact with each other.
Consisting of four npn layers, a strip-shaped separated and independent n emitter layer 1 is formed on one main surface, and an intermediate layer p
Base layer 2 is exposed. The other side of the p base layer 2 has n
A base layer 3 and a p emitter layer 4 are formed. The pn junction 5 at the interface between the n emitter and the p base forms the n emitter layer 1.
It is exposed on the side surface of a rectangular convex portion (hereinafter abbreviated as a segment) including the segment, and is protected by an oxide film 6. A cathode electrode 71 is provided on the top of this segment, a gate electrode 72 is provided on the exposed portion of the p base layer 2, and an anode electrode 73 is provided on the p emitter layer 4 on the other main surface side.
第３図には、単位ＧＴＯサイリスクであるセグメント２
０を同心円状に配置したＧＴＯサイリスクの一例を基板
１０の平面図で示す。セグメント２０は、通常短冊状の
形をしており、長手方向の両端はほぼ円弧状である。Figure 3 shows segment 2, which is the unit GTO Cyrisk.
An example of a GTO cyrisk in which 0's are arranged concentrically is shown in a plan view of a substrate 10. The segment 20 usually has a rectangular shape, and both ends in the longitudinal direction are approximately arcuate.
セグメント２０は通常、ぶつ酸硝酸混合液からエツチン
グ液を用いて形成する。このエツチングには、シリコン
からなる半導体基体をエツチング液にひたし、半導体基
体を回転させる回転エツチング法が従来行われている。Segments 20 are typically formed using an etching solution from a mixture of butic acid and nitric acid. Conventionally, this etching is carried out by a rotational etching method in which a semiconductor substrate made of silicon is immersed in an etching solution and the semiconductor substrate is rotated.
この回転エツチング法は、単にエツチング液にひたす場
合に比べて均等にエンチングできる利点がある。この場
合、エツチング深さを深くすると、ｎエミッタ１の直下
でゲート電極７２までの横方向抵抗８が大きくなり、可
制御電流が小さ（なるので、この深さを浅くする必要が
ある。同時にゲート電極７２の端をなるべ（ｐｎ接合５
に近付ける必要がある。This rotary etching method has the advantage that it can be etched more evenly than simply dipping it in an etching solution. In this case, if the etching depth is increased, the lateral resistance 8 directly below the n-emitter 1 to the gate electrode 72 will increase, and the controllable current will become smaller (so this depth must be made shallower. Connect the end of the electrode 72 (pn junction 5
need to be close to.
ｐｎ接合５の露出部を保護する酸化膜６は、露出部表面
に酸化膜を成膜した後ホトエツチングにより同一幅に形
成されるが、その幅を広くするとゲート電極７２の端と
ｐｎ接合５との距離が長くなり、横方向抵抗８が大きく
なる。The oxide film 6 that protects the exposed portion of the pn junction 5 is formed to have the same width by photo-etching after forming an oxide film on the surface of the exposed portion, but if the width is increased, the end of the gate electrode 72 and the pn junction 5 are formed. The distance becomes longer, and the lateral resistance 8 becomes larger.
第４図（ａｌはセグメント部２０表面に平行な面への酸
化膜６０投影図で、そのＡ−Ａ’線、Ｂ−Ｂ″線断面を
第４図Ｑ）ｌに示す。回転エツチング法で行なう場合、
シリコン基板１０表面のエツチング液の流れは放射状と
なり、セグメント２０の幅の狭い長手方向平行部のエツ
チング流の流れは円滑で、第４図ｔａｌのＡ−Ａ″線断
面における第４図（′ｂ）のエツチング面２１に示すよ
うにｐｎ接合５の露出部が確実に酸化膜６で覆われてい
る。しかし、両端のほぼ円弧状の部分でのエツチング流
の流れは円滑でなく、第４図（５）のＢ−Ｂ’線断面に
おける第４図（１））のエンチング面２２に示すように
エツチングが不十分な状態になり、ｐｎ接合部５が酸化
膜６に覆われなくなる。後の工程によりゲートを極７２
を形成すると、酸化膜６よりはみ出したｐｎ接合部５が
ゲート電極７２と接触するため、ゲート７２とカソード
７１の間の逆耐圧の不良が発生する。特にエツチング深
さを浅くすると面２２の曲率が小さくなり、この不良が
発生しやすい。この不良を防止するには酸化膜６の幅を
広くすることが有効であるが、上述のようにこれには制
約がある。FIG. 4 (Al is a projection view of the oxide film 60 on a plane parallel to the surface of the segment portion 20, and its cross section along the lines AA' and B-B'' is shown in FIG. 4Q)l. If you do
The flow of the etching liquid on the surface of the silicon substrate 10 is radial, and the flow of the etching liquid on the narrow longitudinal parallel portions of the segments 20 is smooth. ), the exposed portion of the pn junction 5 is reliably covered with the oxide film 6. However, the etching flow is not smooth in the approximately arc-shaped portions at both ends, as shown in FIG. As shown in the etched surface 22 in FIG. 4 (1) in the cross section taken along the line B-B' in (5), the etching becomes insufficient and the pn junction 5 is no longer covered with the oxide film 6. Depending on the process, the gate can be set to pole 72.
, the pn junction 5 protruding from the oxide film 6 comes into contact with the gate electrode 72, resulting in a reverse breakdown voltage failure between the gate 72 and the cathode 71. In particular, when the etching depth is made shallow, the curvature of the surface 22 becomes small, and this defect is likely to occur. In order to prevent this defect, it is effective to widen the width of the oxide film 6, but as mentioned above, there are restrictions on this.
本発明の目的は、上記の問題を解決し、セグメントのエ
ミッタ直下からゲート電極までの横方向抵抗を小さくし
て可制御１ｉ流の向上を図ったＧＴＯサイリスクのエミ
ッタと隣接ベース間のｐｎ接合が酸化膜に完全に覆われ
、逆耐圧不良をなくすることにある。The purpose of the present invention is to solve the above problems and improve the controllable 1i current by reducing the lateral resistance from just below the emitter of the segment to the gate electrode. The purpose is to completely cover the oxide film and eliminate reverse breakdown voltage defects.
上記の目的を達成するために、本発明は、交互に異なる
導電型を有する内側の二つのベース層と外側の二つの層
からなる隣接する４層よりなり、一方の第一導電型のエ
ミッタ眉が複数の短冊状の突出部として形成されてその
表面にエミッタ電極が設けられ、その間の低部に存在す
る第二導電型のベース層の表面にゲート電極が設けられ
、エミッタＲｈとゲート電極の間の表面へのｐｎ接合の
露出部が絶縁膜で覆われるＧＴＯサイリスクにおいて、
短冊状エミッタ層表面の長手方向平行部の外側の絶ａ膜
の幅よりエミッタ層表面の長手方向両端部の外側の絶縁
膜の幅が広いものとする。To achieve the above object, the present invention consists of four adjacent layers consisting of two inner base layers and two outer layers with alternating different conductivity types, one emitter layer of the first conductivity type. is formed as a plurality of strip-shaped protrusions, and an emitter electrode is provided on the surface of the protrusion, and a gate electrode is provided on the surface of the base layer of the second conductivity type that exists in the lower part between them, and the emitter Rh and the gate electrode are provided with an emitter electrode. In GTO Sirisk, where the exposed part of the pn junction to the surface between is covered with an insulating film,
The width of the insulating film on the outside of both ends of the emitter layer surface in the longitudinal direction is wider than the width of the insulating film on the outside of the parallel portions of the strip-shaped emitter layer surface in the longitudinal direction.
短冊状エミッタ層長手方向両端部の外側のｐｎ接合を覆
う絶縁膜の幅を広くすることにより、エツチング不足で
エミッタ層表面からｐｎ接合の露出部までの距離が大き
い場合も絶縁膜がｐｎ接合を確実に覆うため、逆耐圧不
良の発生することがない。By widening the width of the insulating film that covers the pn junction on the outside of both ends of the strip-shaped emitter layer in the longitudinal direction, the insulating film can close the pn junction even if the distance from the emitter layer surface to the exposed part of the pn junction is large due to insufficient etching. Since it is securely covered, there is no possibility of reverse breakdown voltage failure.
〔実施例〕
第１図に本発明の一実施例を示す。短冊状に突出したセ
グメントを側面を含めて表面に平行な面に投影した場合
のエミッタ電極の被着部を囲む酸化膜６の形状を示す。[Example] FIG. 1 shows an example of the present invention. The shape of the oxide film 6 surrounding the emitter electrode attachment part is shown when a rectangular protruding segment is projected onto a plane parallel to the surface including the side surfaces.
短冊状セグメントの狭幅部の酸化膜の帯の幅ｄ１に比べ
長手方向のほぼ円弧部の外側の酸化膜の幅むは広くなっ
ている。The width of the oxide film on the outside of the substantially circular arc portion in the longitudinal direction is wider than the width d1 of the oxide film band on the narrow portion of the strip-shaped segment.
狭幅部の酸化膜帯の幅ｄ１を従来の値の９０ｐｔａにし
ｃｌ。The width d1 of the oxide film band in the narrow portion is set to the conventional value of 90 pta cl.
た場合でも、両端での酸化膜のＩＰ＋ ２６ Ｏｎにし
た場合は、凸状セグメントを形成するゲートエッチング
深さを従来よりも５〜１０ｘ浅くしてもゲート・カソー
ド間の逆耐圧の低下は発生しなかった。このことは、セ
グメントの長手方向両端部の酸化膜幅を広げたことによ
り、ｐｎ接合面露出部５を確実に酸化膜により覆うこと
が可能であることを意味する。Even if the oxide film at both ends is set to IP+26 On, the reverse breakdown voltage between the gate and cathode will not decrease even if the gate etching depth to form the convex segment is made 5 to 10x shallower than before. I didn't. This means that by increasing the width of the oxide film at both ends in the longitudinal direction of the segment, it is possible to reliably cover the pn junction surface exposed portion 5 with the oxide film.
このように、ゲートエツチング深さを浅くすることによ
ってｐベース横方向砥抗８が低下し、可制御電流が２０
〜３０％増大した。ＧＴＯサイリスタのターン・オフ時
のゲート電極７２よりのゲート電流引きぬきに関しては
、セグメントの長手方向両端部において酸化膜幅ｄｔを
大きくすることによりｎエミッタとゲート電極間距離は
広がるが、セグメントの長手方向平行部で均等にゲート
電流の引きぬきが達成されるので、可制御電流に何ら悪
影響を与えない。Thus, by reducing the gate etching depth, the p-base lateral abrasion 8 is reduced, and the controllable current is reduced to 20
~30% increase. Regarding the gate current drawn from the gate electrode 72 during turn-off of the GTO thyristor, the distance between the n emitter and the gate electrode increases by increasing the oxide film width dt at both longitudinal ends of the segment. Since the gate current is drawn evenly in the direction parallel portions, there is no adverse effect on the controllable current.
第５図５第６図に他の実施例を示す。第５図の実施例で
は酸化膜の輪郭もセグメントと同様に両端が円弧状では
あるが相似形ではなく、ｄｔがｄｌより広い、第６図の
実施例では酸化膜６は両端でセグメントの長手方向に直
角方向にも幅ｄ、をｄ、より広くとっている。以上の本
発明の実施例は、短冊状セグメント２０を第３図に示す
ように基板１０に放射状に配置した場合であって、ＧＴ
Ｏエレメントの中心方向に近い一方の端部と外周側の他
方の端部については、その広げた酸化膜の幅は両方とも
同じであってもよいが、外周側ではｐｎ接合の形がくず
れやすいので外周側端部の酸化膜の幅の方を広くするこ
とも有効である。しかし、本発明はセグメントの細部形
状やその配置方法によって制限されるものではない。ま
たｐｎ接合露出部を覆い、エミッタ電極７１とゲート電
極７２との間を絶縁する保護膜は酸化膜６以外の絶縁膜
であってもよい。Another embodiment is shown in FIG. 5 and FIG. 6. In the embodiment shown in FIG. 5, the outline of the oxide film is arcuate at both ends like the segment, but they are not similar, and dt is wider than dl. In the embodiment shown in FIG. Also in the direction perpendicular to the direction, the width d is wider than d. In the embodiment of the present invention described above, the strip segments 20 are arranged radially on the substrate 10 as shown in FIG.
Regarding one end near the center of the O element and the other end on the outer periphery side, the width of the expanded oxide film may be the same for both, but the shape of the pn junction tends to collapse on the outer periphery side. Therefore, it is also effective to increase the width of the oxide film at the outer peripheral end. However, the present invention is not limited by the detailed shapes of the segments or how they are arranged. Further, the protective film that covers the exposed pn junction portion and insulates between the emitter electrode 71 and the gate electrode 72 may be an insulating film other than the oxide film 6.
本発明によれば、ＧＴＯサイリスクの短冊状セグメント
の長手方向両端部で絶縁膜の幅を長手方向平行部より広
くすることにより、セグメント形成のためのエツチング
深さを浅くしてもセグメント両端部でのｐｎ接合露出部
が絶縁膜で覆われないおそれが除かれ、エミッタ直下か
らゲート電極までのベース横方向抵抗を減少させて可制
御電流の増大したＧＴＯサイリスタを逆耐圧低下なしに
得ることができた。According to the present invention, by making the width of the insulating film wider at both longitudinal ends of the strip-shaped segment of GTO Silisk than at the parallel longitudinal part, even if the etching depth for segment formation is made shallow, the width of the insulating film at both longitudinal ends of the strip-shaped segment of the GTO SIRISK is made wider than at the parallel parts in the longitudinal direction. This eliminates the possibility that the exposed part of the pn junction is not covered with an insulating film, reduces the lateral resistance of the base from just below the emitter to the gate electrode, and makes it possible to obtain a GTO thyristor with increased controllable current without lowering the reverse breakdown voltage. Ta.
【図面の簡単な説明】
第１図は本発明の一実施例の酸化膜のセグメント表面に
平行な面への投影図、第２図はＧＴＯサイリスクの要部
断面図、第３図はＧＴＯサイリスク基板の平面図、第４
図＋ａ＋、 （ｂｌは従来のＧＴＯサイリスタの問題点
を示し、（ａ）は第１図と同様ｑ酸化膜投影図、山）は
＋ａ＋のＡ−Ａ’線およびＢ−８’線における断面図、
第５図、第６図はそれぞれ本発明の異なる実施例の第１
図と同様の酸化膜投影図である。
１：ｎエミッタ層、２：ｐベース層、５：ｐｎ接合、６
：酸化膜、ｌＯ：シリコン基板、２ｏ：セグメント。
第１図
第２図
第４図
第５図
第ｂｖＡ[Brief Description of the Drawings] Fig. 1 is a projection view of an oxide film according to an embodiment of the present invention onto a plane parallel to the segment surface, Fig. 2 is a cross-sectional view of the main part of GTO Syllisk, and Fig. 3 is a diagram of GTO Syllisk. Top view of the board, 4th
Figure +a+, (bl shows the problem of the conventional GTO thyristor, (a) is a q oxide film projection view similar to Figure 1, and the mountain) is a cross-sectional view of +a+ along the AA' line and B-8' line. ,
FIG. 5 and FIG. 6 are the first embodiments of different embodiments of the present invention, respectively.
It is a projection view of an oxide film similar to the figure. 1: n emitter layer, 2: p base layer, 5: pn junction, 6
: oxide film, lO: silicon substrate, 2o: segment. Figure 1 Figure 2 Figure 4 Figure 5 bvA
Claims (1)
と外側の二つの層からなる４層よりなり、一方の第一導
電型のエミッタ層が複数の短冊状の突出部として形成さ
れてその表面にエミッタ電極が形成され、その間の低部
に存在する第二導電型のベース層の表面にゲート電極が
設けられ、エミッタ電極とゲート電極の間へのｐｎ接合
の露出部が絶縁膜で覆われるものにおいて、短冊状エミ
ッタ層表面の長手方向平行部の外側の絶縁膜の幅よりエ
ミッタ層表面長手方向両端部の外側の絶縁膜の幅が広い
ことを特徴とするゲート・ターン・オフ・サイリスタ。1) Consisting of four layers consisting of two inner base layers and two outer layers having alternately different conductivity types, one emitter layer of the first conductivity type is formed as a plurality of rectangular protrusions. An emitter electrode is formed on the surface, a gate electrode is provided on the surface of the base layer of the second conductivity type existing in the lower part between them, and the exposed part of the pn junction between the emitter electrode and the gate electrode is covered with an insulating film. A gate turn-off thyristor characterized in that the width of the outer insulating film at both longitudinal ends of the emitter layer surface is wider than the width of the outer insulating film at the longitudinally parallel parts of the strip-shaped emitter layer surface. .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP26970687A JPH01111375A (en) | 1987-10-26 | 1987-10-26 | Gate turn-off thyristor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP26970687A JPH01111375A (en) | 1987-10-26 | 1987-10-26 | Gate turn-off thyristor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01111375A true JPH01111375A (en) | 1989-04-28 |
Family
ID=17476051
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP26970687A Pending JPH01111375A (en) | 1987-10-26 | 1987-10-26 | Gate turn-off thyristor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01111375A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2005505913A (en) * | 2001-05-22 | 2005-02-24 | ゼネラル セミコンダクター，インク． | Low voltage punch-through bidirectional transient voltage suppressor and method for manufacturing the same |
| US6996150B1 (en) | 1994-09-14 | 2006-02-07 | Rohm Co., Ltd. | Semiconductor light emitting device and manufacturing method therefor |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5913372A (en) * | 1982-07-15 | 1984-01-24 | Hitachi Ltd | Semiconductor device |
-
1987
- 1987-10-26 JP JP26970687A patent/JPH01111375A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5913372A (en) * | 1982-07-15 | 1984-01-24 | Hitachi Ltd | Semiconductor device |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6996150B1 (en) | 1994-09-14 | 2006-02-07 | Rohm Co., Ltd. | Semiconductor light emitting device and manufacturing method therefor |
| US8934513B2 (en) | 1994-09-14 | 2015-01-13 | Rohm Co., Ltd. | Semiconductor light emitting device and manufacturing method therefor |
| JP2005505913A (en) * | 2001-05-22 | 2005-02-24 | ゼネラル セミコンダクター，インク． | Low voltage punch-through bidirectional transient voltage suppressor and method for manufacturing the same |
| JP4685333B2 (en) * | 2001-05-22 | 2011-05-18 | ゼネラル セミコンダクター，インク． | Low voltage punch-through bidirectional transient voltage suppressor |
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