JPH01109756A - Lead frame for semiconductor device - Google Patents
Lead frame for semiconductor deviceInfo
- Publication number
- JPH01109756A JPH01109756A JP26660187A JP26660187A JPH01109756A JP H01109756 A JPH01109756 A JP H01109756A JP 26660187 A JP26660187 A JP 26660187A JP 26660187 A JP26660187 A JP 26660187A JP H01109756 A JPH01109756 A JP H01109756A
- Authority
- JP
- Japan
- Prior art keywords
- plating
- solder
- layer
- lead frame
- thickness
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 18
- 238000000034 method Methods 0.000 claims abstract description 14
- 229910000881 Cu alloy Inorganic materials 0.000 claims abstract description 5
- 229910052802 copper Inorganic materials 0.000 claims abstract description 4
- 238000007747 plating Methods 0.000 claims description 87
- 229910000679 solder Inorganic materials 0.000 abstract description 64
- 229910018104 Ni-P Inorganic materials 0.000 abstract description 15
- 229910018536 Ni—P Inorganic materials 0.000 abstract description 15
- 239000000758 substrate Substances 0.000 abstract 3
- 230000009916 joint effect Effects 0.000 abstract 2
- 238000005452 bending Methods 0.000 description 22
- 229910045601 alloy Inorganic materials 0.000 description 14
- 239000000956 alloy Substances 0.000 description 14
- 230000004907 flux Effects 0.000 description 6
- 229910001096 P alloy Inorganic materials 0.000 description 5
- 238000011156 evaluation Methods 0.000 description 5
- 239000000243 solution Substances 0.000 description 5
- 229910018100 Ni-Sn Inorganic materials 0.000 description 4
- 229910018532 Ni—Sn Inorganic materials 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 238000005476 soldering Methods 0.000 description 4
- 238000010438 heat treatment Methods 0.000 description 3
- 238000006243 chemical reaction Methods 0.000 description 2
- 230000000052 comparative effect Effects 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 238000007772 electroless plating Methods 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 229910000532 Deoxidized steel Inorganic materials 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 230000032683 aging Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000003638 chemical reducing agent Substances 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 238000004320 controlled atmosphere Methods 0.000 description 1
- 238000010790 dilution Methods 0.000 description 1
- 239000012895 dilution Substances 0.000 description 1
- 230000005496 eutectics Effects 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 238000007654 immersion Methods 0.000 description 1
- 239000011261 inert gas Substances 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 229910052745 lead Inorganic materials 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 239000005416 organic matter Substances 0.000 description 1
- 230000001737 promoting effect Effects 0.000 description 1
- 238000006722 reduction reaction Methods 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 230000035945 sensitivity Effects 0.000 description 1
- 230000035882 stress Effects 0.000 description 1
- 229910052718 tin Inorganic materials 0.000 description 1
- 238000005406 washing Methods 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
- 239000002023 wood Substances 0.000 description 1
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
［産業上の利用分野］
本発明はトランジスタ等の半導体装置のリードフレーム
に係り、より詳細には、上記半導体を組立てる際の半導
体素子との半田接合性およびリード部の半田耐熱剥離性
を改善した半導体装置用リードフレームに関するもので
ある。[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a lead frame for a semiconductor device such as a transistor, and more particularly, it relates to a lead frame for a semiconductor device such as a transistor, and more particularly, to a method for solder bonding with a semiconductor element and a lead portion when assembling the semiconductor. The present invention relates to a lead frame for semiconductor devices with improved solder heat resistance and peelability.
［従来の技術］
一般にパワートランジスタ用半導体装置は、半導体素子
とリードフレームを半田によって加熱接合し、半導体素
子の電極部とリードフレームとの間をＡＪ２．またはＡ
ｕワイヤで配線した後、これら。[Prior Art] Generally, in a semiconductor device for a power transistor, a semiconductor element and a lead frame are heat-bonded by solder, and AJ2. or A
These after wiring with u wires.
の配線部を樹脂モールドし、最後にアクタ−リードに半
田付けして製造されている。The wiring part is molded in resin and finally soldered to the actor lead.
この半導体素子とリードフレームの半田接合（半田ダイ
ボンディング）においては、まずリードフレームを０２
？１度の管理された７囲気中で、ブロック上に載せて２
５０〜４００℃に加熱し、次いで半導体素子と接合させ
るべき部分に半田ボールあるいは半田リボン等を置いて
溶融させ、この溶融した半田上に半導体素子を置いて接
合させる方法が用いられている。In this solder bonding (solder die bonding) between the semiconductor element and the lead frame, first the lead frame is
? Place it on a block in a controlled atmosphere of 7 degrees.
A method is used in which the solder is heated to 50 to 400° C., then a solder ball or ribbon is placed on the part to be joined to the semiconductor element and melted, and the semiconductor element is placed on the melted solder and joined.
最近では、半導体素子の汚染を防止する目的で、フラッ
クスを使用せず不活性ガス雰囲気中において、半導体素
子とリードフレームを接合する方法が開発され、この方
法に対して表面酸化、表面汚染（乾燥シミ）の少ない極
めて清浄なリードフレームが要求される様になって来た
。Recently, in order to prevent contamination of semiconductor elements, a method of bonding semiconductor elements and lead frames in an inert gas atmosphere without using flux has been developed. There is a growing demand for extremely clean lead frames with few stains.
このフラックスを用いない半田ボンデインク法において
はＮｉ−Ｐめっきを施したリードフレームが主に用いら
れている。In this solder bonding method that does not use flux, a lead frame plated with Ni--P is mainly used.
Ｎｉ−Ｐ合金めっきを施したリードフレームが用いられ
る理由は、Ｎｉ−Ｐ合金めつき皮膜中のＰが、半田ボン
ディング時に用いられる半田組成物であるＳｎ、Ｐｂや
Ｎｉ−Ｐ合金めつきのＮｉより酸化されやすい性質を有
しており、半田ダイボンディング時に、半田ボール表面
やＮｉ−Ｐ合金めりき表面の酸化物を還元する効果を有
するためである。この様にＮｉ−Ｐ合金めつきは、フラ
ックスを使用しない半田ダイボンディング用に好適なめ
っきであるといえる。The reason why a lead frame with Ni-P alloy plating is used is that the P in the Ni-P alloy plating film is stronger than the Sn and Pb in the solder composition used during solder bonding and the Ni in the Ni-P alloy plating. This is because it has the property of being easily oxidized and has the effect of reducing oxides on the solder ball surface and the Ni-P alloy plated surface during solder die bonding. In this way, Ni-P alloy plating can be said to be a suitable plating for solder die bonding without using flux.
しかしながら、Ｎｉ−Ｐ合金めっきは通常のＮｉめつき
に比較して、めつきコストが高いこと、また、めっき皮
膜の硬度がＨｖ６００以上を示し難く、Ｎｉ−Ｐ合金め
つきを施したリードフレームのアウターリード部の曲げ
加工・において、クラックを発生する等の問題を有して
いる。However, Ni-P alloy plating has a higher plating cost than normal Ni plating, and it is difficult for the plating film to show a hardness of Hv600 or higher. There are problems such as cracks occurring during bending of the outer lead portion.
これらの問題点に対し、ＮｉめつきとＮｉ−Ｐ合金めっ
きを積層した二層めっきが特公昭６０−３３３１２号公
報にて開示されている。To solve these problems, Japanese Patent Publication No. 60-33312 discloses two-layer plating in which Ni plating and Ni--P alloy plating are laminated.
二層めっきの理想的な構成としては、素地Ｃｕ合金にＮ
ｉめつきを施こし、その上層に良好な半田ダイボンディ
ング性を有する最小のめつき厚みのＮｉ−Ｐ合金めつき
を行なう方法が良いと考えられる。The ideal structure for two-layer plating is N on the base Cu alloy.
It is considered that a method of applying i-plating and then plating an Ni--P alloy with a minimum plating thickness that has good solder die bonding properties on the upper layer is considered to be a good method.
すなわち、Ｎｉめつきを施こすことにより、半田ダイボ
ンディングを行なう際の加熱によって、Ｃｕがダイボン
ディング表面に拡散するのを防止することができ、かつ
、Ｎｉ−Ｐ合金めつきを最小の厚みとしたことにより、
コストも、低下し、かつ、曲げ加工も容易となる。That is, by applying Ni plating, Cu can be prevented from diffusing onto the die bonding surface due to heating during solder die bonding, and the Ni-P alloy plating can be minimized in thickness. By doing this,
The cost is also reduced and bending becomes easier.
特にめっきコスト、曲げ加工性の点でＮｉ−Ｐ合金めつ
き厚みを薄く設けることは重要であり、そのためにＮｉ
−Ｐ合金めつきの均一な厚みの皮膜を設けるため、下層
のＮｉめつき表面としてはカラーデンシトメータ値１．
２〜２．０程度の光沢あるいは半光沢めっきを用いるこ
とが望ましいと考えられている。In particular, it is important to make the Ni-P alloy plating thin in terms of plating cost and bending workability.
- In order to provide a P alloy plating film with a uniform thickness, the lower Ni plating surface has a color densitometer value of 1.
It is considered desirable to use gloss or semi-gloss plating of about 2 to 2.0.
しかしながら、一般に、二層めっきはＮｉ−Ｐ合金めっ
き一層のみで構成されためっきに比較して、半田付は後
の熱経時により半田層の剥離を生じやすい。However, in general, two-layer plating is more likely to cause peeling of the solder layer due to subsequent heat aging than plating composed of only one layer of Ni--P alloy plating.
半田の加熱剥離は、半田付は後のＮｉあるいはＮｉ−Ｐ
合金めっきと半田層の接合界面において熱履歴を受ける
ことにより、Ｎｉ−Ｓｎ合金層が形成され、リード部の
曲げ加工時にＮｉ−Ｓｎ合金層内で剥離を生じる現象で
あり、従来の二層めっきではＮｉ−Ｓｎ合金層が二層め
っきの境界に達した時最も剥離を生じやすい、また、め
っき層の硬さによっても半田の加熱剥離の感受性が異な
り下層Ｎｉめっき層の硬度が高いもの程、曲げ加工時に
クラックを生じると共に曲げ応力がＮｉ−Ｓｎ合金層に
作用し、剥離を助長する。Heat peeling of solder is performed after soldering with Ni or Ni-P.
This is a phenomenon in which a Ni-Sn alloy layer is formed due to thermal history at the bonding interface between the alloy plating and the solder layer, and peeling occurs within the Ni-Sn alloy layer during bending of the lead. In this case, peeling is most likely to occur when the Ni-Sn alloy layer reaches the boundary between the two-layer plating, and the sensitivity to solder heating peeling also varies depending on the hardness of the plating layer, and the harder the lower Ni plating layer is, the more Cracks occur during bending, and bending stress acts on the Ni-Sn alloy layer, promoting peeling.
このため半導体組立て後アクタ−リード部のめつき層を
化学的に溶解するか、あるいはアクタ−リード部を除い
て他の部分にＮｉめっきを施こす方法がとられているが
、これらの方法ではコストが高くつくという欠点を有し
ていた。For this reason, methods are used to chemically dissolve the plating layer on the actor lead after semiconductor assembly, or to apply Ni plating to other parts except for the actor lead. It had the disadvantage of being expensive.
［発明が解決しようとする問題点］
本発明は以上の問題点を解決するためになされたもので
あって、安定した半田接合性を維持しつつ、かつ、アウ
ターリード部の半田耐熱剥離性を。[Problems to be Solved by the Invention] The present invention has been made to solve the above-mentioned problems, and it is possible to maintain stable solder bonding properties and improve the solder heat-resistant peelability of the outer lead portion. .
改善したリードフレームを提供せんとするものである。The present invention aims to provide an improved lead frame.
［問題点を解決するための手段］
本発明は、ＣｕあるいはＣｕ合金下地、当該Ｃｕ下地表
面に形成されたカラーデンシトメータ値０．５〜１．０
の無光沢Ｎｉめつき層と、当該めっき層上に形成された
膜厚０．０５〜０．５μｍのＮｉ−Ｐめっき層と、によ
り構成されており、当該Ｎｉ−Ｐめっき層は無電解法に
り形成されていることを特徴とする半導体装置用リード
フレームに要旨が存在する。[Means for Solving the Problems] The present invention provides a Cu or Cu alloy base, and a color densitometer value of 0.5 to 1.0 formed on the surface of the Cu base.
It is composed of a matte Ni plating layer of The subject matter is a lead frame for a semiconductor device, which is characterized in that it is formed of a laminate.
［作用］
本発明者等はフラックスを使用せずに優れた半田ダイボ
ンディング性を有し、かつ、リード部の半田耐熱剥離性
、曲げ加工性の優れた二層めっき方法について鋭意研究
を行なった結果、半導体素子と半田接合されるリードフ
レームにおいて、その表面にカラーデンシトメータ値０
．５〜１．０の無光沢Ｎｉめっき層を設け、ついで無電
解法によるＰを含有するＮｉめっき層を０．０５〜０．
５μｍ積層することにより、木問題点を解決することが
可能なことを見出した。[Function] The present inventors have conducted intensive research on a two-layer plating method that has excellent solder die bonding properties without using flux, and has excellent solder heat peeling resistance and bending workability of the lead part. As a result, the surface of the lead frame that is soldered to the semiconductor element has a color densitometer value of 0.
．． A matte Ni plating layer with a thickness of 0.5 to 1.0% is provided, and then a Ni plating layer containing P by an electroless method is applied with a thickness of 0.05 to 0.0%.
It has been found that the wood problem can be solved by laminating 5 μm thick layers.
本発明の特徴とするところは以下の通りである。The features of the present invention are as follows.
（１）下層めっき層としてカラーデンシトメータ値０．
５〜１．０の無光沢めっきを行なうことにより半田耐熱
剥離性、曲げ加工性を改善した。(1) As the lower plating layer, the color densitometer value is 0.
By performing matte plating of 5 to 1.0, the solder heat peeling resistance and bending workability were improved.
すなわち、■半田の加熱剥離は、半田とＮｉの反応によ
るＮｉ−３ｎ合金層の厚みが二層めっきの境界に達した
時に、最も発生しやすいとの知見を得たことから、二層
めっき間の接合力を強化することを検討し、Ｎｉめっき
の光沢度を管理し、めっき表面の粗度を粗くすることに
より、半田耐熱剥離性を改善できる事を確認した。In other words, it was found that heat peeling of solder is most likely to occur when the thickness of the Ni-3n alloy layer due to the reaction between the solder and Ni reaches the boundary between the two-layer plating. We investigated ways to strengthen the bonding strength of the Ni plating, and confirmed that the solder heat resistance and peelability could be improved by controlling the glossiness of the Ni plating and increasing the roughness of the plating surface.
■さらにリード部の曲げ加工性を改善するために、光沢
剤を含まないめっき液を用いた。すなわち、上記めっき
液を用いることにより、有機物の共析が無く、めっき皮
膜硬度の低い皮膜を形成させることが出来、本目的に最
適であることを確認した。■Furthermore, in order to improve the bending workability of the lead part, we used a plating solution that does not contain brighteners. That is, by using the above plating solution, it was possible to form a film with low plating film hardness without eutectoiding of organic matter, and it was confirmed that it is optimal for this purpose.
（２）上層めっきに無電解めっきを行なうことにより良
好で安定した半田接合性を得ることができた。(2) By performing electroless plating on the upper layer plating, it was possible to obtain good and stable solder bondability.
すなわち、■本発明は下層めっきを上記理由により粗度
の粗い無光沢めっきと設定したため、粗度の粗い下層め
っき表面に均一で薄いめっきを形成させることが必要で
あり、複雑な形状においても均一なめっき厚みが得られ
る無電解めつきが最適であ委。In other words, ■ In the present invention, the lower layer plating is set to be a matte plating with a rough surface for the above reasons, so it is necessary to form a uniform and thin plating on the rough surface of the lower layer plating, and it is necessary to form a uniform and thin plating on the rough surface of the lower layer plating. Electroless plating is the best option as it provides a smooth plating thickness.
また、■無電解Ｎｉ−Ｐめっきは、化学的な還元反応に
よりＮｉ−Ｐめっきが析出するため、電解法によるＮｉ
−Ｐめっきに比べめっき表面の酸化皮膜の形成が薄く、
安定した半田接合性が得られるものと考えられる。In addition, in electroless Ni-P plating, Ni-P plating is precipitated by a chemical reduction reaction.
-The formation of an oxide film on the plating surface is thinner than P plating,
It is thought that stable solder bondability can be obtained.
以下に数値限定の理由を述べる。The reasons for the numerical limitations are explained below.
（１）下層めっきのカラーデンシトメータ値を０．５〜
１．０と限定したのは、０．５以下では一般にＮｉめっ
き結晶粒が明瞭な粒状を呈し、その影響が上層めっきま
でおよび、半田接合時の半田ボールの広がりを妨げる作
用があるため、下限を０．５とした。一方、上限の１．
０を越えると、Ｎｉめっき結晶粒が比較的平滑となり、
半田接合性には大きな影響はないものの、めつき皮膜の
曲げ加工性の低下および半田耐熱剥離性の低下を生じる
。よフて上限を１．０とした。(1) Color densitometer value of lower layer plating is 0.5~
The lower limit was set at 1.0 because if it is less than 0.5, the Ni plating crystal grains will generally take on a clear granular shape, which will affect the upper layer plating and prevent the spread of solder balls during solder joints. was set to 0.5. On the other hand, the upper limit of 1.
When it exceeds 0, the Ni plating crystal grains become relatively smooth,
Although it does not have a large effect on solder bondability, it causes a decrease in bending workability of the plating film and a decrease in solder heat resistance and peelability. Therefore, the upper limit was set to 1.0.
（２）無電解Ｎ ｉ −Ｐめっき厚みを０．０５〜０．
５μｍとしたのは、０．５μｍ以下では、均一な皮膜が
得られる無電解法といえども、実際上良好な半田拡がり
性を得ることが難しい、従って０．０５μｍを安定した
半田接合性が得られる下限とした。一方０．０５μｍ以
上では、半ｉ接合性は特に低下する訳ではないが、曲げ
加工性の低下をまねくのみで、めっき厚みの増加に見合
う効果がなくて不経済である。よって０．５μｍを上限
とした。(2) Electroless Ni-P plating thickness is 0.05-0.
The reason why we chose 5 μm is that if the thickness is 0.5 μm or less, it is difficult to obtain good solder spreadability in practice, even if it is an electroless method that can produce a uniform film. The lower limit was set as the lower limit. On the other hand, if the thickness is 0.05 μm or more, the semi-i bondability does not particularly decrease, but it only causes a decrease in bending workability, and is uneconomical because there is no effect commensurate with the increase in plating thickness. Therefore, the upper limit was set to 0.5 μm.
（実施例） 以下に実施例を挙げて本発明を具体的に説明する。(Example) The present invention will be specifically explained below with reference to Examples.
リードフレーム材としてりん脱酸鋼材を準備し、一般的
なトランジスタ用のフレーム形状ばリード部板厚０．５
ｍｍとしてスタンピングした０次いで、通常用いられる
めっき前処理を行なった後、下層めっき一水洗一上層め
っぎを連続して行なった。A phosphor deoxidized steel material is prepared as a lead frame material, and if the frame shape is a typical transistor, the lead part thickness is 0.5.
After stamping as mm, a commonly used pre-plating treatment was performed, followed by lower layer plating, water washing, and upper layer plating.
めっき後のサンプルについて半田接合性の判定としての
半田拡がり性、半田耐熱剥離性、曲げ加工性等の評価を
行った。なお、下層および上層めっき厚みの合計が１．
５μｍになるように設定した。The samples after plating were evaluated for solder spreadability, solder heat peeling resistance, bending workability, etc. to determine solder bondability. Note that the total thickness of the lower layer and upper layer plating is 1.
The thickness was set to 5 μm.
（１）まず、第１表に示すごとく下層メツキ条件を設定
した。また、上層めっきについては、下記のごとく設定
した。すなわち、
（２）上層めっき
・めっき液・・・無電解ＮＬ−Ｐ合金めっき液ブルーシ
ューマー液
（日本カニゼン社）５倍希釈
・温度・・・９０〜９２℃
・めつき厚み佛・・０．０３μｍ〜１．０μｍ上記めっ
き条件により得られた試料について前記したように、半
田拡がり性、半田耐熱剥離性、曲げ加工性等の評価を行
なうが、それぞれの評価方法について以下に説明する。(1) First, lower layer plating conditions were set as shown in Table 1. Furthermore, the upper layer plating was set as follows. That is, (2) Upper layer plating/plating solution...electroless NL-P alloy plating solution Blue Schumer's solution (Nippon Kanigen Co., Ltd.) 5 times dilution/temperature...90~92°C -Plating thickness...0. 03 μm to 1.0 μm As described above, the samples obtained under the above plating conditions were evaluated for solder spreadability, solder heat peeling resistance, bending workability, etc., and each evaluation method will be explained below.
半田拡がり性評価方法
・雰囲気・・−Ｎ２ガス
（０２濃度１０ｐｐｍ以下）
・半田ボール・・・９０Ｐｂ−１０Ｓｎ１．５ｍｍφ
・温度・・・４５０℃
・フラックス・・・使用せず
・評価方法・・・４５０℃に加熱され、たヒートステー
ジに試片をセットし試片が４５０℃に
達してから半田ボールを試片上に置
く、半田が自然に拡がるまでの時間
（秒）を測定した。Solder spreadability evaluation method / Atmosphere: -N2 gas (02 concentration 10 ppm or less) - Solder ball: 90Pb-10Sn 1.5 mmφ - Temperature: 450°C - Flux: Not used - Evaluation method... The sample was set on a heat stage heated to 450°C, and after the sample reached 450°C, a solder ball was placed on the sample, and the time (seconds) until the solder spread naturally was measured.
半田耐熱剥離性
めっき後のリードフレームを大気中３５０℃×５分→大
気中２００℃ｘ２４Ｈｒの加、熱を行なった後、リード
部を下記条件で半田付けした。The lead frame after solder heat-resistant peelability plating was heated in the atmosphere at 350°C for 5 minutes → in the air at 200°C for 24 hours, and then the lead portions were soldered under the following conditions.
・半田組成−５ｎ６３−Ｐｂ３７ （共晶）・半田温度
・・・２６０℃
・浸漬時間・・・５秒
・フラックス・・・水溶性活性フランクス半田付は後の
試片を１２５℃に保持された加熱炉にて加熱し５０Ｈｒ
、１００Ｈｒ、１５０Ｈｒ経過後リ一ド部の曲げ加工（
曲げ半径０．５Ｒ）にて半田層の剥離の有無を調査した
。・Solder composition: 5n63-Pb37 (eutectic) ・Solder temperature: 260°C ・Immersion time: 5 seconds ・Flux: water-soluble activated Franks soldering The specimen after soldering was kept at 125°C Heated in a heating furnace for 50 hours
, after 100 hours and 150 hours, bending of the lead part (
The presence or absence of peeling of the solder layer was investigated at a bending radius of 0.5R).
曲げ加工性
半田耐熱剥離性と同条件で熱履歴を受け、リード部に半
田付けを行なった試片に９いて、リード部を０．５Ｒに
て９０″″の曲げを行ない曲げ加工部のクラックの発生
状況を調査した。Bending workability Soldering heat resistance Peeling resistance A test piece was subjected to heat history under the same conditions as the lead part and was soldered. The situation of occurrence was investigated.
以上の試験結果を第２表に示す。評価基準は下記のごと
く定めた。The above test results are shown in Table 2. The evaluation criteria were determined as follows.
すなわち、
評価基準
・半田拡がり性・・・半田拡がり時間の平均値で示す、
（ｎ＝ｔ Ｏ）
・曲げ加工性・・・曲げ半径０．５Ｒにて９０”曲げし
、曲げ部のクラック発生状況を
実体顕微鏡にて観察し、下記のごと
く定めた。In other words, evaluation criteria: solder spreadability...shown as the average value of solder spread time;
(n=tO) - Bending workability: The material was bent for 90'' at a bending radius of 0.5R, and the occurrence of cracks in the bent portion was observed using a stereomicroscope, and determined as follows.
○・・・クラックの発生は認められない。○: No cracks were observed.
Δ・・・わずかにクラックが発生。Δ...Slight cracks occur.
×・・・素地の露出を伴なった クラックが発生。×...with exposure of the base material A crack occurs.
・半田剥離性
○・・・剥離を認めず
Δ・・・微小部分の剥離が認められる
×・・・顕著な剥離が認められる
第２表において、下層めっきのカラーデンシトメータ値
が０．５〜１．０、上層めっき厚みが０．０５〜０．５
μｍの組み合わせによる本発明の実施例Ｎ０１１乃至Ｎ
００９の試験片では、比較例に比し、同等以上の半田拡
がり性を有すると共に、優れた曲げ加工性および半田耐
熱剥離性を有している。・Solder removability ○...No peeling observed Δ...Peeling of minute parts was observed ×...Significant peeling was observed In Table 2, the color densitometer value of the lower layer plating was 0.5. ~1.0, upper layer plating thickness is 0.05~0.5
Examples N011 to N of the present invention based on combinations of μm
The test piece No. 009 had solder spreadability equal to or better than that of the comparative example, as well as excellent bending workability and solder heat resistance and peelability.
一方、本発明の範囲外の比較例Ｎｏ、１０乃至Ｎｏ、１
４について見ると、Ｎｏ、１０のごとく、下層めつきの
カラーデンシトメーター値のみ。On the other hand, comparative examples No. 10 to No. 1 outside the scope of the present invention
Looking at No. 4, like No. 10, only the color densitometer value of the lower layer plating is shown.
が下限以下の０．３の場合、曲げ加工性および半田耐熱
剥離性は良好であるが、半田拡がり性が悪い、また、Ｎ
ｏ、１１やＮｏ、１２のごとく、カラーデンシトメータ
〒値が上限以上の１．２および１．７の場合には、半田
拡がり性は良好であるが、曲げ加工性および半田耐熱剥
離性が悪い。is 0.3 below the lower limit, bending workability and solder heat peeling resistance are good, but solder spreadability is poor, and N
If the color densitometer value is 1.2 or 1.7, which is above the upper limit, as in No. bad.
また、上層めっき厚みの範囲外の影響については、下限
以下の０．０１μｍでは半田拡がり性が著しく爪下し、
上限以上の１．０μｍでは、曲げ加工性の低下が著しい
。In addition, regarding the influence of the upper layer plating thickness outside the range, at 0.01 μm below the lower limit, the solder spreadability is significantly lower than the nail thickness.
When the thickness is 1.0 μm, which is more than the upper limit, the bending workability is significantly reduced.
なお、Ｎｏ、１５は従来例を示しており、半田拡がり性
は良好であるが、曲げ加工性、半田耐熱剥離性は良くな
い。Note that No. 15 indicates a conventional example, which has good solder spreadability but poor bending workability and solder heat resistance and peelability.
以上の様にすべての特性を満足するためには本発明の方
法に示した、下層めっきのカラーデンシトメーター値０
．５〜１．０、上層めっきの厚み０．０５〜０．５μｍ
の組合わせにて構成されることが必要である。As mentioned above, in order to satisfy all the characteristics, the color densitometer value of the lower layer plating must be 0 as shown in the method of the present invention.
．． 5-1.0, upper layer plating thickness 0.05-0.5 μm
It is necessary to have a combination of the following.
［発明の効果］
以上の通り説明したごとく、本発明は半田接合性を満足
し、かつ、優れた半田耐熱剥離性を有しており半導体装
置の信頼性を向上させたリードフレームを経済的に提供
することができた。[Effects of the Invention] As explained above, the present invention economically provides a lead frame that satisfies solder bondability, has excellent solder heat peeling resistance, and improves the reliability of semiconductor devices. I was able to provide it.
Claims (1)
成されたカラーデンシトメータ値０．５〜１．０の無光
沢Ｎｉめっき層と、当該めっき層上に形成された膜厚０
．０５〜０．５μｍのＮｉ−Ｐめっき層と、により構成
されており、当該Ｎｉ−Ｐめっき層は無電解法により形
成されていることを特徴とする半導体装置用リードフレ
ーム。A Cu or Cu alloy base, a matte Ni plating layer with a color densitometer value of 0.5 to 1.0 formed on the surface of the Cu base, and a film thickness of 0 formed on the plating layer.
．． 1. A lead frame for a semiconductor device, comprising a Ni--P plating layer having a thickness of 0.05 to 0.5 .mu.m, the Ni--P plating layer being formed by an electroless method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP26660187A JPH01109756A (en) | 1987-10-23 | 1987-10-23 | Lead frame for semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP26660187A JPH01109756A (en) | 1987-10-23 | 1987-10-23 | Lead frame for semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01109756A true JPH01109756A (en) | 1989-04-26 |
Family
ID=17433080
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP26660187A Pending JPH01109756A (en) | 1987-10-23 | 1987-10-23 | Lead frame for semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01109756A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05308115A (en) * | 1992-04-28 | 1993-11-19 | Nippondenso Co Ltd | Hybrid integrated circuit |
| EP0762800A2 (en) * | 1995-09-07 | 1997-03-12 | Star Micronics Co., Ltd. | Lead frame for electroacoustic transducer and electroacoustic transducer |
| US20130084760A1 (en) * | 2011-09-30 | 2013-04-04 | Apple Inc. | Connector with multi-layer ni underplated contacts |
| JP2017208461A (en) * | 2016-05-19 | 2017-11-24 | Ｓｈプレシジョン株式会社 | Lead frame and manufacturing method of lead frame |
-
1987
- 1987-10-23 JP JP26660187A patent/JPH01109756A/en active Pending
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05308115A (en) * | 1992-04-28 | 1993-11-19 | Nippondenso Co Ltd | Hybrid integrated circuit |
| DE4313980B4 (en) * | 1992-04-28 | 2005-08-04 | Denso Corp., Kariya | Integrated hybrid circuit and method for its manufacture |
| EP0762800A2 (en) * | 1995-09-07 | 1997-03-12 | Star Micronics Co., Ltd. | Lead frame for electroacoustic transducer and electroacoustic transducer |
| EP0762800A3 (en) * | 1995-09-07 | 1997-04-23 | Star Mfg Co | |
| US20130084760A1 (en) * | 2011-09-30 | 2013-04-04 | Apple Inc. | Connector with multi-layer ni underplated contacts |
| US8637165B2 (en) * | 2011-09-30 | 2014-01-28 | Apple Inc. | Connector with multi-layer Ni underplated contacts |
| JP2017208461A (en) * | 2016-05-19 | 2017-11-24 | Ｓｈプレシジョン株式会社 | Lead frame and manufacturing method of lead frame |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN101689517B (en) | Semiconductor device bonding wire and wire bonding method | |
| US5814168A (en) | Process for producing high-strength, high-electroconductivity copper-base alloys | |
| US6646330B2 (en) | Lead frame for semiconductor device, process for producing the same and semiconductor device using the same | |
| JPH09275182A (en) | Lead frame for semiconductor device | |
| JPH06196349A (en) | Copper lead frame material for tantalum capacitor and manufacture thereof | |
| JPH04329891A (en) | Tin plated copper alloy material and its production | |
| JP2006269903A (en) | Lead frame for semiconductor device | |
| US9421645B2 (en) | Solder joint material and method of manufacturing the same | |
| US4576659A (en) | Process for inhibiting metal migration during heat cycling of multilayer thin metal film structures | |
| JPH01109756A (en) | Lead frame for semiconductor device | |
| US7268021B2 (en) | Lead frame and method of manufacturing the same | |
| EP2099580A1 (en) | Soldering filler metal, assembly method for semiconductor device using same, and semiconductor device | |
| JPH01257356A (en) | Lead frame for semiconductor | |
| JPS6215621B2 (en) | ||
| JPS6215622B2 (en) | ||
| JP3313006B2 (en) | Copper alloy lead frame for bare bond | |
| JP5465874B2 (en) | Copper bonding wire manufacturing method and copper bonding wire using the manufacturing method | |
| JPH08204081A (en) | Lead frame for semiconductor device, semiconductor device, and manufacturing method thereof | |
| JPS6353287A (en) | Ag-coated electric conductor | |
| JPS6036000B2 (en) | Heat-resistant silver coated copper wire and its manufacturing method | |
| JPH05190725A (en) | Lead frame and semiconductor device | |
| JPS6244691B2 (en) | ||
| JPS61198507A (en) | Composite material for electronic component and manufacture | |
| JP2007275917A (en) | Surface treatment film and soldering method using the same | |
| JPS63312935A (en) | Copper alloy material for semiconductor lead frame |