JPH01108650U - - Google Patents
Info
- Publication number
- JPH01108650U JPH01108650U JP400688U JP400688U JPH01108650U JP H01108650 U JPH01108650 U JP H01108650U JP 400688 U JP400688 U JP 400688U JP 400688 U JP400688 U JP 400688U JP H01108650 U JPH01108650 U JP H01108650U
- Authority
- JP
- Japan
- Prior art keywords
- viterbi decoder
- demodulator
- counter
- processor
- pseudo
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Digital Transmission Methods That Use Modulated Carrier Waves (AREA)
Description
第１図はこの考案の一実施例によるＰＳＫ復調
装置を示すブロツク図、第２図は従来のＰＳＫ復
調装置を示すブロツク図である。
図において、１はＡＧＣアンプ、３は復調器、
４はビタビ復号器、５はカウンタ、６はプロセツ
サを示す。なお、図中、同一符号は同一、又は相
当部分を示す。
FIG. 1 is a block diagram showing a PSK demodulator according to an embodiment of this invention, and FIG. 2 is a block diagram showing a conventional PSK demodulator. In the figure, 1 is an AGC amplifier, 3 is a demodulator,
4 is a Viterbi decoder, 5 is a counter, and 6 is a processor. In addition, in the figures, the same reference numerals indicate the same or equivalent parts.
Claims (1)
ビタビ復号器の出力の擬似誤りパルスを入力とす
るカウンタと、カウンタのカウント数によつてＡ
ＧＣアンプ制御電圧を出力するプロセツサとを備
えたことを特徴とするＰＳＫ復調装置。 AGC amplifier, demodulator, Viterbi decoder,
A counter inputs the pseudo-error pulse output from the Viterbi decoder and the number of counts of the counter.
A PSK demodulator comprising: a processor that outputs a GC amplifier control voltage.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP400688U JPH01108650U (en) | 1988-01-14 | 1988-01-14 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP400688U JPH01108650U (en) | 1988-01-14 | 1988-01-14 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01108650U true JPH01108650U (en) | 1989-07-24 |
Family
ID=31206135
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP400688U Pending JPH01108650U (en) | 1988-01-14 | 1988-01-14 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01108650U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05259929A (en) * | 1991-11-13 | 1993-10-08 | Motorola Inc | Radio receiver and method for adaptively controlling its operation parameter |
-
1988
- 1988-01-14 JP JP400688U patent/JPH01108650U/ja active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05259929A (en) * | 1991-11-13 | 1993-10-08 | Motorola Inc | Radio receiver and method for adaptively controlling its operation parameter |