JPH01106451A - Insulating plate for semiconductor device - Google Patents
Insulating plate for semiconductor deviceInfo
- Publication number
- JPH01106451A JPH01106451A JP62262635A JP26263587A JPH01106451A JP H01106451 A JPH01106451 A JP H01106451A JP 62262635 A JP62262635 A JP 62262635A JP 26263587 A JP26263587 A JP 26263587A JP H01106451 A JPH01106451 A JP H01106451A
- Authority
- JP
- Japan
- Prior art keywords
- insulating plate
- metallized surface
- slit
- joint
- heat sink
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 68
- 230000000694 effects Effects 0.000 abstract description 12
- 239000011800 void material Substances 0.000 abstract 1
- 229910000679 solder Inorganic materials 0.000 description 16
- 238000005219 brazing Methods 0.000 description 10
- 229910052751 metal Inorganic materials 0.000 description 9
- 239000002184 metal Substances 0.000 description 9
- 230000008646 thermal stress Effects 0.000 description 7
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 6
- PMHQVHHXPFUNSP-UHFFFAOYSA-M copper(1+);methylsulfanylmethane;bromide Chemical compound Br[Cu].CSC PMHQVHHXPFUNSP-UHFFFAOYSA-M 0.000 description 5
- 238000001465 metallisation Methods 0.000 description 5
- 239000000758 substrate Substances 0.000 description 5
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 4
- 229910052782 aluminium Inorganic materials 0.000 description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 229910052750 molybdenum Inorganic materials 0.000 description 4
- 239000011733 molybdenum Substances 0.000 description 4
- 230000035882 stress Effects 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 3
- 230000017525 heat dissipation Effects 0.000 description 3
- 230000007774 longterm Effects 0.000 description 3
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- 101700004678 SLIT3 Proteins 0.000 description 2
- 102100027339 Slit homolog 3 protein Human genes 0.000 description 2
- 238000010292 electrical insulation Methods 0.000 description 2
- 238000003780 insertion Methods 0.000 description 2
- 230000037431 insertion Effects 0.000 description 2
- 239000011810 insulating material Substances 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 238000005304 joining Methods 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 230000002250 progressing effect Effects 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000020169 heat generation Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
- 230000001902 propagating effect Effects 0.000 description 1
- 230000002195 synergetic effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/2612—Auxiliary members for layer connectors, e.g. spacers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
- H01L2224/49111—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49175—Parallel arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、半導体素子用絶縁板に係り、特に発熱体とな
る半導体素子を積層するのに適したメタライズパターン
を有する絶縁板に関するものである。[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to an insulating plate for semiconductor elements, and particularly to an insulating plate having a metallized pattern suitable for stacking semiconductor elements that serve as heating elements. .
一般に半導体素子用絶縁板は、半導体素子をヒートシン
ク（金属ベース）等に取付ける場合の電気的絶縁のため
に用いられるもので、ヒートシンク上にはんだ、銀ろう
等のろう付により接合されている。このような絶縁板は
、電気的な絶縁を行なう他に、特に発熱性の半導体素子
を搭載する場合には、半導体素子のそのものに発生した
熱をヒートシンク側に放熱させる役割をも兼ねるもので
。Generally, an insulating plate for semiconductor devices is used for electrical insulation when a semiconductor device is attached to a heat sink (metal base), etc., and is bonded to the heat sink by brazing with solder, silver solder, or the like. In addition to providing electrical insulation, such an insulating plate also serves to dissipate the heat generated in the semiconductor element itself to the heat sink, especially when a heat-generating semiconductor element is mounted.
絶縁板としては、例えばアルミナ等の絶縁部材が用いら
れる。As the insulating plate, an insulating member such as alumina is used, for example.
ところで、この種の絶縁板に半導体素子を搭載したり、
絶縁板自身をヒートシンク上に取付ける場合には、はん
だ等のろう付を用いて行なわれるが、絶縁板となるアル
ミナ等は、ろう付けに適さないため、絶縁板の表裏面に
半導体素子と接合するためのメタライズ面や、ヒートシ
ンクと接合するためのメタライズ面を設けている。メタ
ライズ面は、モリブデン、タングステン膜等が用いられ
る。By the way, it is possible to mount semiconductor elements on this type of insulating board,
When attaching the insulating plate itself to the heat sink, it is done using brazing such as solder, but since the insulating plate is made of alumina, etc., which is not suitable for brazing, semiconductor elements are bonded to the front and back sides of the insulating plate. There is a metallized surface for bonding to the heat sink and a metallized surface for bonding to the heat sink. A molybdenum, tungsten film, or the like is used for the metallized surface.
更に従来のこの種の絶縁板では、例えば特開昭’５５−
１１８６４１号公報等に開示されるように、絶縁板に施
されたメタライズ面に複数のスリットを設けて、はんだ
等のろう付は時に発生するボイドをスリットから逃して
ボイドの 低減を−図ったり、或いは、はんだ等の接合
部に生じるクラック発生率は、接合される部材の線膨張
係数差の大きさに左右される他に、接合部の長さが長い
程、部材間の歪が大きくなってクラックが生じ易いので
１例えば特開昭５５−１６５６５６号公報等に開示され
るように、絶縁板の裏面メタライズ面を表面側に搭載さ
れる半導体素子の直下に配置して、絶縁板とヒートシン
クとの接合部（ろう何部）を半導体素子直下に°集中さ
せ、このようにしてメタライズ面ひいては接合部の長さ
をできるだけ短かくして、接合部のクラックの発生を減
少させたり、また、この半導体素子直下のメタライズの
面の他に半導体素子チップ取付は面の水平を保つため、
第２のメタライズ面を設ける等種々の配慮がなされてい
る。Furthermore, in the conventional insulating board of this kind, for example,
As disclosed in Publication No. 118641, etc., a plurality of slits are provided in the metallized surface of an insulating plate, and voids that sometimes occur during brazing with solder are released from the slits to reduce voids. Alternatively, the incidence of cracks that occur at joints such as solder depends on the difference in the linear expansion coefficients of the members being joined, and the longer the length of the joint, the greater the strain between the members. Since cracks are likely to occur, 1. For example, as disclosed in Japanese Unexamined Patent Publication No. 55-165656, the back metallized surface of the insulating plate is placed directly under the semiconductor element mounted on the front side, and the insulating plate and heat sink are connected. By concentrating the joints (brazing parts) directly under the semiconductor element, the metallized surface and therefore the length of the joints can be made as short as possible to reduce the occurrence of cracks at the joints, and the semiconductor element In addition to the metallized surface directly below, the semiconductor element chip must be mounted in order to keep the surface level.
Various considerations have been made, such as providing a second metallized surface.
前述した如く、従来よりこの種絶縁板には、メタライズ
面にスリットを形成したり、メタライズ面の配置位置を
特定しつつ接合部の長さをできるだけ短かくする等、メ
タライズパターンに種々の配慮を施して、熱伝導低下原
因たるボイド発生を防止したり、クラックの減少化を図
っている。As previously mentioned, various considerations have been made to the metallized pattern of this type of insulating board, such as forming slits on the metallized surface and minimizing the length of the joint while specifying the placement position of the metallized surface. This prevents the occurrence of voids, which are the cause of reduced heat conduction, and reduces the occurrence of cracks.
しかしながら、上記従来技術の中で、メタライズ面にス
リットを形成する従来例では、ボイド低減を図る点に重
点が置かれ、絶縁板とヒートシンク間の接合部のクラッ
ク低減を図る点については充分な配慮がなされていなか
った。すなわち、従来のスリット方式は、メタライズ面
２１に施されるはんだ等の接合８Ｐに発生するボイドや
熱を第４図の従来例に示すように、絶縁板１のメタライ
ズ面２１に設けた十文字のスリット部２２を介して外部
に逃している。しかし、熱応力の長期繰返し印加により
生じるクラックは、図の矢印に示すように絶縁板の四隅
及び絶縁板の端面より中心方向に進行する性質を有して
いるため、十文字スリットで区分されるはんだ等の接合
部がすべてクラックで侵される傾向があった。特に、−
度クラックが発生すると、クラックが切欠きどなって切
欠部に応力集中が発生する切欠き効果が働き、クラック
の進行を助長する。なお、第４図の斜線２３で示す部分
は、クラックが末だ進行してない部分をクラック進行状
況として表わしたもので、同図では、絶縁板１のＡ側よ
りもＢ側の方がクラックの進行が著るしいが、このよう
になるのは、接合部の厚みがＡ側よりＢ側の方が薄いと
いった場合に起こる。すなわち、接合部が薄いほど熱応
力が増大する傾向にあるためである。However, among the above-mentioned conventional technologies, in the conventional example in which slits are formed on the metallized surface, emphasis is placed on reducing voids, and sufficient consideration is given to reducing cracks at the joint between the insulating plate and the heat sink. had not been done. That is, in the conventional slit method, as shown in the conventional example in FIG. It escapes to the outside via the slit portion 22. However, cracks caused by long-term repeated application of thermal stress have the property of propagating from the four corners of the insulating board and the end face of the insulating board toward the center, as shown by the arrows in the figure. There was a tendency for all the joints to be attacked by cracks. In particular, −
When a crack occurs, the crack becomes a notch, creating a notch effect in which stress is concentrated in the notch, which promotes the progression of the crack. Note that the area indicated by diagonal lines 23 in FIG. 4 shows the progress of the crack in the area where the crack has not yet progressed. This progress is remarkable, but this happens when the thickness of the joint is thinner on the B side than on the A side. That is, this is because the thinner the joint, the more thermal stress tends to increase.
このような接合部の厚みの不均衡は、特に絶縁板上の半
導体素子の搭載される箇所とそれ以外の箇所の重量の不
均衡に起因して生じる。Such an imbalance in the thickness of the joint portion is caused particularly by an imbalance in weight between the portion on the insulating plate where the semiconductor element is mounted and the portion other than the portion on the insulating plate.
また、上記従来技術の中で、絶縁板の裏面メタライズを
半導体素子搭載箇所の直下に形成する方式のものは、ク
ラックの発生を減少できる反面、絶縁板とヒートシンク
間に空間が存在するため、その分、絶縁板からヒートシ
ンク側への熱伝導が低下して、半導体素子のチップ温度
が上昇子る傾向があった。特に電流制限付イグナイタの
場合には、電流制限時に発熱が増大、するため、初期的
にも熱応力が増大し、長期的な信頼性の面で改善すべき
点があった。In addition, among the above-mentioned conventional technologies, the method in which metallization is formed on the back side of the insulating plate directly under the semiconductor element mounting area can reduce the occurrence of cracks, but on the other hand, there is a space between the insulating plate and the heat sink. However, the heat conduction from the insulating plate to the heat sink side decreased, and the chip temperature of the semiconductor element tended to rise. In particular, in the case of an igniter with a current limit, heat generation increases when the current is limited, so thermal stress increases even in the initial stage, and there is a need for improvement in terms of long-term reliability.
本発明は以上の点に鑑みてなされたものであり、その目
的とするところは、ヒートシンクとの接合箇所における
ボイド、クラック等の発生を有効に抑制し、しかも放熱
面積を充分に確保して、半導体素子、絶縁板、ヒートシ
ンク等で構成される半導体組立体の耐久性、信頼性の向
上化を図り得る半導体素子用絶縁板を提供することにあ
る。The present invention has been made in view of the above points, and its purpose is to effectively suppress the occurrence of voids, cracks, etc. at the joint with the heat sink, and to secure a sufficient heat dissipation area. An object of the present invention is to provide an insulating plate for a semiconductor element that can improve the durability and reliability of a semiconductor assembly composed of a semiconductor element, an insulating plate, a heat sink, and the like.
上記目的は、絶縁板の裏面メタライズの中で、第１のメ
タライズ面を絶縁板表面側の半導体素子搭載箇所の直下
部に形成し、且つ第２のメタライズ面を第１のメタライ
ズ面の周囲にスリット部を介して配設し、前記スリット
部の少なくとも一部を絶縁板の端面にまで延設すること
で達成される。The above purpose is to form the first metallized surface directly below the semiconductor element mounting area on the front side of the insulating plate in the metallization on the back side of the insulating plate, and to form the second metallized surface around the first metallized surface. This is achieved by providing the insulation plate through a slit and extending at least a portion of the slit to the end surface of the insulating plate.
既に「発明が解決しようとする問題点」でも述べたよう
に、絶縁板とヒートシンク間の接合部のクラックは、絶
縁板の端面及び四隅から中央に向かって進行し、且つ絶
縁材が傾きをもって接合された場合には、接合部の厚み
の薄い方がクラックの進行度合が大きい。しかも、クラ
ック部には。As already mentioned in "Problems to be Solved by the Invention," cracks at the joint between the insulating board and the heat sink progress from the ends and four corners of the insulating board toward the center, and the insulating material is joined at an angle. In this case, the thinner the joint, the more likely the crack will progress. Moreover, in the crack part.
クラック自身の切欠効果が働き、応力集中を生じるため
、更にクラックは進行する性質を有する。Since the notch effect of the crack itself acts and causes stress concentration, the crack has the property of further progressing.
ところで１本発明の如き絶縁板色ヒートシンク上に積層
する場合には、絶縁板裏面の第１．第２メタライズ面と
ヒートシンクの間がはんだ等のろう材が接合されるが、
第１のメタライズ面の周りには、メタライズの施されな
いスリットがあるため、この部分は、ろう材が存在しな
い非接合箇所となる。すなわち、絶縁板の第１のメタラ
イズ面とヒートシンク間の接合部（これを第１の接合部
と称する）と、第１の接合部の周りに配される第２のメ
タライズ面とヒートシンク間の接合部（これを第２の接
合部と称する）との間には、スリット状の非接合部が存
在することになる。By the way, when laminating an insulating plate on a colored heat sink as in the present invention, the first . A brazing material such as solder is bonded between the second metallized surface and the heat sink,
Since there is a slit in which no metallization is applied around the first metallized surface, this portion becomes a non-bonded portion where no brazing material is present. That is, the joint between the first metallized surface of the insulating plate and the heat sink (this is referred to as the first joint), and the joint between the second metallized surface arranged around the first joint and the heat sink. (This will be referred to as the second joint part) there will be a slit-shaped non-joint part.
しかして、このような接合構造によれば、第１の接合部
の周囲、すなわち第２の接合部に絶縁板の四隅及び端面
からクラックが生じたとしても、そのクラックがスリッ
ト状の非接合部に至ることにより、切欠効果が消失し応
力集中がなくなるため、クラックの進行を止め、第２の
接合部側にクラックが及ぶことを有効は防止することが
できる。According to such a joint structure, even if cracks occur from the four corners and end surfaces of the insulating plate around the first joint, that is, the second joint, the cracks will spread to the slit-shaped non-joint parts. By reaching this point, the notch effect disappears and stress concentration disappears, so it is possible to stop the progress of the crack and effectively prevent the crack from extending to the second joint portion side.
更に第１の接合部は、スリットを介して第２の接合部と
区分けされ、第１の接合部の長さをできるだけ短かくす
ることができるので、ヒートシンクと絶縁板の接合部間
の熱ひずみを極力小さくできること、及び接合部の厚み
に傾きがあって厚さの不均衡が生じても、半導体搭載箇
所の直下の接合部は、傾きの始点（絶縁板一端の接合箇
所で接合部の厚さが最も薄いところ）から外れた位置に
あるので、その厚みも充分に確保され、熱応力も低減さ
れるので、第１接合部自身がクラックの生じにくい状態
にある。従って１本発明によれば、第２の接合部にクラ
ックが生じたとしても、第１の接合部は、前記スリット
によるクラック進行防止効果と第１接合部自身がクラッ
クの生じにくい構造特性をもたせたことから、接合箇所
の必要範囲での健全性を充分に保持できる。Furthermore, the first joint is separated from the second joint through a slit, and the length of the first joint can be made as short as possible, thereby reducing thermal strain between the joint between the heat sink and the insulating plate. Even if there is a slope in the thickness of the joint and an imbalance in thickness occurs, the joint immediately below the semiconductor mounting area can be Since the first joint part is located away from the thinnest part (the thinnest part), a sufficient thickness is ensured, and thermal stress is reduced, so that the first joint part itself is in a state where it is difficult for cracks to occur. Therefore, according to the present invention, even if a crack occurs in the second joint, the first joint has the effect of preventing crack progression due to the slit and the first joint has structural characteristics that make it difficult for cracks to occur. Therefore, the integrity of the joint can be maintained within the necessary range.
更に、第１のメタライズ面の他に、この周りに配される
第２のメタライズ面もヒートシンクとろう材により接合
するので、熱伝導性が向上し半導体の温度上昇を低減で
きる。このため、各接合部に印加される熱応力を減少で
き、初期的なりラックが入るまでの時間も長くできる。Furthermore, in addition to the first metallized surface, the second metallized surface disposed around the first metallized surface is also bonded to the heat sink by the brazing material, so that thermal conductivity is improved and the temperature rise of the semiconductor can be reduced. Therefore, the thermal stress applied to each joint can be reduced, and the time required for initial rack insertion can be lengthened.
更に、本発明においても、従来同様にヒートシンクと絶
縁板の接合部をスリットにより分断できるので、スリッ
トによるボンド低減を行ない得る。Furthermore, in the present invention as well, the bond between the heat sink and the insulating plate can be separated by a slit, as in the conventional case, so that the bond can be reduced by the slit.
本発明の実施例を図面に基づき説明する。 Embodiments of the present invention will be described based on the drawings.
第１図は本発明の第１実施例たる半導体素子用絶縁板の
裏面図である。FIG. 1 is a back view of an insulating plate for semiconductor devices according to a first embodiment of the present invention.
図中、１は絶縁板で１例えばアルミナ、窒化アルミニウ
ム等で形成され、絶縁板１の裏面に以下に述べる第１の
メタライズ面２、スリット部３゜３′、第２のメタライ
ズ面４が配設される。In the figure, 1 is an insulating plate 1 made of, for example, alumina, aluminum nitride, etc. On the back side of the insulating plate 1, a first metallized surface 2, a slit portion 3°3', and a second metallized surface 4, which will be described below, are arranged. will be established.
第１．第２のメタライズ面２，４は１例えば、絶縁材１
の裏面に施されるモリブデン膜或いはタングステン膜等
で構成され、更に、通常は、モリブデン膜等が酸化し易
いので、これらの膜上に更にニッケル等の金属メツキを
施してなる。これらのメタライズ面の中で、第１のメタ
ライズ面２は、絶縁板における半導体素子搭載位置の直
下に形成される。また、第１のメタライズ面２の周囲に
メタライズを施さないスリット部３が確保され、このス
リット部３を介して第１のメタライズ面２の周囲に第２
のメタライズ面４が配設されるパターン構成となってい
る。第２のメタライズ面４は、複数のスリット部３′に
より複数のメタライズパターンに区分されている。本実
施例の各スリット部３′はスリット部３を夫々絶縁板１
の各端面に至るまで直線的に延長したものである。1st. The second metallized surfaces 2, 4 are 1, for example, an insulating material 1
It is composed of a molybdenum film, a tungsten film, etc. applied to the back surface of the substrate, and since the molybdenum film etc. are usually easily oxidized, these films are further plated with a metal such as nickel. Among these metallized surfaces, the first metallized surface 2 is formed directly below the semiconductor element mounting position on the insulating plate. Further, a slit portion 3 which is not metalized is secured around the first metallized surface 2, and a second metallized surface is formed around the first metallized surface 2 through this slit portion 3.
It has a pattern configuration in which metallized surfaces 4 are arranged. The second metallized surface 4 is divided into a plurality of metallized patterns by a plurality of slits 3'. In this embodiment, each slit portion 3' is formed by connecting the slit portion 3 to the insulating plate 1.
It extends linearly to each end face.
スリット部３，３′は、その幅ｄが３ｍ以上確保されて
いる。これは、スリット幅を３ＩＩＩ１１以下にすると
、後述するヒートシンク７Ｌ絶縁板１の各メタライズ面
２，４をはんだ等で接合した場合に、各接合部のフィレ
ット部がスリットを超えて接合してしまい、スリットの
存在意義がなくなるためである。なお、絶縁板１の表面
にも、半導体素子或いは別のヒートシンク板を接合する
ためのメタライズ面（図示せず）が形成されている。The slit portions 3, 3' have a width d of 3 m or more. This is because if the slit width is set to 3III11 or less, when the metallized surfaces 2 and 4 of the heat sink 7L insulating plate 1, which will be described later, are joined with solder or the like, the fillet part of each joint will be joined beyond the slit. This is because the slit loses its significance. Note that a metallized surface (not shown) for bonding a semiconductor element or another heat sink plate is also formed on the surface of the insulating plate 1.
このような絶縁板１を用いた半導体組立体の積層構造例
を第２図（ａ） 、 （ｂ）に示す。An example of a laminated structure of a semiconductor assembly using such an insulating plate 1 is shown in FIGS. 2(a) and 2(b).
第２図（ａ）は第１の積層構造例で、図中、５は半導体
素子（パワートランジスタ等）、６は第１のヒートシン
ク（例えばモリブデン板）、７はニッケルメッキを施し
た銅又はアルミニウムよりなる第２のヒートシンク（金
属ベース）であり、上から順に、半導体素子５．第１の
ヒートシンク６゜絶縁板１．第２のヒートシンク７が積
層され、且つこれらの部品間は符号８，９．１０で示す
はんだにて接合されている。なお、本実施例では、絶縁
板１は、アルミナよりな°）、絶縁板１上には、ヒート
シンク６を介して半導体素子５を塔載する。FIG. 2(a) shows an example of the first laminated structure, in which 5 is a semiconductor element (power transistor, etc.), 6 is a first heat sink (for example, a molybdenum plate), and 7 is nickel-plated copper or aluminum. A second heat sink (metal base) consisting of semiconductor elements 5. First heat sink 6° insulation plate 1. The second heat sink 7 is stacked, and these parts are joined by solder indicated by reference numerals 8, 9, and 10. In this embodiment, the insulating plate 1 is made of alumina), and the semiconductor element 5 is mounted on the insulating plate 1 via a heat sink 6.
絶縁板１の裏面における第１．第２のメタライズ面２，
４は、はんだ１０にて第２のヒートシンク７に接合され
る。１１はワイヤボンディング用の部材であり、はんだ
１２により絶縁板１に接続される。1st on the back surface of the insulating plate 1. second metallized surface 2,
4 is joined to the second heat sink 7 with solder 10. Reference numeral 11 denotes a wire bonding member, which is connected to the insulating plate 1 with solder 12.
第２図（ｂ）は第２の積層構造例に示すもので、本例で
は、絶縁板１を窒化アルミニウム基板としたときの積層
構造を示し、図中、第２図（ａ）と同一符号は同一部品
を示すものであり、特に本例では、絶縁板１が高熱伝導
性を有する窒化アルミニウムで構成するので、半導体素
子５をはんだ９を介して直接絶縁板１上に搭載したもの
である。FIG. 2(b) shows a second example of a laminated structure. In this example, the laminated structure is shown when the insulating plate 1 is an aluminum nitride substrate, and in the figure, the same reference numerals as in FIG. 2(a) are shown. indicate the same parts; in particular, in this example, since the insulating plate 1 is made of aluminum nitride having high thermal conductivity, the semiconductor element 5 is directly mounted on the insulating plate 1 via the solder 9. .
しかして、第２図（ａ） 、 （ｂ）に示すように、絶
縁１の第１．第２のメタライズ面２，４とヒートシンク
７をはんだ１０を介して接合した場合には。As shown in FIGS. 2(a) and 2(b), the first . In the case where the second metallized surfaces 2 and 4 and the heat sink 7 are joined via the solder 10.
スリット部３に対応する部分にスリット状の非接合部１
５が形成される。A slit-shaped non-joint part 1 in the part corresponding to the slit part 3
5 is formed.
第３図は、第２図（ａ）の積層構造を全体的にみた半導
体組立体の平面図で、同図に示すように第２のヒートシ
ンク７上には、半導体５．第１のヒートシンク ６等が
配設される他に印刷基板１３が接合され、半導体素子５
と印刷基板１３上のワイヤボンディング部材１１とがワ
イヤ１４により接続され、電気的導通がとられている。FIG. 3 is a plan view of the semiconductor assembly, showing the entire stacked structure of FIG. 2(a). As shown in the figure, a semiconductor 5. In addition to the first heat sink 6 and the like, a printed circuit board 13 is bonded to the semiconductor element 5.
and the wire bonding member 11 on the printed circuit board 13 are connected by a wire 14 to establish electrical continuity.
次に本実施例の作用を説明する。Next, the operation of this embodiment will be explained.
一般にヒートシンクと絶縁板間の接合部を生じるクラッ
クは、線膨張係数差の大きい被接合部材間で発生しやす
く、且つ接合部の長さが長くなる程、接合部における被
接合部間の熱膨張差（熱歪）が大きいので生じやすい。In general, cracks that occur at the joint between a heat sink and an insulating plate are more likely to occur between joined parts with a large difference in coefficient of linear expansion, and the longer the length of the joint, the greater the thermal expansion between the joined parts at the joint. This is likely to occur because the difference (thermal strain) is large.
第２図（ａ）を例にとれば各部材の線膨張係数は絶縁板
１がアルミナ基板であり６．８ Ｘ １０’″Ｂ、はん
だ１０は２８×１０″″Ｂ、金属ベース７は銅で１７Ｘ
１０″″Ｂ、アルミニウムの場合で２４ＸＩＯ−０であ
る。すなわち、最もはんだ付は面積の大きく、線膨張係
数差の大きい絶縁板１と第２のヒートシンク（金属ベー
ス）７間のはんだ接合部１ｏにクラックが発生しゃすい
。Taking Figure 2 (a) as an example, the linear expansion coefficient of each member is 6.8 x 10''B for the insulating plate 1 which is an alumina substrate, 28 x 10''B for the solder 10, and 28 x 10''B for the metal base 7. So 17X
10″″B, 24XIO-0 for aluminum. That is, cracks are most likely to occur in the soldered joint 1o between the insulating plate 1 and the second heat sink (metal base) 7, which has a large surface area and a large difference in coefficient of linear expansion.
また第２図（ｂ）の場合は、絶縁板１は窒化アルミニウ
ムで線膨張係数は４．３ Ｘ １０″″Ｂであり、第２
図（ａ）と同様にクラックははんだ１ｏで発生しやすい
。クラックの発生及び進行は、熱伝達率を低下させ、ひ
いては装置の信頼性を低下させる。In the case of Fig. 2(b), the insulating plate 1 is made of aluminum nitride and has a coefficient of linear expansion of 4.3 x 10''B.
Similar to Figure (a), cracks are likely to occur in the solder 1o. The occurrence and progression of cracks reduce the heat transfer coefficient and, in turn, reduce the reliability of the device.
これらのクラックの進行は、〔発明が解決しようとする
問題点〕の項でも既述したように、その性質上、絶縁基
板１の四隅及び端面から進行するもので、且つ接合部１
０に傾きがある場合には、接合部の薄い方に生じ易い。As already mentioned in the [Problems to be Solved by the Invention] section, these cracks propagate from the four corners and end faces of the insulating substrate 1 due to their nature, and from the joints 1
If there is a slope at 0, it tends to occur on the thinner side of the joint.
第２図（ａ） 、 （ｂ）では、絶縁板１及び接合部１
０に傾きが生じた場合、第１のヒートシンク６及び半導
体素子５の自重により、接合部１ｏのＡ側の厚みが薄く
なる傾向にある。そして、一端クラックが発生すると、
クラック自身応カ朶中を発生させる切欠効果が働き、ク
ラックの進行を助長することになる。In FIGS. 2(a) and 2(b), the insulating plate 1 and the joint 1
If there is a slope at 0, the thickness of the joint portion 1o on the A side tends to become thinner due to the weight of the first heat sink 6 and the semiconductor element 5. And once a crack occurs,
The crack itself has a notch effect that generates stress, which promotes the progress of the crack.
しかして、本実施例の場合の絶縁板１とヒートシンク７
間の接合部１ｏでは、長期的な熱疲労サイクルが加わる
と、絶縁板１の一端及び四隅にある第２の接合部（第２
のメタライズ面４に対応するもの）１０ｂからクラック
が生じることになるが、本実施例では、スリット状の非
接合部３ａにクラックが至ると、クラックの切欠効果が
消失してクラックの進行が止まる。更に第１の接合部１
０ａは、スリット状の非接合部１５を介して第２の接合
部１０ｂと区分けされ、第１の接合部１０ａの長さをで
きるだけ短かくすることができるので、ヒートシンク７
と絶縁板１の接合部１０ａ間の熱ひずみを極力小さくで
きると、及び接合部１０全体の厚みに傾きがあって厚さ
の不均衡が生じても、半導体搭載箇所の直下の接合部１
０ａは。Therefore, the insulating plate 1 and the heat sink 7 in this embodiment
When a long-term thermal fatigue cycle is applied to the joints 1o between the
(corresponding to the metallized surface 4) 10b, but in this example, when the crack reaches the slit-shaped non-bonded part 3a, the notch effect of the crack disappears and the crack stops progressing. . Furthermore, the first joint 1
0a is separated from the second joint part 10b via a slit-shaped non-joint part 15, and the length of the first joint part 10a can be made as short as possible, so that the heat sink 7
If the thermal strain between the bonding portion 10a of the insulating plate 1 and the bonding portion 10a can be minimized, and even if the overall thickness of the bonding portion 10 is inclined and an imbalance in thickness occurs, the bonding portion 1 directly below the semiconductor mounting location can be
0a is.
傾きの始点（絶縁板１一端の接合箇所１０ｂで接合部の
厚さが最も薄いところ）から外れた位置にあるので、そ
の厚みも充分に確保され、熱応力も低減されるので、第
１接合部１０ａ自身がクラックの生じにくい状態にある
。従って、本実施例によれば、第２の接合部１０ｂにク
ラックが生じたとしても、第１の接合部１０ａは、前記
スリット状非接合部１５によりクラック進行防止効果と
第１ユク部自身がクラックの生じにくい構造特性をもた
せたことから、両者の相乗効果で接合箇所の必要範囲で
の健全性を充分に保持できる。Since it is located away from the starting point of the inclination (the point where the thickness of the joint is the thinnest at the joint 10b at one end of the insulating plate 1), sufficient thickness is ensured and thermal stress is reduced, so the first joint The portion 10a itself is in a state where it is difficult for cracks to occur. Therefore, according to this embodiment, even if a crack occurs in the second joint part 10b, the first joint part 10a has the effect of preventing crack progression due to the slit-like non-joint part 15 and the first joint part itself. Since it has a structural characteristic that makes it difficult for cracks to occur, the synergistic effect of both can sufficiently maintain the soundness of the joint within the necessary range.
更に、第１のメタライズ面２の他に、この周りに配され
る第２のメタライズ面４もヒートシンクとろう材により
接合するので、熱伝導性が向上し半導体の温度上昇を低
減できる。このため、各接合部に印加される熱応力を減
少でき、初期的なりラックが入るまでの時間も長くでき
る。Furthermore, in addition to the first metallized surface 2, the second metallized surface 4 disposed around the first metallized surface 2 is also bonded to the heat sink using a brazing material, so that thermal conductivity is improved and the temperature rise of the semiconductor can be reduced. Therefore, the thermal stress applied to each joint can be reduced, and the time required for initial rack insertion can be lengthened.
更に、ヒートシンク７と絶縁板１の接合部１０をスリッ
ト３により分断できるので、スリットに 、よるボン
ド低減を行ない得る。Furthermore, since the joint 10 between the heat sink 7 and the insulating plate 1 can be separated by the slit 3, the bond can be reduced by the slit.
第５図（ａ） 、（ｂ）は、本発明の第２．第３実施例
を示す絶縁板１の裏面図である。FIGS. 5(a) and 5(b) show the second embodiment of the present invention. It is a back view of the insulating board 1 which shows 3rd Example.
第５図（ａ）における符号２で示す部分が第１実施例と
同様に半導体素子直下の第１のメタライズ面であり、そ
の周囲にスリット３を介して配される第２のメタライズ
面４を複数のスリット３′を介して更に細分化した例で
あり、また、第５図（ｂ） ｔｚスリット３′の入れ方
を変更した例である。The part indicated by the reference numeral 2 in FIG. 5(a) is the first metallized surface directly under the semiconductor element, as in the first embodiment, and the second metallized surface 4 arranged around it through the slit 3 is the first metallized surface directly below the semiconductor element. This is an example of further subdivision through a plurality of slits 3', and FIG. 5(b) is an example of changing the way the tz slits 3' are inserted.
これＳの実施例によるメタライズパターンでも第１実施
例と同様の効果を奏し得る。The metallization pattern according to the embodiment S can also produce the same effects as the first embodiment.
第６図（ａ）は本発明の第４実施例を示す絶縁板の表面
図、同図（ｂ）はその裏面図を示すものである。本実施
例は、半導体素子を複数搭載するための絶縁板の具体例
を示したもので、斜線部はメタライズ面である。第６図
（、）のメタライズ面２’ａ〜２’ｃには、各半導体素
子５が接合を介して搭載され、また、各メタライズ面２
’ａ〜２’ｃは互いの耐圧性を保持するため所定の間隔
で分離配置されている。第６図（ｂ）は裏面のメタライ
ズパターンを示し、２ａ〜２ｃが各半導体素子搭載箇所
の２’ａ〜２’ｃの直下に配置される第１のメタライズ
面で、この第１のメタライズ面２ａ〜２Ｃの夫々の周囲
に第２のメタライズ面４がスリット部３を介して配設さ
れている。また、第２のメタライズ面４はスリット部３
に通じるスリット部３′により複数に細分化されている
。FIG. 6(a) is a front view of an insulating plate showing a fourth embodiment of the present invention, and FIG. 6(b) is a back view thereof. This example shows a specific example of an insulating plate for mounting a plurality of semiconductor elements, and the shaded area is the metallized surface. Each semiconductor element 5 is mounted on the metallized surfaces 2'a to 2'c in FIG.
'a to 2'c are separated at predetermined intervals in order to maintain mutual pressure resistance. FIG. 6(b) shows the metallized pattern on the back side, and 2a to 2c are the first metallized surfaces arranged directly under 2'a to 2'c of the respective semiconductor element mounting locations. A second metallized surface 4 is provided around each of 2a to 2C via a slit portion 3. Further, the second metallized surface 4 is connected to the slit portion 3
It is subdivided into a plurality of parts by a slit part 3' leading to the slit part 3'.
第６図（Ｃ）は絶縁板１の裏面メタライズパターンの変
形例（第５実施例）を示すものである。FIG. 6(C) shows a modification (fifth embodiment) of the metallization pattern on the back surface of the insulating plate 1.
第７図（ａ） 、 （ｂ）は、第４実施例の絶縁板１を
用いた半導体組立体の積層構造例を示すものであり、既
述した第２図（ａ） 、 （ｂ）の積層構造例と同一符
号は、同−或いは共通する要素を示すものである。第７
図（ａ）では、複数の半導体素子５、絶縁板（アルミナ
基板）１、ヒートシンク７、金属ベース７′をはんだ９
．１０．１０’ を介して順次接合したもので、特にヒ
ートシンク７と金属ベース７′とを別個にし、且つ絶縁
板１と接合すべきヒートシンク７を半導体素子５の数に
応じて分割してなる。そして、絶縁板１とヒートシンク
７の接合部１ｏは、第１のメタライズ面２ａ。FIGS. 7(a) and (b) show an example of a laminated structure of a semiconductor assembly using the insulating plate 1 of the fourth embodiment, and are similar to those in FIGS. 2(a) and (b) already described. The same reference numerals as in the laminated structure example indicate the same or common elements. 7th
In figure (a), a plurality of semiconductor elements 5, an insulating plate (alumina substrate) 1, a heat sink 7, and a metal base 7' are connected to a solder 9.
．． In particular, the heat sink 7 and the metal base 7' are made separate, and the heat sink 7 to be bonded to the insulating plate 1 is divided according to the number of semiconductor elements 5. The joint portion 1o between the insulating plate 1 and the heat sink 7 is a first metallized surface 2a.
２ｂ、２ｃの夫々とヒートシンク７とが接合される第１
の接合部１０ａと、第２のメタライズ面４とヒートシン
ク７とが接合される第２の接合部１０ｂとで構成され、
第１の接合部１０ａと第２の接合部１０ｂとの間にスリ
ット状の非接合部１５が確保される。2b, 2c and the heat sink 7 are connected to each other.
and a second joint part 10b where the second metallized surface 4 and the heat sink 7 are joined,
A slit-shaped non-joint part 15 is secured between the first joint part 10a and the second joint part 10b.
第７図（’ｂ ’）は、第７図（ａ）と異なりヒートシ
ンク７を分割せずに１個のヒートシンク７としたもので
、また、ヒートシンク７を金属ベースと兼用させ、絶縁
板１を窒化アルミニウムで構成したものである。In Fig. 7('b'), unlike Fig. 7(a), the heat sink 7 is not divided into one heat sink 7, and the heat sink 7 is also used as a metal base, and the insulating plate 1 is It is made of aluminum nitride.
第８図は、第７図（ａ）の積層構造を全体的にみた半導
体組立体の平面図で、金属ベース７′に接着された印刷
基板１３上のワイヤボンディング部材１１とアルミワイ
ヤ１４とにより、各々の半導体素子５が印刷基板１３と
電気的に接続されている。また、絶縁板１上のワイヤボ
ンディング部材１１は、図示しない外部端子とアルミワ
イヤで超音波接続される。なお、第７図（ａ）のヒート
シンク７とアルミベース７′は、はんだ等のろう付を用
いることなく、超音波溶接も可能であり、このような接
合によれば、接合の信頼性を大幅に向上させることがで
きる６
しかして、本実施例においても、絶縁板１とヒートシン
ク（或いは金属ベース）゛７間接合部１０にクラックが
生じ易いが、既述した他の実施例同様に、スリット３に
対応する非接合部１５のクラック進行防止効果、及び第
１メタライズ面２ａ。FIG. 8 is a plan view of a semiconductor assembly that shows the entire laminated structure of FIG. 7(a). , each semiconductor element 5 is electrically connected to a printed circuit board 13. Further, the wire bonding member 11 on the insulating plate 1 is ultrasonically connected to an external terminal (not shown) using an aluminum wire. Note that the heat sink 7 and aluminum base 7' in Fig. 7(a) can be ultrasonically welded without using solder or other brazing, and this type of joining greatly improves the reliability of the joint. However, in this embodiment as well, cracks are likely to occur in the joint 10 between the insulating plate 1 and the heat sink (or metal base) 7, but as in the other embodiments described above, the slit The crack progression prevention effect of the non-bonded portion 15 and the first metallized surface 2a corresponding to No. 3.
２ｂ、２ｃに対応する第１接合部１０ａの接合長をでき
るだけ短くし且つ接合部１０ａの厚みは。The joining length of the first joining part 10a corresponding to 2b and 2c is made as short as possible, and the thickness of the joining part 10a is set as follows.
充分に確保できる構造特性から、第１接合部１０山自身
でのクラック発生を有効に防乏し、且つスリット３，３
′を介して接合部のボイド発生を低減できるので、第１
メタライズ面２ａ、２ｂ。Due to the structural characteristics that can be ensured sufficiently, cracks can be effectively prevented from occurring in the first joint 10 itself, and the slits 3, 3
’ can reduce the occurrence of voids at the joint, so the first
Metallized surfaces 2a, 2b.
２ｃでの接合部１０ａにて必要最小限の放熱面積を確保
できる。The minimum required heat dissipation area can be ensured at the joint 10a at 2c.
従って、接合部の信頼性の向上を図り、且つ半導体組立
体の耐久性、信頼性を向上させることができ、また１本
実施例では、−枚の絶縁板に複数の半導体素子を実装で
き、半導体素子ごとに個別に絶縁板を用意して接合する
ことがないので、半導体組立体の製造工程の簡略化を図
り得る。Therefore, it is possible to improve the reliability of the joint, and to improve the durability and reliability of the semiconductor assembly.In addition, in this embodiment, a plurality of semiconductor elements can be mounted on one insulating plate, Since there is no need to separately prepare and bond an insulating plate for each semiconductor element, the manufacturing process of the semiconductor assembly can be simplified.
第９図は、本発明の第６実施例を示すもので、本実施例
は、絶縁板１の裏面に形成される第１のメタライズ面２
ａ、２ｂ、２ｃの周囲にスリット３を介して配設される
第２のメタライズ面４を、多数のスリット３′を介して
細分化したものである。FIG. 9 shows a sixth embodiment of the present invention, in which the first metallized surface 2 formed on the back surface of the insulating plate 1 is
A second metallized surface 4 arranged around slits 3 a, 2b, and 2c is subdivided through a large number of slits 3'.
以上のように本発明によれば、絶縁板とヒートシンク間
の接合部のボイド、クラック等の発生を有効に抑制し、
しかも放熱面積を充分に確保して、半導体素子、Ｊ′４
！！縁板、ヒートシンク等で構成される半導体組立体の
耐久性、信頼性の向上化を図ることができる。As described above, according to the present invention, the occurrence of voids, cracks, etc. at the joint between the insulating plate and the heat sink can be effectively suppressed,
Furthermore, by ensuring a sufficient heat dissipation area, the semiconductor element, J'4
! ! The durability and reliability of the semiconductor assembly including the edge plate, heat sink, etc. can be improved.
第１図は本発明の第１実施例たる絶縁板の裏面図、第２
図（ａ） 、 （ｂ）は上記第１実施例の絶縁板を用い
た半導体組立体の積層構造例を表わす側面図、第３図は
第２図（ａ）の半導体組立体の全体を表わす平面図、第
４図は従来の絶縁板の裏面図。
第５図（ａ） 、 （ｂ）は本発明の第２．第３実施例
たる絶縁板の裏面図、第６図（ａ） 、 （ｂ）は本発
明の第４実施例たる絶縁板の表面図及び裏面図、第６図
（ｃ）は本発明の第５実施例たゐ」絶縁板の裏面図。
第７図（ａ） 、 （ｂ）は上記第４実施例を用いた半
導体組立体の積層構造例を表わす側面図、第８図は第７
図（ａ）の半導体組立体の全体を表わす平面図。
第９図は本発明の第６実施例たる絶縁板の裏面図である
。
１・・・絶縁板、２・・・第１のメタライズ面、２ａ。
２ｂ、２ｃ・・・第１のメタライズ面、３・・・第１の
メタライズ面周囲のスリット部、３′・・・スリット部
、４・・・第２のメタライズ面、５・・・半導体素子、
７・・・ヒートシンク、１０・・・接合部（ろう何部）
、１０ａ・・・第１接合部、１０ｂ・・・第２接合部、
１５・・・スリット状の非接合部。
第１圓
第３回
第５ 口
第 ６ 口
第７回
（ａ）
第３図Figure 1 is a back view of the insulating plate according to the first embodiment of the present invention, and the second
Figures (a) and (b) are side views showing an example of a laminated structure of a semiconductor assembly using the insulating plate of the first embodiment, and Figure 3 shows the entire semiconductor assembly of Figure 2 (a). FIG. 4 is a plan view and a back view of a conventional insulating plate. FIGS. 5(a) and 5(b) show the second embodiment of the present invention. 6(a) and 6(b) are front and back views of an insulating plate according to a fourth embodiment of the present invention, and FIG. 6(c) is a back view of an insulating plate according to a third embodiment of the present invention. FIG. 5 is a back view of the insulating plate of Embodiment 5. 7(a) and 7(b) are side views showing an example of the laminated structure of a semiconductor assembly using the fourth embodiment, and FIG.
FIG. 2 is a plan view showing the entire semiconductor assembly of FIG. FIG. 9 is a back view of an insulating plate according to a sixth embodiment of the present invention. DESCRIPTION OF SYMBOLS 1... Insulating plate, 2... 1st metallized surface, 2a. 2b, 2c...first metallized surface, 3...slit portion around the first metallized surface, 3'...slit portion, 4...second metallized surface, 5...semiconductor element ,
7...Heat sink, 10...Joint part (wax part)
, 10a...first joint part, 10b...second joint part,
15...Slit-shaped non-joint part. 1st round 3rd round 5th round 6th round 7th round (a) Figure 3
Claims (3)
と接合するためのメタライズ面を有する半導体素子用の
絶縁板において、前記メタライズ面は、前記半導体素子
の搭載箇所の直下に形成される第１のメタライズ面と、
この第１のメタライズ面の周囲にメタライズを施さない
スリト部を介して配設される第２のメタライズ面とで構
成され、且つ前記スリット部は、少なくとも一部が前記
絶縁板の端面まで延設されてなることを特徴とする半導
体素子用絶縁板。1. In an insulating plate for a semiconductor element having a semiconductor element mounted on the front surface and a metallized surface for bonding to a heat sink on the back surface, the metallized surface is a first metallized surface formed directly below the mounting location of the semiconductor element. The face and
A second metallized surface is provided around the first metallized surface through a slit portion which is not metalized, and the slit portion is at least partially extended to the end surface of the insulating plate. An insulating board for semiconductor devices characterized by:
イズ面は、複数のスリットにより複数のパターンに区分
されてなる半導体素子用絶縁板。2. 2. The insulating plate for semiconductor devices according to claim 1, wherein the second metallized surface is divided into a plurality of patterns by a plurality of slits.
半導体素子は複数よりなり、前記絶縁板の表面の半導体
素子搭載箇所及び裏面の前記第１のメタライズ面は、そ
れぞれ前記半導体素子の数と同数で、一定の間隔を置い
て配置されてなる半導体素子用絶縁板。3. In claim 1 or 2, the semiconductor elements are comprised of a plurality of semiconductor elements, and the number of semiconductor element mounting locations on the front surface of the insulating plate and the first metallized surface on the back surface are the same as the number of semiconductor elements, respectively. Insulating plates for semiconductor devices, which are arranged at regular intervals.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62262635A JPH07105460B2 (en) | 1987-10-20 | 1987-10-20 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62262635A JPH07105460B2 (en) | 1987-10-20 | 1987-10-20 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH01106451A true JPH01106451A (en) | 1989-04-24 |
| JPH07105460B2 JPH07105460B2 (en) | 1995-11-13 |
Family
ID=17378524
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62262635A Expired - Lifetime JPH07105460B2 (en) | 1987-10-20 | 1987-10-20 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH07105460B2 (en) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5606487A (en) * | 1990-07-18 | 1997-02-25 | Hitachi, Ltd. | Electronic device for offsetting adverse effects of a plurality of chips which repetitively produce large pulses of heat |
| WO2000034539A1 (en) * | 1998-12-07 | 2000-06-15 | Hitachi, Ltd. | Composite material and use thereof |
| EP1995774A2 (en) | 2007-05-25 | 2008-11-26 | Kabushiki Kaisha Toyota Jidoshokki | Semiconductor device |
| JP2010232369A (en) * | 2009-03-26 | 2010-10-14 | Honda Motor Co Ltd | Semiconductor device |
| CN102263092A (en) * | 2010-05-31 | 2011-11-30 | 三菱电机株式会社 | Semiconductor module and method of manufacturing the same |
| WO2014034306A1 (en) * | 2012-08-29 | 2014-03-06 | 日立オートモティブシステムズ株式会社 | Electronic control device |
| JP2016082088A (en) * | 2014-10-17 | 2016-05-16 | 株式会社Uacj | Heat sink with circuit board, and method of manufacturing the same |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62203354A (en) * | 1986-03-03 | 1987-09-08 | Mitsubishi Electric Corp | Semiconductor device |
-
1987
- 1987-10-20 JP JP62262635A patent/JPH07105460B2/en not_active Expired - Lifetime
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62203354A (en) * | 1986-03-03 | 1987-09-08 | Mitsubishi Electric Corp | Semiconductor device |
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5606487A (en) * | 1990-07-18 | 1997-02-25 | Hitachi, Ltd. | Electronic device for offsetting adverse effects of a plurality of chips which repetitively produce large pulses of heat |
| WO2000034539A1 (en) * | 1998-12-07 | 2000-06-15 | Hitachi, Ltd. | Composite material and use thereof |
| KR100352993B1 (en) * | 1998-12-07 | 2002-09-18 | 가부시끼가이샤 히다치 세이사꾸쇼 | Composite material and application thereof |
| US6909185B1 (en) | 1998-12-07 | 2005-06-21 | Hitachi, Ltd. | Composite material including copper and cuprous oxide and application thereof |
| EP1995774A2 (en) | 2007-05-25 | 2008-11-26 | Kabushiki Kaisha Toyota Jidoshokki | Semiconductor device |
| JP2010232369A (en) * | 2009-03-26 | 2010-10-14 | Honda Motor Co Ltd | Semiconductor device |
| CN102263092A (en) * | 2010-05-31 | 2011-11-30 | 三菱电机株式会社 | Semiconductor module and method of manufacturing the same |
| JP2011249723A (en) * | 2010-05-31 | 2011-12-08 | Mitsubishi Electric Corp | Semiconductor module and manufacturing method thereof |
| WO2014034306A1 (en) * | 2012-08-29 | 2014-03-06 | 日立オートモティブシステムズ株式会社 | Electronic control device |
| JP2014045156A (en) * | 2012-08-29 | 2014-03-13 | Hitachi Automotive Systems Ltd | Electronic control device |
| JP2016082088A (en) * | 2014-10-17 | 2016-05-16 | 株式会社Uacj | Heat sink with circuit board, and method of manufacturing the same |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH07105460B2 (en) | 1995-11-13 |
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