JP7501889B2 - Method for manufacturing bonded wafer and method for manufacturing acoustic wave device - Google Patents

Method for manufacturing bonded wafer and method for manufacturing acoustic wave device Download PDF

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JP7501889B2
JP7501889B2 JP2020055189A JP2020055189A JP7501889B2 JP 7501889 B2 JP7501889 B2 JP 7501889B2 JP 2020055189 A JP2020055189 A JP 2020055189A JP 2020055189 A JP2020055189 A JP 2020055189A JP 7501889 B2 JP7501889 B2 JP 7501889B2
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惠一郎 本山
敦哉 高橋
治 川内
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H3/00—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators
    • H03H3/007—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks
    • H03H3/02—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks for the manufacture of piezoelectric or electrostrictive resonators or networks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02002—Preparing wafers
    • H01L21/02005—Preparing bulk and homogeneous wafers
    • H01L21/02008—Multistep processes
    • H01L21/0201—Specific process step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02002—Preparing wafers
    • H01L21/02005—Preparing bulk and homogeneous wafers
    • H01L21/02008—Multistep processes
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    • H01L21/02013—Grinding, lapping
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H9/00—Networks comprising electromechanical or electro-acoustic devices; Electromechanical resonators
    • H03H9/02—Details
    • H03H9/125—Driving means, e.g. electrodes, coils
    • H03H9/145—Driving means, e.g. electrodes, coils for networks using surface acoustic waves
    • H03H9/14538—Formation
    • H03H9/14541—Multilayer finger or busbar electrode
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N30/00—Piezoelectric or electrostrictive devices
    • H10N30/01—Manufacture or treatment
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Description

本発明は、圧電性基板用ウエハと非圧電性基板用ウエハとを接合した接合ウエハの製造方法と弾性波デバイスの製造方法に関する。 The present invention relates to a method for manufacturing a bonded wafer in which a wafer for a piezoelectric substrate and a wafer for a non-piezoelectric substrate are bonded together, and a method for manufacturing an acoustic wave device .

弾性表面波デバイス等の弾性波デバイスは、圧電性基板上に櫛型電極やパッド電極などを形成し、圧電性基板と実装基板との間に空隙部を形成して構成される。弾性波デバイスを製造する場合、圧電性基板は、特性改善のため、圧電性基板より熱膨張率の低い非圧電性基板をウエハ状態で接合する。そして、接合したウエハの状態で櫛型電極等の励振電極やパッド電極等の電極形成を行なう。圧電性基板に非圧電性基板を接合する目的の１つに、温度変化に伴う特性変化を防止することがある。すなわち、弾性波デバイスをフィルタとして構成した場合、圧電性基板の温度変化により変形すると、櫛型電極のピッチが変化し、フィルタリングする周波数が変化する。このような周波数変化を抑制するため、圧電性基板に、圧電性基板より熱膨張率が低い非圧電性基板を接合する。これにより、圧電性基板の温度変化による変形を抑制し、フィルタリングする周波数の変化を防止する。 An acoustic wave device such as a surface acoustic wave device is configured by forming a comb electrode or a pad electrode on a piezoelectric substrate and forming a gap between the piezoelectric substrate and a mounting substrate. When manufacturing an acoustic wave device, a non-piezoelectric substrate having a lower thermal expansion coefficient than the piezoelectric substrate is bonded to the piezoelectric substrate in a wafer state in order to improve the characteristics. Then, in the bonded wafer state, electrodes such as an excitation electrode such as a comb electrode and a pad electrode are formed. One of the purposes of bonding a non-piezoelectric substrate to a piezoelectric substrate is to prevent a change in characteristics due to a temperature change. That is, when an acoustic wave device is configured as a filter, if the piezoelectric substrate is deformed due to a temperature change , the pitch of the comb electrode changes, and the frequency to be filtered changes. In order to suppress such a frequency change, a non-piezoelectric substrate having a lower thermal expansion coefficient than the piezoelectric substrate is bonded to the piezoelectric substrate. This suppresses the deformation of the piezoelectric substrate due to a temperature change, and prevents a change in the frequency to be filtered.

弾性波デバイスにおいては、圧電性基板にＬＴ（リチウム酸タンタレート）やＬＮ（リチウム酸ニオブ）を用いる場合、結晶方位により弾性表面波の伝播特性が変化するため、圧電性基板と非圧電性基板との接合に際し、少なくとも圧電性基板の結晶方位について配慮する必要がある。さらには、非圧電性基板が単結晶の場合は、非圧電性基板の結晶方位についても配慮する場合もある。このため、円形をなすウエハの外周の一部にウエハの位置及び方向を示すオリエンテーションフラット（以下オリフラと称す。）が設けられている（例えば特許文献１参照）。 In acoustic wave devices, when LT (lithium tantalate) or LN (lithium niobium oxide) is used for the piezoelectric substrate, the propagation characteristics of the surface acoustic wave change depending on the crystal orientation, so when bonding the piezoelectric substrate to the non-piezoelectric substrate, it is necessary to take into consideration at least the crystal orientation of the piezoelectric substrate. Furthermore, when the non-piezoelectric substrate is a single crystal, the crystal orientation of the non-piezoelectric substrate may also be taken into consideration. For this reason, an orientation flat (hereinafter referred to as an orientation flat) indicating the position and orientation of the wafer is provided on part of the outer periphery of the circular wafer (see, for example, Patent Document 1).

図２２に特許文献１に示された従来の接合ウエハ７０を示す。この従来の接合ウエハ７０は、非圧電性基板用ウエハ７１と圧電性基板用ウエハ７２とを接着剤７３により接合している。非圧電性基板用ウエハ７１と圧電性基板用ウエハ７２の外周には、それぞれオリフラ７１ａ、７２ａが設けられている。このような接合ウエハ７０を製造する際には、まずそれぞれオリフラ７１ａ、７２ａを有する非圧電性基板用ウエハ７１と圧電性基板用ウエハ７２とをそれぞれ別々に製造する。そして、接合の際には、それぞれ、オリフラ７１ａとオリフラ７２ａの位置と方向が一致するようにして接合を行なう。その後、研磨装置により圧電性基板用ウエハ７２の表面を機械的に研磨して圧電性基板用ウエハ７２を薄くする。続いて、ＣＭＰ工程（化学的機械研磨）を行ない、圧電性基板用ウエハ７２をさらに薄くすると共に、電極形成面である圧電性基板用ウエハ７２の表面７２ｂを平滑化する。 Figure 22 shows a conventional bonded wafer 70 shown in Patent Document 1. In this conventional bonded wafer 70, a non-piezoelectric substrate wafer 71 and a piezoelectric substrate wafer 72 are bonded together with an adhesive 73. The non-piezoelectric substrate wafer 71 and the piezoelectric substrate wafer 72 are provided with orientation flats 71a and 72a on their outer peripheries. When manufacturing such a bonded wafer 70, the non-piezoelectric substrate wafer 71 and the piezoelectric substrate wafer 72, each having orientation flats 71a and 72a, are first manufactured separately. Then, when bonding, the positions and directions of the orientation flats 71a and 72a are aligned, respectively, and bonding is performed. After that, the surface of the piezoelectric substrate wafer 72 is mechanically polished by a polishing device to thin the piezoelectric substrate wafer 72. Next, a CMP process (chemical mechanical polishing) is performed to further thin the piezoelectric substrate wafer 72 and smooth the surface 72b of the piezoelectric substrate wafer 72, which is the electrode formation surface.

特開２０１０－１８７３７３号公報JP 2010-187373 A

上述した従来の接合ウエハ７０の場合、これを研磨して圧電性基板用ウエハ７２を薄くする工程を経た後に、圧電性基板用ウエハ７２において、オリフラ７２ａ近傍の領域の厚さが他の領域の厚さよりも薄くなるということが判明した。このことは、圧電性基板用ウエハ７２の厚さの不均一化を招く。このような圧電性基板用ウエハ７２の厚さの不均一は、複数個分の弾性波デバイス用の接合ウエハを分断したものから弾性波デバイスを製造する際に、弾性波デバイスの周波数特性の不揃いの原因になる。 In the case of the conventional bonded wafer 70 described above, it was found that after the process of polishing the wafer 72 for the piezoelectric substrate to thin it, the thickness of the region of the wafer 72 for the piezoelectric substrate near the orientation flat 72a becomes thinner than the thickness of other regions. This leads to non-uniformity in the thickness of the wafer 72 for the piezoelectric substrate. Such non-uniformity in the thickness of the wafer 72 for the piezoelectric substrate causes non-uniformity in the frequency characteristics of the acoustic wave device when the acoustic wave device is manufactured from the pieces obtained by cutting the bonded wafer for the acoustic wave device.

本発明は、上述した問題点に鑑み、圧電性基板用ウエハがその全域において厚さが均一となる接合ウエハの製造方法と弾性波デバイスの製造方法を提供することを目的とする。 In view of the above-mentioned problems, an object of the present invention is to provide a method for manufacturing a bonded wafer in which a piezoelectric substrate wafer has a uniform thickness over its entire area, and a method for manufacturing an acoustic wave device.

本発明の接合ウエハの製造方法の一つの態様は、圧電性基板用ウエハと非圧電性基板用ウエハとが接合された接合ウエハの製造方法において、外周にオリフラを有する非圧電性基板用ウエハを製造する工程と、前記非圧電性基板用ウエハより狭い面積を有し、外周にオリフラを有する圧電性基板用ウエハを製造する工程と、前記非圧電性基板用ウエハと前記圧電性基板用ウエハとを、各ウエハに設けたオリフラの向きが一致し、かつ両ウエハの外周弧状円が同心をなすように両ウエハを接合する工程と、前記接合した圧電性基板用ウエハの弧状をなす外周を、円弧状の研磨面に沿って、オリフラが消滅する以下のウエハサイズになるまで研磨する工程と、を含む。 One embodiment of the method for manufacturing a bonded wafer of the present invention is a method for manufacturing a bonded wafer in which a piezoelectric substrate wafer and a non-piezoelectric substrate wafer are bonded together, the method comprising the steps of: manufacturing a non-piezoelectric substrate wafer having an orientation flat on its outer periphery; manufacturing a piezoelectric substrate wafer having an area smaller than that of the non-piezoelectric substrate wafer and having an orientation flat on its outer periphery; bonding the non-piezoelectric substrate wafer and the piezoelectric substrate wafer so that the orientations of the orientation flats on each wafer match and the outer periphery arc-shaped circles of both wafers are concentric; and polishing the arc-shaped periphery of the bonded piezoelectric substrate wafer along an arc-shaped polishing surface until the wafer size becomes equal to or smaller than the wafer size at which the orientation flat disappears.

この接合ウエハの製造方法では、圧電性基板用ウエハと非圧電性基板用ウエハを接合する前の段階では、両ウエハはその外周側にオリフラを有するため、これらのオリフラを例えば光学的に検出して位置制御を行ない、予め設定された相対位置で両ウエハを接合することができる。その後、圧電性基板用ウエハの外周を、オリフラが無くなるまで削除すると、圧電性基板用ウエハはオリフラが無い状態となる。このため、圧電性基板用ウエハの表面を研磨する際に、圧電性基板用ウエハは全面において非圧電性基板用ウエハに安定的に支持される。その結果、オリフラ領域側が他の領域よりも研磨深さが深くなることが無くなり、圧電性基板用ウエハの全領域における厚さが均一化される。このため、接合ウエハを構成している圧電性基板用ウエハに、複数個分の弾性波デバイス用の電極を形成し、その接合ウエハを分断したものを用いて弾性波デバイスを製造する際に、周波数特性が揃ったものが得られる。 In this method of manufacturing a bonded wafer, before the piezoelectric substrate wafer and the non-piezoelectric substrate wafer are bonded, both wafers have orientation flats on their outer peripheries, and these orientation flats can be detected, for example, optically, and their positions controlled to bond the two wafers at a preset relative position. If the outer periphery of the piezoelectric substrate wafer is then removed until the orientation flat disappears, the piezoelectric substrate wafer will have no orientation flat. Therefore, when the surface of the piezoelectric substrate wafer is polished, the entire surface of the piezoelectric substrate wafer is stably supported by the non-piezoelectric substrate wafer. As a result, the orientation flat region is no longer polished deeper than other regions, and the thickness of the entire region of the piezoelectric substrate wafer is made uniform. Therefore, when electrodes for multiple acoustic wave devices are formed on the piezoelectric substrate wafers that constitute the bonded wafer, and the bonded wafer is cut to produce acoustic wave devices, the frequency characteristics are consistent.

本発明の接合ウエハの製造方法の他の態様は、圧電性基板用ウエハと非圧電性基板用ウエハとが接合された接合ウエハの製造方法において、外周にオリフラを有する非圧電性基板用ウエハを製造する工程と、前記非圧電性基板用ウエハより狭い面積を有し、前記非圧電性基板用ウエハとの接合面の反対側である面に、オリフラの代わりにマークを有する圧電性基板用ウエハを製造する工程と、前記非圧電性基板用ウエハと前記圧電性基板用ウエハとを、２枚のウエハの相対的な向きが予め設定された向きとなり、かつ両ウエハの外周弧状円が同心をなすように接合する工程と、前記接合した圧電性基板用ウエハの弧状をなす外周を研磨する工程と、を含む。 Another aspect of the method for manufacturing a bonded wafer of the present invention is a method for manufacturing a bonded wafer in which a piezoelectric substrate wafer and a non-piezoelectric substrate wafer are bonded, the method comprising the steps of manufacturing a non-piezoelectric substrate wafer having an orientation flat on its outer periphery, manufacturing a piezoelectric substrate wafer having an area smaller than that of the non-piezoelectric substrate wafer and having a mark instead of an orientation flat on a surface opposite to the bonding surface with the non-piezoelectric substrate wafer, bonding the non-piezoelectric substrate wafer and the piezoelectric substrate wafer so that the relative orientations of the two wafers are in a predetermined orientation and the outer periphery arc-shaped circles of both wafers are concentric, and polishing the arc-shaped outer periphery of the bonded piezoelectric substrate wafer.

この接合ウエハの製造方法では、圧電性基板用ウエハと非圧電性基板用ウエハを接合する前段階では、圧電性基板用ウエハはマークを有し、非圧電性基板用ウエハはオリフラを有するため、これらのマーク及びオリフラを例えば光学的に検出して位置制御を行ない、予め設定された相対位置で両ウエハを接合することができる。接合後、圧電性基板用ウエハの表面を研磨する際には、圧電性基板用ウエハはオリフラを有しない。このため、圧電性基板用ウエハの表面研磨の際に、オリフラ領域側が他の領域よりも研磨深さが深くなることが無くなり、圧電性基板用ウエハの全領域における厚さが均一化される。このため、接合ウエハを構成している圧電性基板用ウエハに、複数個分の弾性波デバイス用の電極を形成し、その接合ウエハを分断したものを用いて弾性波デバイスを製造する際に、周波数特性が揃ったものが得られる。 In this method of manufacturing a bonded wafer, prior to bonding the piezoelectric substrate wafer and the non-piezoelectric substrate wafer, the piezoelectric substrate wafer has a mark and the non-piezoelectric substrate wafer has an orientation flat, so that these marks and orientation flats can be detected, for example, optically, and position control can be performed to bond the two wafers at a preset relative position. After bonding, when the surface of the piezoelectric substrate wafer is polished, the piezoelectric substrate wafer does not have an orientation flat. Therefore, when the surface of the piezoelectric substrate wafer is polished, the orientation flat region is not polished deeper than other regions, and the thickness of the entire region of the piezoelectric substrate wafer is made uniform. Therefore, when electrodes for multiple acoustic wave devices are formed on the piezoelectric substrate wafers constituting the bonded wafer, and the bonded wafer is cut and used to manufacture acoustic wave devices, the frequency characteristics are consistent.

本発明の接合ウエハの製造方法のさらに他の一つの態様は、圧電性基板用ウエハと非圧電性基板用ウエハとが接合された接合ウエハの製造方法において、外周側にオリフラを有する非圧電性基板用ウエハを製造する工程と、前記非圧電性基板用ウエハより狭い面積を有し、オリフラの代わりにダブルノッチを有する圧電性基板用ウエハを製造する工程と、前記非圧電性基板用ウエハと前記圧電性基板用ウエハとを、両ウエハの相対的な向きが予め設定された向きとなり、かつ同心をなすように接合する工程と、前記接合した圧電性基板用ウエハの弧状をなす外周を、円弧状の研磨面に沿って、前記ダブルノッチが消滅する以下のウエハサイズになるまで研磨する工程と、を含む。 Yet another embodiment of the method for manufacturing a bonded wafer of the present invention is a method for manufacturing a bonded wafer in which a piezoelectric substrate wafer and a non-piezoelectric substrate wafer are bonded together, the method comprising the steps of manufacturing a non-piezoelectric substrate wafer having an orientation flat on its outer periphery, manufacturing a piezoelectric substrate wafer having an area smaller than that of the non-piezoelectric substrate wafer and having a double notch instead of an orientation flat, bonding the non-piezoelectric substrate wafer and the piezoelectric substrate wafer so that the relative orientations of the two wafers are in a predetermined direction and are concentric, and polishing the arc-shaped outer periphery of the bonded piezoelectric substrate wafer along an arc-shaped polishing surface until the wafer size becomes equal to or smaller than the wafer size at which the double notch disappears.

この接合ウエハの製造方法では、圧電性基板用ウエハと非圧電性基板用ウエハを接合する前段階では、両ウエハはそれぞれその外周側にオリフラとダブルノッチを有するため、これらを例えば光学的に検出して位置制御を行ない、予め設定された相対位置で両ウエハを接合することができる。接合後、圧電性基板用ウエハの表面研磨の際に、圧電性基板用ウエハにオリフラが無いため、従来のように、オリフラ領域側が他の領域よりも研磨深さが深くなることが無くなり、圧電性基板用ウエハの全領域における厚さが均一化される。このため、接合ウエハを構成している圧電性基板用ウエハに、複数個分の弾性波デバイス用の電極を形成し、その接合ウエハを分断したものを用いて弾性波デバイスを製造する際に、周波数特性が揃ったものが得られる。 In this method of manufacturing bonded wafers, prior to bonding the piezoelectric substrate wafer and the non-piezoelectric substrate wafer, both wafers have an orientation flat and a double notch on their outer periphery, and these can be detected, for example, optically to control the position and bond the two wafers at a preset relative position. After bonding, when the surface of the piezoelectric substrate wafer is polished, since the piezoelectric substrate wafer has no orientation flat, the orientation flat region is not polished deeper than other regions as in the past, and the thickness of the entire region of the piezoelectric substrate wafer is made uniform. For this reason, electrodes for multiple acoustic wave devices are formed on the piezoelectric substrate wafers that make up the bonded wafer, and when acoustic wave devices are manufactured using cut pieces of the bonded wafer, products with uniform frequency characteristics can be obtained.

本発明の弾性波デバイスの製造方法の一つの態様は、接合ウエハとして、上述した態様の接合ウエハの製造方法のいずれかにより製造された接合ウエハを用い、前記接合ウエハの前記圧電性基板用ウエハ上に複数の弾性波デバイス用の電極を形成する工程と、前記複数の弾性波デバイス用の電極を形成した接合ウエハを個々の弾性波デバイス用のベアチップに分断する工程と、前記ベアチップを実装基板用ウエハ上に実装する工程と、前記ベアチップを実装した実装基板用ウエハを個々の弾性波デバイスに分断する工程とを含む。 One aspect of the method for manufacturing an acoustic wave device of the present invention includes the steps of using a bonded wafer manufactured by any of the above-mentioned aspects of the method for manufacturing a bonded wafer as a bonded wafer, forming electrodes for a plurality of acoustic wave devices on the piezoelectric substrate wafer of the bonded wafer, dividing the bonded wafer on which the electrodes for the plurality of acoustic wave devices have been formed into bare chips for individual acoustic wave devices, mounting the bare chips on a wafer for a mounting substrate, and dividing the wafer for a mounting substrate on which the bare chips have been mounted into individual acoustic wave devices.

このように、接合ウエハとして、オリフラの無い圧電性基板用ウエハを、非圧電性基板用ウエハに接合したものを用いることにより、周波数特性が揃った弾性波デバイスが得られる。 In this way, by using a wafer for a piezoelectric substrate without an orientation flat bonded to a wafer for a non-piezoelectric substrate as the bonding wafer, an acoustic wave device with consistent frequency characteristics can be obtained.

本発明によれば、圧電性基板用ウエハと非圧電性基板用ウエハの接合ウエハにおいて、圧電性基板用ウエハの表面を研磨することにより、圧電性基板用ウエハの厚さを薄くしかつ表面を平滑化する場合、圧電性基板用ウエハの全面にわたり、より均一化された厚さが得られる。このため、接合ウエハの圧電性基板用ウエハ上に複数個の弾性波デバイス分の電極を形成し、接合ウエハを分断して弾性波デバイスを得る場合、周波数特性が揃った弾性波デバイスを得ることができる。 According to the present invention, in a bonded wafer of a piezoelectric substrate wafer and a non-piezoelectric substrate wafer, when the surface of the piezoelectric substrate wafer is polished to reduce the thickness of the piezoelectric substrate wafer and smooth the surface, a more uniform thickness is obtained over the entire surface of the piezoelectric substrate wafer. Therefore, when electrodes for multiple acoustic wave devices are formed on the piezoelectric substrate wafer of the bonded wafer and the bonded wafer is divided to obtain acoustic wave devices, acoustic wave devices with uniform frequency characteristics can be obtained.

本発明の接合ウエハの一実施の形態の接合ウエハを示す斜視図である。1 is a perspective view showing a bonded wafer according to an embodiment of the bonded wafer of the present invention; 図１の接合ウエハの平面図である。FIG. 2 is a plan view of the bonded wafer of FIG. 1 . 図１の接合ウエハの側面図である。FIG. 2 is a side view of the bonded wafer of FIG. 1 . 本発明の接合ウエハの製造方法の第１の実施の形態を示す工程図である。1A to 1C are process diagrams showing a first embodiment of a method for producing a bonded wafer of the present invention. 図１の接合ウエハの製造工程における圧電性基板用ウエハの外周部分の研磨機構を示す図である。2 is a diagram showing a polishing mechanism for the outer periphery of a piezoelectric substrate wafer in the manufacturing process of the bonded wafer of FIG. 1 . FIG. （ａ）～（ｃ）は図１の接合ウエハにおける圧電性基板用ウエハの表面の研磨工程による圧電性基板用ウエハの厚さの変化を示す図である。2A to 2C are diagrams showing changes in thickness of the piezoelectric substrate wafer in the bonded wafer of FIG. 1 due to a polishing process of the surface of the piezoelectric substrate wafer. 図１の接合ウエハにおける圧電性基板用ウエハの表面の研磨機構を示す図である。2 is a diagram showing a polishing mechanism of the surface of the piezoelectric substrate wafer in the bonded wafer of FIG. 1 . （ａ）は圧電性基板用ウエハ表面のＣＭＰ研磨機構を示す斜視図、（ｂ）はその研磨機構のうち、ウエハを保持するホルダを示す側面図である。FIG. 2A is a perspective view showing a CMP polishing mechanism for a surface of a wafer for a piezoelectric substrate, and FIG. 2B is a side view showing a holder for holding a wafer in the polishing mechanism. 圧電性基板用ウエハがオリフラを有する場合と有しない場合とについて、圧電性基板用ウエハの厚さのばらつきについて対比試験を行なった際の、接合ウエハの平面構造を示す平面図である。13 is a plan view showing the planar structure of a bonded wafer when a comparison test was conducted on the variation in thickness of a piezoelectric substrate wafer when the piezoelectric substrate wafer has an orientation flat and when the piezoelectric substrate wafer does not have an orientation flat. FIG. 圧電性基板用ウエハの表面研磨後の厚さが１．５μｍに設定されている場合、従来例と本発明の各一例における、複数の測定点についての圧電性基板用ウエハの厚みを比較して示すグラフである。1 is a graph showing a comparison of thicknesses of a piezoelectric substrate wafer at a plurality of measurement points in a conventional example and an example of the present invention, when the thickness of the piezoelectric substrate wafer after surface polishing is set to 1.5 μm. 表面研磨後の圧電性基板用ウエハの厚さが３μｍに設定されている場合において、図１０と同じく各測定点における圧電性基板用ウエハの厚さを比較して示すグラフである。11 is a graph showing a comparison of thicknesses of a piezoelectric substrate wafer at each measurement point, similar to FIG. 10, in a case where the thickness of the piezoelectric substrate wafer after surface polishing is set to 3 μm. 表面研磨後の圧電性基板用ウエハの厚さが５μｍに設定されている場合において、図１０と同じく各測定点における圧電性基板用ウエハの厚さを比較して示すグラフである。11 is a graph showing a comparison of thicknesses of a piezoelectric substrate wafer at each measurement point, similar to FIG. 10, in a case where the thickness of the piezoelectric substrate wafer after surface polishing is set to 5 μm. 弾性表面波デバイスとして構成される共振器における圧電性基板の厚さと共振周波数及び***振周波数との関係の一例を示すグラフである。1 is a graph showing an example of the relationship between the thickness of a piezoelectric substrate and the resonance frequency and anti-resonance frequency in a resonator configured as a surface acoustic wave device. 弾性表面波デバイスとして構成されるフィルタの電極構成例を示す平面図である。1 is a plan view showing an example of an electrode configuration of a filter configured as a surface acoustic wave device; 図１４に示すフィルタにおける、周波数と減衰量との関係を、中心周波数と共に示す図である。FIG. 15 is a diagram showing the relationship between frequency and attenuation in the filter shown in FIG. 14 together with the center frequency. 従来のようにオリフラがあるウエハと、本発明のようにオリフラが無いウエハの各一例について、図１４に示すフィルタを構成した場合の中心周波数の分布を示すグラフである。15 is a graph showing the distribution of center frequencies when the filter shown in FIG. 14 is constructed for each of an example of a conventional wafer having an orientation flat and an example of a wafer having no orientation flat according to the present invention. 本発明の接合ウエハの製造方法の第２の実施の形態を示す工程図である。5A to 5C are process diagrams showing a second embodiment of a method for producing a bonded wafer according to the present invention. 本発明の接合ウエハの製造方法の第３の実施の形態を示す工程図である。11A to 11C are process diagrams showing a third embodiment of a method for producing a bonded wafer of the present invention. 本発明の接合ウエハの製造方法の第４の実施の形態に用いる圧電性基板用ウエハと製造方法の工程図である。13A to 13C are diagrams showing a piezoelectric substrate wafer used in a fourth embodiment of a method for manufacturing a bonded wafer according to the present invention and steps of the manufacturing method. 本発明による弾性波デバイスの製造方法の一実施の形態の工程の一部を示す工程図である。3A to 3C are process diagrams showing some of the steps of an embodiment of a method for manufacturing an acoustic wave device according to the present invention. 本発明による弾性波デバイスの製造方法の一実施の形態の工程の残部を示す工程図である。10A to 10C are process diagrams showing the remaining steps of the embodiment of the method for manufacturing an acoustic wave device according to the present invention. 従来の接合ウエハの一例を示す斜視図である。FIG. 1 is a perspective view showing an example of a conventional bonded wafer.

＜第１の実施の形態＞
本発明による接合ウエハの第１の実施の形態を図１～図３により説明する。接合ウエハ１は、非圧電性基板用ウエハ２と、圧電性基板用ウエハ３とを接合して構成される。圧電性基板用ウエハ３は、弾性表面波デバイスを構成する場合には、タンタル酸リチウム（ＬＴ）又はニオブ酸リチウム（ＬＮ）が用いられる。非圧電性基板用ウエハ２は、圧電性基板用ウエハ３より熱膨張率が低い例えばシリコン、サファイア、多結晶アルミナ、多結晶スピネル、水晶又はガラス等が用いられる。しかしながら本発明においては、非圧電性基板用ウエハ２や圧電性基板用ウエハ３としてはこれらの材料に限定されず、他の材料を使用してもよい。また、本発明は、圧電性基板の厚さにより特性の変化が生じる他の弾性波デバイスに適用される。 First Embodiment
A first embodiment of the bonded wafer according to the present invention will be described with reference to Figs. 1 to 3. The bonded wafer 1 is formed by bonding a non-piezoelectric substrate wafer 2 and a piezoelectric substrate wafer 3. When a surface acoustic wave device is to be formed, lithium tantalate (LT) or lithium niobate (LN) is used for the piezoelectric substrate wafer 3. For the non-piezoelectric substrate wafer 2, a material having a lower thermal expansion coefficient than the piezoelectric substrate wafer 3, such as silicon, sapphire, polycrystalline alumina, polycrystalline spinel, quartz, or glass, is used. However, in the present invention, the non-piezoelectric substrate wafer 2 and the piezoelectric substrate wafer 3 are not limited to these materials, and other materials may be used. The present invention is also applicable to other acoustic wave devices in which the characteristics change depending on the thickness of the piezoelectric substrate.

非圧電性基板用ウエハ２は、その外周２ａに、直線状をなすオリフラ２ａ１を有する。非圧電性基板用ウエハ２の外周２ａにおけるオリフラ２ａ１以外の部分は円弧状をなす。圧電性基板用ウエハ３は円形をなし、オリフラを有していない。圧電性基板用ウエハ３は、非圧電性基板用ウエハ２より狭い面積を有する。そして、図２に示すように、オリフラ２ａ１を含む非圧電性基板用ウエハ２の外周２ａは、圧電性基板用ウエハ３の外周３ａよりも外側に位置する。圧電性基板用ウエハ３の外周３ａで描かれる円は、非圧電性基板用ウエハ２の外周２ａで描かれる円と同心をなすように接合される。 The non-piezoelectric substrate wafer 2 has a linear orientation flat 2a1 on its outer periphery 2a. The portion of the outer periphery 2a of the non-piezoelectric substrate wafer 2 other than the orientation flat 2a1 is arc-shaped. The piezoelectric substrate wafer 3 has a circular shape and does not have an orientation flat. The piezoelectric substrate wafer 3 has a smaller area than the non-piezoelectric substrate wafer 2. As shown in FIG. 2, the outer periphery 2a of the non-piezoelectric substrate wafer 2, including the orientation flat 2a1, is located outside the outer periphery 3a of the piezoelectric substrate wafer 3. The circle formed by the outer periphery 3a of the piezoelectric substrate wafer 3 is bonded to be concentric with the circle formed by the outer periphery 2a of the non-piezoelectric substrate wafer 2.

図３に示すように、圧電性基板用ウエハ３の厚さｔ１は、非圧電性基板用ウエハ２の厚さｔ２より薄く（ｔ１＜ｔ２）形成される。例えば圧電性基板用ウエハ３の厚さｔ１は０．２μｍ以上、２０μｍ以下であり、非圧電性基板用ウエハ２の厚さｔ２は８０μｍ以上、５００μｍ以下である。しかし本発明においては、各ウエハ２、３の厚さはこれらの値に限定されない。 As shown in FIG. 3, the thickness t1 of the piezoelectric substrate wafer 3 is formed to be thinner than the thickness t2 of the non-piezoelectric substrate wafer 2 (t1<t2). For example, the thickness t1 of the piezoelectric substrate wafer 3 is 0.2 μm or more and 20 μm or less, and the thickness t2 of the non-piezoelectric substrate wafer 2 is 80 μm or more and 500 μm or less. However, in the present invention, the thicknesses of the wafers 2 and 3 are not limited to these values.

この接合ウエハ１の製造工程は、図４（ａ）に示す非圧電性基板用ウエハ２を製造する工程と、図４（ｂ）に示す圧電性基板用ウエハ３Ｘを製造する工程と、図４（ｃ）に示すようにウエハ２、３Ｘを接合して接合ウエハ１Ｘを得る工程と、接合ウエハ１Ｘの圧電性基板用ウエハ３Ｘの外周を研磨して図４（ｄ）に示すように、外径を縮小させた圧電性基板用ウエハ３を有する接合ウエハ１を得る工程とを含む。 The manufacturing process of this bonded wafer 1 includes a step of manufacturing a non-piezoelectric substrate wafer 2 shown in FIG. 4(a), a step of manufacturing a piezoelectric substrate wafer 3X shown in FIG. 4(b), a step of bonding the wafers 2 and 3X together to obtain a bonded wafer 1X as shown in FIG. 4(c), and a step of polishing the outer periphery of the piezoelectric substrate wafer 3X of the bonded wafer 1X to obtain a bonded wafer 1 having a piezoelectric substrate wafer 3 with a reduced outer diameter as shown in FIG. 4(d).

図４（ａ）に示す非圧電性基板用ウエハ２の製造は、従来と同様の工程で行なう。例えば円柱形で得られるインゴットからインゴットの両端をスライサーにより切除する工程と、インゴットの外周の研削等により、インゴットの全長について直径を揃える工程と、直径を揃えたインゴットの側面をスライス又は研削することにより、ウエハのオリフラ２ａ１となる平面部分を形成する工程と、インゴットをスライサーによりウエハ状に切断する工程と、切断により得られたウエハを研磨する工程である。ただし、オリフラ２ａ１の形成は、ウエハとして得られた後に研削等により形成してもよい。図４（ａ）に示す圧電性基板用ウエハ３Ｘの製造も同様の工程により行なわれる。ただし、圧電性基板用ウエハ３Ｘは、その外周円の直径が、非圧電性基板用ウエハ２の外周円の直径よりも小さくなるように形成する。すなわち、圧電性基板用ウエハ３Ｘの面積は、非圧電性基板用ウエハ２の面積より狭い。 The non-piezoelectric substrate wafer 2 shown in FIG. 4(a) is manufactured by the same process as in the conventional method. For example, the process includes a step of cutting both ends of a cylindrical ingot with a slicer, a step of grinding the outer periphery of the ingot to make the diameter uniform over the entire length of the ingot, a step of slicing or grinding the side of the ingot with the uniform diameter to form a flat portion that will become the orientation flat 2a1 of the wafer, a step of cutting the ingot into a wafer shape with a slicer, and a step of polishing the wafer obtained by cutting. However, the orientation flat 2a1 may be formed by grinding after the wafer is obtained. The piezoelectric substrate wafer 3X shown in FIG. 4(a) is also manufactured by the same process. However, the piezoelectric substrate wafer 3X is formed so that the diameter of its outer periphery is smaller than the diameter of the outer periphery of the non-piezoelectric substrate wafer 2. In other words, the area of the piezoelectric substrate wafer 3X is smaller than the area of the non-piezoelectric substrate wafer 2.

非圧電性基板用ウエハ２と圧電性基板用ウエハ３Ｘとの接合は、非圧電性基板用ウエハ２と圧電性基板用ウエハ３Ｘとを、それぞれのウエハに設けたオリフラ２ａ１とオリフラ３ｂ１の向きが一致するようにして行なう。また、この接合は、非圧電性基板用ウエハ２と圧電性基板用ウエハ３Ｘの外周弧状円が同心をなすようにして行なう。 The non-piezoelectric substrate wafer 2 and the piezoelectric substrate wafer 3X are bonded together such that the orientations of the orientation flats 2a1 and 3b1 on the non-piezoelectric substrate wafer 2 and the piezoelectric substrate wafer 3X are aligned. This bonding is also performed so that the outer circumferential arc circles of the non-piezoelectric substrate wafer 2 and the piezoelectric substrate wafer 3X are concentric.

非圧電性基板用ウエハ２と圧電性基板用ウエハ３Ｘの接合は、接着剤により行なうこともできる。しかしながら本実施の形態においては、この接合を常温接合により行なっている。この常温接合を行なう場合、アルゴン等の原子ビームを、非圧電性基板用ウエハ２の接合面と、圧電性基板用ウエハ３Ｘの接合面に照射して接合面を活性化する。そして、圧電性基板用ウエハ３Ｘと非圧電性基板用ウエハ２とを、両ウエハの接合面に存在する原子どうしの原子間力によって接合するものである。このため、接合するウエハを加熱する必要がなく、接合後に接合面にストレスが残留せず、接合ウエハの歪みや反りの発生を防止できる。 The non-piezoelectric substrate wafer 2 and the piezoelectric substrate wafer 3X can also be bonded with an adhesive. However, in this embodiment, this bonding is performed by room temperature bonding. When performing this room temperature bonding, an atomic beam of argon or the like is irradiated onto the bonding surfaces of the non-piezoelectric substrate wafer 2 and the piezoelectric substrate wafer 3X to activate the bonding surfaces. Then, the piezoelectric substrate wafer 3X and the non-piezoelectric substrate wafer 2 are bonded by the atomic force between the atoms present on the bonding surfaces of both wafers. Therefore, there is no need to heat the wafers to be bonded, no stress remains on the bonding surfaces after bonding, and the occurrence of distortion or warping of the bonded wafers can be prevented.

図４（ｃ）に示すように非圧電性基板用ウエハ２と圧電性基板用ウエハ３Ｘとを接合した後は、図４（ｄ）に示すように、二点点線で示す圧電性基板用ウエハ３Ｘの外周３ｂが、実線で示す外周３ａにまで縮小した円となるように研磨する。すなわち、圧電性基板用ウエハ３Ｘの外周３ｂの研磨により、円弧状の研磨面に沿って、オリフラ３ｂ１が消滅する以下のウエハサイズとし、圧電性基板用ウエハ３を得る。なお、ここで、オリフラ３ｂ１が消滅する以下のウエハサイズの意味するところは、厳密な意味でオリフラ３ｂ１が消滅するという意味ではなく、実質的にオリフラ３ｂ１が消滅する程度に外周が研磨されればよい。 After bonding the non-piezoelectric substrate wafer 2 and the piezoelectric substrate wafer 3X as shown in FIG. 4(c), as shown in FIG. 4(d), the outer periphery 3b of the piezoelectric substrate wafer 3X, shown by the two-dot dotted line, is polished to a circle shrunk to the outer periphery 3a, shown by the solid line. That is, by polishing the outer periphery 3b of the piezoelectric substrate wafer 3X, the wafer size is reduced along the arc-shaped polished surface to the wafer size below which the orientation flat 3b1 disappears, and the piezoelectric substrate wafer 3 is obtained. Note that the wafer size below which the orientation flat 3b1 disappears does not mean that the orientation flat 3b1 disappears in the strict sense, but rather it is sufficient that the outer periphery is polished to the extent that the orientation flat 3b1 essentially disappears.

このような圧電性基板用ウエハ３Ｘの外周３ｂの研磨は、例えば図５に示す機構の研磨装置を用いて行なう。すなわち非圧電性基板用ウエハ２と圧電性基板用ウエハ３Ｘとを接合した接合ウエハ１Ｘを不図示の回転テーブル上に固定する。一方、回転テーブルに対して回転軸５ｘが例えば回転テーブルの半径方向に向いた回転砥石５を設ける。回転砥石５は、円盤状の砥石本体５ａと、砥石本体５ａを保持する砥石ホルダ５ｂとを備える。圧電性基板用ウエハ３Ｘの外周３ｂの研磨は、回転テーブルと共に接合ウエハ１Ｘを矢印６に示すように回転させると同時に、砥石本体５ａを圧電性基板用ウエハ３Ｘの外周３ｂに接触させ、かつ矢印７に示すように回転させて行なう。圧電性基板用ウエハ３Ｘの外周３ｂの研磨の進行に伴い、砥石本体５ａが次第に接合ウエハ１Ｘの回転中心に近づく方向に、接合ウエハ１Ｘをセットしている回転テーブルと回転砥石５の少なくともいずれか一方を移動させる。 Such polishing of the outer periphery 3b of the piezoelectric substrate wafer 3X is performed, for example, by using a polishing device having a mechanism as shown in FIG. 5. That is, the bonded wafer 1X obtained by bonding the non-piezoelectric substrate wafer 2 and the piezoelectric substrate wafer 3X is fixed on a rotating table (not shown). On the other hand, a rotary grindstone 5 is provided with a rotation axis 5x facing, for example, in the radial direction of the rotating table relative to the rotating table. The rotary grindstone 5 includes a disk-shaped grindstone body 5a and a grindstone holder 5b for holding the grindstone body 5a. The outer periphery 3b of the piezoelectric substrate wafer 3X is polished by rotating the bonded wafer 1X together with the rotating table as shown by the arrow 6, and at the same time, by bringing the grindstone body 5a into contact with the outer periphery 3b of the piezoelectric substrate wafer 3X and rotating it as shown by the arrow 7. As the polishing of the outer periphery 3b of the piezoelectric substrate wafer 3X progresses, at least one of the rotating table on which the bonded wafer 1X is set and the rotary grindstone 5 is moved in a direction in which the grindstone body 5a gradually approaches the center of rotation of the bonded wafer 1X.

このような圧電性基板用ウエハ３Ｘの外周３ｂの研磨を行なった後、続いて圧電性基板用ウエハ３の表面の研磨を行なう。すなわち図６（ａ）に示すように、厚さｔaの未研磨状態から、圧電性基板用ウエハ３の表面３ｃ１の機械研磨により、図６（ｂ）に示す厚さｔｂと、厚さが大幅に減少するように研磨を行なう。続いて図６（ｂ）に示す圧電性基板用ウエハ３の表面３ｃ２を、化学的機械研磨により、図６（ｃ）に示す厚さｔｃに厚さを減少させると共に、表面３ｃの平滑化を行なう。 After polishing the outer periphery 3b of the piezoelectric substrate wafer 3X in this way, the surface of the piezoelectric substrate wafer 3 is then polished. That is, as shown in FIG. 6(a), the surface 3c1 of the piezoelectric substrate wafer 3 is mechanically polished to reduce the thickness significantly from an unpolished state of thickness ta to thickness tb shown in FIG. 6(b). Next, the surface 3c2 of the piezoelectric substrate wafer 3 shown in FIG. 6(b) is chemically and mechanically polished to reduce the thickness to thickness tc shown in FIG. 6(c), and the surface 3c is smoothed.

図６（ａ）から図６（ｂ）に至るように、圧電性基板用ウエハ３の厚さを大幅に減少させる機械研磨は、例えば図７に示すような研磨機構により行なう。この機械研磨機構は、不図示の回転テーブルにセットされる接合ウエハ１に対し、その上面、すなわち圧電性基板用ウエハ３の表面３ｃ１を研磨するための研磨ホイール９を備える。この研磨ホイール９は、円盤状をなし、下面に接合ウエハ１の圧電性基板用ウエハ３を研磨する複数の研磨ピース９ａがリング状に配置されている。研磨ホイール９は、回転駆動軸９ｂを有する。 As shown in Fig. 6(a) through Fig. 6(b), mechanical polishing to significantly reduce the thickness of the piezoelectric substrate wafer 3 is performed by a polishing mechanism such as that shown in Fig. 7. This mechanical polishing mechanism is equipped with a polishing wheel 9 for polishing the upper surface of the bonded wafer 1 set on a rotating table (not shown), i.e., the surface 3c1 of the piezoelectric substrate wafer 3. This polishing wheel 9 is disk-shaped, and multiple polishing pieces 9a for polishing the piezoelectric substrate wafer 3 of the bonded wafer 1 are arranged in a ring shape on the underside. The polishing wheel 9 has a rotation drive shaft 9b.

この研磨機構においては、接合ウエハ１を研磨するに当たり、研磨ホイール９の研磨ピース９ａが、その研磨ピース９ａの集合体で接合ウエハ１の回転中心から外周に亘る範囲について接触するように、研磨ホイール９を位置決めする。そして、接合ウエハ１を不図示の回転テーブルと共に矢印１０に示すように回転させると同時に、研磨ホイール９を矢印１１に示すように回転させて接合ウエハ１の表面、すなわち圧電性基板用ウエハ３の表面３ｃ１を研磨する。 In this polishing mechanism, when polishing the bonded wafer 1, the polishing wheel 9 is positioned so that the polishing pieces 9a of the polishing wheel 9 are in contact with the bonded wafer 1 over a range from the center of rotation to the outer periphery as a group of the polishing pieces 9a. The bonded wafer 1 is then rotated together with a rotating table (not shown) as indicated by arrow 10, and at the same time, the polishing wheel 9 is rotated as indicated by arrow 11 to polish the surface of the bonded wafer 1, i.e., the surface 3c1 of the piezoelectric substrate wafer 3.

その後の図６（ｂ）から図６（ｃ）に至る化学的機械研磨においては、研磨による圧電性基板用ウエハ３の厚さの減少度合が少なく、精度良くかつ表面を平滑に研磨する。この化学的機械研磨は、例えば図８に示すような研磨機構により行なう。この化学的機械研磨装置は、不図示の回転テーブル上に固定される研磨パッド１４を有する。研磨パッド１４上には、スラリー供給装置１５により、圧電性基板用ウエハ３に対して化学的研磨作用を果たすスラリー状の研磨剤１６が供給される。一方、接合ウエハ１は、円形のホルダ１７の下面に、圧電性基板用ウエハ３を下向きにして保持される。そして、ホルダ１７の位置決め機構により、接合ウエハ１を研磨パッド１４に加圧状態で接触させ、研磨パッド１４を矢印１８に示すように回転させて圧電性基板用ウエハ３の表面の化学的機械研磨を行なう。 In the subsequent chemical mechanical polishing from FIG. 6(b) to FIG. 6(c), the thickness of the piezoelectric substrate wafer 3 is reduced by polishing, and the surface is polished accurately and smoothly. This chemical mechanical polishing is performed by a polishing mechanism such as that shown in FIG. 8. This chemical mechanical polishing device has a polishing pad 14 fixed on a rotating table (not shown). A slurry supplying device 15 supplies a slurry-like abrasive 16, which performs a chemical polishing action on the piezoelectric substrate wafer 3, onto the polishing pad 14. Meanwhile, the bonded wafer 1 is held on the lower surface of a circular holder 17 with the piezoelectric substrate wafer 3 facing downward. Then, the positioning mechanism of the holder 17 brings the bonded wafer 1 into contact with the polishing pad 14 under pressure, and the polishing pad 14 is rotated as shown by the arrow 18 to perform chemical mechanical polishing of the surface of the piezoelectric substrate wafer 3.

このように圧電性基板用ウエハ３のオリフラを無くしたことによる圧電性基板用ウエハ３の厚さ均一化の効果を確認するため、オリフラの有る圧電性基板用ウエハ３との対比試験を行なった。対比試験は、図９に点線で示すように、オリフラ３ｂ１を残した場合と、オリフラ３ｂ１を残さない実線で示す場合とについて、機械研磨と化学的機械研磨後の圧電性基板用ウエハ３の厚さの分布を調べた。非圧電性基板用ウエハ２にはサファイアを用い、厚さを４００μｍとした。圧電性基板用ウエハ３にはタンタル酸リチウム（ＬＴ）を用い、目標厚さを１．５μｍ、３μｍ、５μｍとしてそれぞれの厚さで対比試験を行なった。 To confirm the effect of making the thickness of the piezoelectric substrate wafer 3 uniform by eliminating the orientation flat in this way, a comparison test was conducted with a piezoelectric substrate wafer 3 with an orientation flat. In the comparison test, the thickness distribution of the piezoelectric substrate wafer 3 after mechanical polishing and chemical mechanical polishing was examined for the case where the orientation flat 3b1 was left as shown by the dotted line in Figure 9, and the case where the orientation flat 3b1 was not left as shown by the solid line. Sapphire was used for the non-piezoelectric substrate wafer 2, with a thickness of 400 μm. Lithium tantalate (LT) was used for the piezoelectric substrate wafer 3, and comparison tests were conducted for each thickness with target thicknesses of 1.5 μm, 3 μm, and 5 μm.

また、非圧電性基板用ウエハ２の外周２ａの円弧部分の直径は１００ｍｍとした。また、オリフラ３ｂ１が有る場合における、圧電性基板用ウエハ３Ｘの外周３ｂの円弧部分の直径は９５ｍｍとした。また、オリフラ３ｂ１の無い圧電性基板用ウエハ３の外周３ａの一部を、外周３ｂを研磨する前のオリフラ３ｂ１と一致させた。 The diameter of the arc portion of the outer periphery 2a of the non-piezoelectric substrate wafer 2 was set to 100 mm. When the orientation flat 3b1 was present, the diameter of the arc portion of the outer periphery 3b of the piezoelectric substrate wafer 3X was set to 95 mm. A portion of the outer periphery 3a of the piezoelectric substrate wafer 3 without the orientation flat 3b1 was made to coincide with the orientation flat 3b1 before the outer periphery 3b was polished.

図９に、圧電性基板用ウエハ３、３Ｘにおける研磨後の厚さの測定点５０を示す。測定点５０は、圧電性基板用ウエハ３、３Ｘの中心からオリフラ（ＯＦ）３ｂ１側に離れる方向に５ｍｍごとの間隔に設定した。圧電性基板用ウエハ３の厚さの測定はレーザビームを用いる厚さ測定装置により行なった。 Figure 9 shows measurement points 50 for the thickness of the piezoelectric substrate wafer 3, 3X after polishing. The measurement points 50 were set at intervals of 5 mm in the direction away from the center of the piezoelectric substrate wafer 3, 3X toward the orientation flat (OF) 3b1. The thickness of the piezoelectric substrate wafer 3 was measured using a thickness measuring device that uses a laser beam.

図１０～図１２に示されるように、目標の厚さ１．５μｍ、３μｍ、５μｍのいずれの場合であっても、オリフラ３ｂ１が有る場合に、圧電性基板用ウエハ３Ｘのオリフラ（ＯＦ）３ｂ１側の測定点（図１０～図１２における－５ｍｍ～－４０ｍｍの測定点）では、オリフラ３ｂ１の反対側の測定点より、圧電性基板用ウエハ３Ｘの厚さは狭くなった。一方、オリフラ３ｂ１の無い圧電性基板用ウエハ３の場合、外周研磨前に存在したオリフラ３ｂ１側とその反対側の厚さの差は小さくなった。表１はこのような厚さ測定における厚さの最大値と最小値との差Ｒ（μｍ）と標準偏差（μｍ）とを示す。表１から、オリフラ３ｂ１を無くしたことにより、圧電性基板用ウエハ３全体における厚さのばらつきが大幅に改善されることが分かる。 As shown in Figures 10 to 12, whether the target thickness is 1.5 μm, 3 μm, or 5 μm, when the orientation flat 3b1 is present, the thickness of the piezoelectric substrate wafer 3X is narrower at the measurement points on the orientation flat (OF) 3b1 side of the piezoelectric substrate wafer 3X (measurement points at -5 mm to -40 mm in Figures 10 to 12) than at the measurement points on the opposite side of the orientation flat 3b1. On the other hand, in the case of a piezoelectric substrate wafer 3 without the orientation flat 3b1, the difference in thickness between the orientation flat 3b1 side that existed before peripheral polishing and the opposite side is smaller. Table 1 shows the difference R (μm) between the maximum and minimum thickness values in such thickness measurements, and the standard deviation (μm). It can be seen from Table 1 that the elimination of the orientation flat 3b1 significantly improves the thickness variation throughout the piezoelectric substrate wafer 3.

Figure 0007501889000001
Figure 0007501889000001

図１３はタンタル酸リチウム（ＬＴ）を圧電性基板に用い、非圧電性基板にシリコンを用いて弾性表面波デバイスで共振器を構成した場合における、圧電性基板の厚さと共振周波数Ｆｒ及び***振周波数Ｆａとの関係を示す。この関係を調べるため、圧電性基板用ウエハ３の表面に櫛型電極を形成して共振器を構成し、圧電性基板の厚さ０．５μｍ～１０μｍの範囲で変えて共振周波数Ｆｒと***振周波数Ｆａの測定を行なった。 13 shows the relationship between the thickness of the piezoelectric substrate and the resonance frequency Fr and anti-resonance frequency Fa when a resonator is constructed with a surface acoustic wave device using lithium tantalate (LT) for the piezoelectric substrate and silicon for the non-piezoelectric substrate. To investigate this relationship, a comb-shaped electrode was formed on the surface of the piezoelectric substrate wafer 3 to construct a resonator, and the resonance frequency Fr and anti-resonance frequency Fa were measured while changing the thickness of the piezoelectric substrate in the range of 0.5 μm to 10 μm .

図１３から理解されるように、圧電性基板の厚さが約３μｍ以下になると、圧電性基板の厚さが共振周波数Ｆｒ及び***振周波数Ｆａに影響を与え、特に２μｍ以下になると、その影響が甚大になることが分かる。そのため、圧電性基板を薄型化して共振器の高周波化とＱ値の向上を計る場合に、圧電性基板用ウエハ３の全面における厚さの均一化は重要な課題であることが分かる。 As can be seen from Fig. 13, when the thickness of the piezoelectric substrate is about 3 µm or less, the thickness of the piezoelectric substrate affects the resonance frequency Fr and the anti-resonance frequency Fa , and when the thickness is 2 µm or less, the effect becomes particularly significant. Therefore, when thinning the piezoelectric substrate to increase the frequency of the resonator and improve the Q value, it is clear that making the thickness uniform over the entire surface of the piezoelectric substrate wafer 3 is an important issue.

図１４は圧電性基板用ウエハ３の表面に形成される複数個のフィルタ２０の電極パターンの一例を示す。このフィルタ２０は、それぞれ反射器２１を並設した共振器１９Ａ～１９Ｅをラダー構造に組んで構成される。一部の共振器１９Ａ～１９Ｃは、入力ポート２２と出力ポート２３との間のライン２４に挿入される。他の共振器１９Ｄ，１９Ｅは、ライン２４とグランドポート２５ａ、２５ｂとの間にそれぞれ挿入される。このフィルタは、各共振器１９Ａ～１９Ｅをそれぞれラダー構造の基本単位として構成されるもので、各共振器１９Ａ～１９Ｃのインピーダンスと各共振器１９Ｄ、１９Ｅのインピーダンスとで決定される通過帯域を持つ。図１５は図１４に示すフィルタの通過帯域と中心周波数Ｆｏの概略を示す。 Figure 14 shows an example of the electrode pattern of multiple filters 20 formed on the surface of a piezoelectric substrate wafer 3. This filter 20 is composed of resonators 19A to 19E, each of which has a reflector 21 arranged in parallel, assembled into a ladder structure. Some of the resonators 19A to 19C are inserted into a line 24 between an input port 22 and an output port 23. The other resonators 19D and 19E are inserted between the line 24 and ground ports 25a and 25b, respectively. This filter is composed of the resonators 19A to 19E as basic units of the ladder structure, and has a passband determined by the impedance of each of the resonators 19A to 19C and the impedance of each of the resonators 19D and 19E. Figure 15 shows an outline of the passband and center frequency Fo of the filter shown in Figure 14.

図１４の電極パターンを有するフィルタの試作を、圧電性基板用ウエハ３にオリフラ３ｂ１を有するものと、有しないもので行ない、中心周波数Ｆｏのばらつきについて比較した。この試作において、圧電性基板用ウエハ３にタンタル酸リチウム（ＬＴ）を用い、その設定厚さを３μｍとした。また、非圧電性基板用ウエハ２にサファイアを用い、その厚さを４００μｍとした。また、共振器１９Ａ～１９Ｅ及び反射器２１の電極ピッチを２．１０μｍとした。 Filters having the electrode pattern of Figure 14 were prototyped with and without orientation flat 3b1 on the piezoelectric substrate wafer 3, and the variations in center frequency Fo were compared. In this prototype, lithium tantalate (LT) was used for the piezoelectric substrate wafer 3, with a set thickness of 3 μm. Sapphire was used for the non-piezoelectric substrate wafer 2, with a thickness of 400 μm. The electrode pitch of resonators 19A-19E and reflector 21 was 2.10 μm.

図１６は圧電性基板用ウエハ３にオリフラ３ｂ１を有するものと、これを有しないものを用い、図１４に示す構成のフィルタを構成した場合の中心周波数Ｆｏの分布を示す。この中心周波数の測定は、オリフラ３ｂ１を有するウエハから得たフィルタと、オリフラ３ｂ１を有しないもののサンプルをそれぞれ４５個ずつとり行なった。そして測定値から、中心周波数の最大値Ｒmaxと最小値Ｒminの差であるレンジ（Ｒmax－Ｒmin）(MHz)と標準偏差σ（MHz）を求めた。表２にその結果を示す。 Figure 16 shows the distribution of center frequencies Fo when a filter with the configuration shown in Figure 14 is constructed using piezoelectric substrate wafers 3 with and without orientation flat 3b1. This center frequency was measured using 45 samples each of filters obtained from wafers with orientation flat 3b1 and those without orientation flat 3b1. From the measured values, the range (Rmax - Rmin) (MHz), which is the difference between the maximum value Rmax and the minimum value Rmin of the center frequency, and the standard deviation σ (MHz) were calculated. The results are shown in Table 2.

Figure 0007501889000002
Figure 0007501889000002

表２から分かるように、図１４に示したフィルタを構成した場合、オリフラを無くした圧電性基板用ウエハから得たフィルタの場合、オリフラが有る圧電性基板用ウエハから得たフィルタよりも中心周波数のレンジが狭く、標準偏差σの値も小さくなった。すなわち、オリフラを無くした圧電性基板用ウエハから得たフィルタの場合、周波数特性が揃ったフィルタが得られた。 As can be seen from Table 2, when constructing the filter shown in Figure 14, the filter obtained from a piezoelectric substrate wafer without an orientation flat had a narrower center frequency range and a smaller standard deviation σ value than the filter obtained from a piezoelectric substrate wafer with an orientation flat. In other words, the filter obtained from a piezoelectric substrate wafer without an orientation flat had a filter with consistent frequency characteristics.

＜第２の実施の形態＞
本発明による接合ウエハの製造方法の第２の実施の形態を図１７により説明する。この実施の形態は、圧電性基板用ウエハ３Ｘとして、オリフラ３ｂ１の代わりに、オリフラ３ｂ１と同位置となるウエハ表面にマーク３ｄを印したものである。このマーク３ｄは、レーザ又は色つきインクの印刷等により印すことができる。また、このマーク３ｄは、線状ではなく、３ｄで示す線状部分よりも外周側に、他の領域と異なる色の物質を着けたものであってもよい。また、このマーク３ｄは、接合のための位置合わせの際に、撮像装置により光学的に検出されるためのものであるため、非圧電性基板用ウエハ２との接合面の反対側の面に設ける。 Second Embodiment
A second embodiment of the method for manufacturing a bonded wafer according to the present invention will be described with reference to Fig. 17. In this embodiment, instead of the orientation flat 3b1, a mark 3d is printed on the wafer surface at the same position as the orientation flat 3b1 as a piezoelectric substrate wafer 3X. This mark 3d can be printed by a laser or by printing with colored ink. This mark 3d may not be linear, but may be a material of a different color from the other regions applied to the outer periphery of the linear portion indicated by 3d. This mark 3d is provided on the surface opposite to the surface to be bonded to the non-piezoelectric substrate wafer 2, since it is optically detected by an imaging device during alignment for bonding.

この第２の実施の形態により接合ウエハを製造する場合、図１７（ａ）に示すように、外周にオリフラ２ａ１を有する非圧電性基板用ウエハ２を製造する。また、図１７（ｂ）に示すように、非圧電性基板用ウエハ２より狭い面積を有し、非圧電性基板用ウエハとの接合面の反対側である表面に、オリフラの代わりにマーク３ｄを有する圧電性基板用ウエハ３Ｘを製造する。続いて図１７（ｃ）に示すように、非圧電性基板用ウエハ２と圧電性基板用ウエハ３Ｘとを、２枚のウエハの相対的な向きが予め設定された向きとなり、かつ両ウエハの外周弧状円が同心をなすように、オリフラ２ａ１及びマーク３ｄの位置を光学的に検出して、その位置情報に基づき、非圧電性基板用ウエハ２と圧電性基板用ウエハ３Ｘの相対位置を調整して接合する。この例においては、オリフラ２ａ１とマーク３ｄとが平行をなすようにして接合しているが、必ずしも平行である必要がなく、オリフラ２ａ１に対する圧電性基板用ウエハ３Ｘの結晶方位が予め定められた方位になればよい。両ウエハ２、３Ｘの接合後は、接合した圧電性基板用ウエハ３Ｘが非圧電性基板用ウエハ２から剥がれ難くするため、圧電性基板用ウエハ３Ｘの弧状をなす外周３ｂを、図１７（ｄ）に実線で示すように、円弧状の外周３ｂに沿って研磨する。 When manufacturing a bonded wafer according to the second embodiment, as shown in FIG. 17(a), a non-piezoelectric substrate wafer 2 having an orientation flat 2a1 on the outer periphery is manufactured. Also, as shown in FIG. 17(b), a piezoelectric substrate wafer 3X having a smaller area than the non-piezoelectric substrate wafer 2 and a mark 3d instead of the orientation flat is manufactured on the surface opposite to the bonding surface with the non-piezoelectric substrate wafer. Next, as shown in FIG. 17(c), the positions of the orientation flat 2a1 and the mark 3d are optically detected so that the relative orientation of the two wafers is a preset orientation and the peripheral arc-shaped circles of both wafers are concentric, and the non-piezoelectric substrate wafer 2 and the piezoelectric substrate wafer 3X are bonded by adjusting the relative positions of the non-piezoelectric substrate wafer 2 and the piezoelectric substrate wafer 3X based on the position information. In this example, the orientation flat 2a1 and the mark 3d are bonded in parallel, but they do not necessarily need to be parallel, and it is sufficient that the crystal orientation of the piezoelectric substrate wafer 3X relative to the orientation flat 2a1 is a predetermined orientation. After the two wafers 2 and 3X are bonded together, the arc-shaped outer periphery 3b of the piezoelectric substrate wafer 3X is polished along the arc-shaped outer periphery 3b as shown by the solid line in FIG. 17(d) so that the bonded piezoelectric substrate wafer 3X is not easily peeled off from the non-piezoelectric substrate wafer 2.

この第２の実施の形態の製造方法においては、圧電性基板用ウエハ３Ｘは、上述の態様と同様に、圧電性基板用ウエハ３はオリフラ３ｂ１を有しない。このため、圧電性基板用ウエハ３の表面研磨の際に、オリフラ領域側が他の領域よりも研磨深さが深くなることが無くなり、圧電性基板用ウエハ３の全領域における厚さが均一化される。その結果、接合ウエハを分断したものから弾性波デバイスを製造する際に、周波数特性が揃ったものが得られる。 In the manufacturing method of this second embodiment, the piezoelectric substrate wafer 3X does not have an orientation flat 3b1, as in the above-mentioned embodiment. Therefore, when polishing the surface of the piezoelectric substrate wafer 3, the orientation flat region side is not polished deeper than other regions, and the thickness of the entire region of the piezoelectric substrate wafer 3 is made uniform. As a result, when acoustic wave devices are manufactured from the cut pieces of the bonded wafer, the frequency characteristics are consistent.

この第２の実施の形態の製造方法においては、圧電性基板用ウエハ３Ｘはオリフラ３ｂ１を有しない。このため、圧電性基板用ウエハ３の表面研磨の際に、オリフラ領域側が他の領域よりも研磨深さが深くなることが無くなり、圧電性基板用ウエハ３の全領域における厚さが均一化される。また、圧電性基板用ウエハ３の表面３ｃを研磨した後は、マーク３ｄは消滅している。その結果、接合ウエハを分断したものから弾性波デバイスを製造する際に、周波数特性が揃ったものが得られる。 In the manufacturing method of the second embodiment, the piezoelectric substrate wafer 3X does not have an orientation flat 3b1. Therefore, when polishing the surface of the piezoelectric substrate wafer 3, the orientation flat area is not polished deeper than other areas, and the thickness of the entire area of the piezoelectric substrate wafer 3 is made uniform. Furthermore, after polishing the surface 3c of the piezoelectric substrate wafer 3, the mark 3d disappears. As a result, when acoustic wave devices are manufactured from the cut pieces of the bonded wafer, the frequency characteristics are consistent.

＜第３の実施の形態＞
本発明による接合ウエハの製造方法の第３の実施の形態を図１８により説明する。この実施の形態は、圧電性基板用ウエハ３Ｘとして、第１の実施の形態におけるオリフラ３ｂ１の代わりに、オリフラ３ｂ１と同位置となるウエハ表面にマーク３ｄを印したものである。また、非圧電性基板用ウエハ２Ｘについても同様に、圧電性基板用ウエハ３Ｘとの接合面の反対側の面に、オリフラ２ａ１の代わりに、オリフラ２ａ１と同位置にマーク２ｂを設けたものである。これらのマーク２ｂ、３ｄは、レーザ又は色つきインクの印刷等により印すことができる。また、これらの２ｂ、３ｄは、線状ではなく、２ｂ、３ｄで示す線状部分よりも外周側に、他の領域と異なる色の物質を着けたものであってもよい。 Third Embodiment
A third embodiment of the method for manufacturing a bonded wafer according to the present invention will be described with reference to Fig. 18. In this embodiment, instead of the orientation flat 3b1 in the first embodiment, a mark 3d is printed on the wafer surface of the piezoelectric substrate wafer 3X at the same position as the orientation flat 3b1. Similarly, instead of the orientation flat 2a1, a mark 2b is provided on the surface opposite to the bonding surface with the piezoelectric substrate wafer 3X at the same position as the orientation flat 2a1 for the non-piezoelectric substrate wafer 2X. These marks 2b and 3d can be printed by a laser or by printing with colored ink. Also, these marks 2b and 3d may not be linear, but may be formed by applying a material of a different color from the other regions to the outer periphery of the linear portions indicated by 2b and 3d.

この第３の実施の形態により接合ウエハを製造する場合、図１８（ａ）に示すように、外周にオリフラの代わりにマーク２ｂを有する非圧電性基板用ウエハ２Ｘを製造する。また、図１８（ｂ）に示すように、非圧電性基板用ウエハ２より狭い面積を有し、非圧電性基板用ウエハとの接合面の反対側である表面に、オリフラの代わりにマーク３ｄを有する圧電性基板用ウエハ３Ｘを製造する。続いて図１８（ｃ）に示すように、非圧電性基板用ウエハ２Ｘと圧電性基板用ウエハ３Ｘとを、２枚のウエハの相対的な向きが予め設定された向きとなり、かつ両ウエハ２Ｘ、３Ｘの外周弧状円が同心をなすように、マーク２ｂ及びマーク３ｄの位置を光学的に検出して、その位置情報に基づき、非圧電性基板用ウエハ２Ｘと圧電性基板用ウエハ３Ｘの相対位置を調整して接合する。この例においては、マーク２ｂとマーク３ｄとが平行をなすようにして接合しているが、必ずしも平行である必要がなく、結果として、マーク２ｂに対する圧電性基板用ウエハ３Ｘの結晶方位等が予め定められた方位になればよい。 When manufacturing a bonded wafer according to this third embodiment, as shown in FIG. 18(a), a non-piezoelectric substrate wafer 2X having a mark 2b on the outer periphery instead of an orientation flat is manufactured. Also, as shown in FIG. 18(b), a piezoelectric substrate wafer 3X having a smaller area than the non-piezoelectric substrate wafer 2 and a mark 3d on the surface opposite to the bonding surface with the non-piezoelectric substrate wafer is manufactured. Next, as shown in FIG. 18(c), the positions of the marks 2b and 3d are optically detected, and the relative positions of the non-piezoelectric substrate wafer 2X and the piezoelectric substrate wafer 3X are adjusted based on the position information and bonded so that the relative orientations of the two wafers are preset and the outer periphery arc circles of both wafers 2X and 3X are concentric. In this example, the marks 2b and 3d are joined so as to be parallel to each other, but they do not necessarily have to be parallel, and as a result, it is sufficient that the crystal orientation of the piezoelectric substrate wafer 3X relative to the mark 2b is in a predetermined orientation.

この実施の形態においても、圧電性基板用ウエハ３Ｘの表面を研磨する前に、接合後の圧電性基板用ウエハ３Ｘの剥がれが生じにくくするため、図１８（ｄ）に示すように、圧電性基板用ウエハ３Ｘの外周３ｂを研磨する。 In this embodiment, before polishing the surface of the piezoelectric substrate wafer 3X, the outer periphery 3b of the piezoelectric substrate wafer 3X is polished as shown in FIG. 18(d) to prevent peeling of the piezoelectric substrate wafer 3X after bonding.

この第３の実施の形態の製造方法においても、圧電性基板用ウエハ３Ｘは、オリフラを有しない。このため、圧電性基板用ウエハ３Ｘの表面３ｃを研磨する際に、従来のように、オリフラ領域側が他の領域よりも研磨深さが深くなることが無くなり、圧電性基板用ウエハ３Ｘの全領域における厚さが均一化される。その結果、接合ウエハを分断したものから弾性波デバイスを製造する際に、周波数特性が揃ったものが得られる。 Even in the manufacturing method of the third embodiment, the piezoelectric substrate wafer 3X does not have an orientation flat. Therefore, when polishing the surface 3c of the piezoelectric substrate wafer 3X, the orientation flat region is not polished deeper than other regions as in the conventional method, and the thickness of the entire piezoelectric substrate wafer 3X is made uniform. As a result, when acoustic wave devices are manufactured from the cut pieces of the bonded wafer, the frequency characteristics are consistent.

＜第４の実施の形態＞
本発明による接合ウエハの製造方法の第４の実施の形態を図１９により説明する。この実施の形態は、圧電性基板用ウエハ３Ｙの外周３ｂに、図１９（ａ）に示すように、それぞれＶ字形をなす切欠きであるノッチ３ｆ、３ｆ（以下ダブルノッチと称す。）を設ける。このダブルノッチ３ｆ、３ｆは、第１の実施の形態におけるオリフラ３ｂ１の代わりに設けられる。このダブルノッチ３ｆ、３ｆは、オリフラ３ｂ１の円周方向の両端とほぼ同位置となるウエハ３Ｙの外周３ｂに設けられる。非圧電性基板用ウエハ２については、オリフラ２ａ１を設ける。 <Fourth embodiment>
A fourth embodiment of the method for manufacturing a bonded wafer according to the present invention will be described with reference to Fig. 19. In this embodiment, as shown in Fig. 19(a), notches 3f, 3f (hereinafter referred to as double notches), which are V-shaped notches, are provided on the outer periphery 3b of the piezoelectric substrate wafer 3Y. These double notches 3f, 3f are provided in place of the orientation flat 3b1 in the first embodiment. These double notches 3f, 3f are provided on the outer periphery 3b of the wafer 3Y at approximately the same positions as both ends in the circumferential direction of the orientation flat 3b1. For the non-piezoelectric substrate wafer 2, an orientation flat 2a1 is provided.

この第４の実施の形態により接合ウエハを製造する場合、図１９（ｂ）に示すように、外周にオリフラ２ａ１を有する非圧電性基板用ウエハ２を製造する。また、図１９（ｃ）に示すように、非圧電性基板用ウエハ２より狭い面積を有し、オリフラの代わりにダブルノッチ３ｆ、３ｆを有する圧電性基板用ウエハ３Ｙを製造する。続いて図１９（ｄ）に示すように、非圧電性基板用ウエハ２と圧電性基板用ウエハ３Ｙとを、２枚のウエハの相対的な向きが予め設定された向きとなり、かつ両ウエハ２、３Ｙの外周弧状円が同心をなすように、オリフラ２ａ１及びダブルノッチ３ｆ、３ｆの位置を光学的に検出して、その位置情報に基づき、非圧電性基板用ウエハ２と圧電性基板用ウエハ３Ｙの相対位置を調整して接合する。 When manufacturing bonded wafers according to this fourth embodiment, as shown in FIG. 19(b), a non-piezoelectric substrate wafer 2 having an orientation flat 2a1 on the outer periphery is manufactured. Also, as shown in FIG. 19(c), a piezoelectric substrate wafer 3Y is manufactured having a smaller area than the non-piezoelectric substrate wafer 2 and having double notches 3f, 3f instead of the orientation flat. Next, as shown in FIG. 19(d), the positions of the orientation flat 2a1 and double notches 3f, 3f are optically detected and the relative positions of the non-piezoelectric substrate wafer 2 and the piezoelectric substrate wafer 3Y are adjusted based on the position information and bonded so that the relative orientations of the two wafers are preset and the outer periphery arc circles of both wafers 2, 3Y are concentric.

図１９の実施の形態においても、圧電性基板用ウエハ３Ｙの表面を研磨する前に、図１９（ｄ）に示すように、圧電性基板用ウエハ３Ｙの外周３ｂを研磨する。この場合、外周３ｂのウエハ半径方向についての研磨の深さは、圧電性基板用ウエハ３Ｙのダブルノッチ３ｆ、３ｆが消滅するウエハサイズ３までとする。 In the embodiment of FIG. 19, before polishing the surface of the piezoelectric substrate wafer 3Y, the outer periphery 3b of the piezoelectric substrate wafer 3Y is polished as shown in FIG. 19(d). In this case, the polishing depth of the outer periphery 3b in the wafer radial direction is set to the wafer size 3 at which the double notches 3f, 3f of the piezoelectric substrate wafer 3Y disappear.

この第４の実施の形態の製造方法においても、圧電性基板用ウエハ３Ｙは、オリフラを有しない。このため、圧電性基板用ウエハ３Ｙの表面３ｃ１を研磨する際に、従来のように、オリフラ領域側が他の領域よりも研磨深さが深くなることが無くなり、圧電性基板用ウエハ３Ｙの全領域における厚さが均一化される。その結果、接合ウエハを分断したものから弾性波デバイスを製造する際に、周波数特性が揃ったものが得られる。 Even in the manufacturing method of this fourth embodiment, the piezoelectric substrate wafer 3Y does not have an orientation flat. Therefore, when polishing the surface 3c1 of the piezoelectric substrate wafer 3Y, the orientation flat region is not polished deeper than other regions as in the conventional method, and the thickness is uniform over the entire region of the piezoelectric substrate wafer 3Y. As a result, when acoustic wave devices are manufactured from the cut pieces of the bonded wafer, the frequency characteristics are consistent.

＜第５の実施の形態＞
接合ウエハの製造方法の第５の実施の形態は、非圧電性基板用ウエハ２に、オリフラ２ａ１の代わりに、図１８（ａ）に示したマーク２ｂを設け、図１９に示すように、圧電性基板用ウエハ３Ｙについては、ダブルノッチ３ｆ、３ｆを設けて接合する。この場合も、図１９について説明したように、圧電性基板用ウエハ３Ｙの外周３ｂを、ダブルノッチ３ｆがなくなるまで研磨する。 Fifth embodiment
In a fifth embodiment of the method for manufacturing bonded wafers, a mark 2b shown in Fig. 18(a) is provided on a non-piezoelectric substrate wafer 2 instead of an orientation flat 2a1, and a double notch 3f, 3f is provided on a piezoelectric substrate wafer 3Y for bonding as shown in Fig. 19. In this case as well, the outer periphery 3b of the piezoelectric substrate wafer 3Y is polished until the double notch 3f disappears, as explained in Fig. 19.

この実施の形態においても、圧電性基板用ウエハ３Ｙはオリフラを有しないため、圧電性基板用ウエハ３Ｙの表面３ｃ１を研磨する際に、圧電性基板用ウエハ３Ｙの表面３ｃ１を均一な厚さに研磨することができる。 In this embodiment, the piezoelectric substrate wafer 3Y does not have an orientation flat, so when polishing the surface 3c1 of the piezoelectric substrate wafer 3Y, the surface 3c1 of the piezoelectric substrate wafer 3Y can be polished to a uniform thickness.

次に前述した接合ウエハ１を用いて弾性波デバイスを製造する方法の一実施の形態を、図２０及び図２１により説明する。図２０（ａ）は、第１の実施の形態ないし第３の実施の形態のいずれかの方法で製造された接合ウエハ１上に、例えば図１４に示すフィルタの複数個分の電極パターンを形成した例を模式的に示す。すなわち接合ウエハ１を構成している圧電性基板用ウエハ３上に、弾性表面波により共振器用の電極３１及びパッド電極３２を形成している。ここで、共振器用の電極３１は、櫛型電極及び反射器を意味している。これらの共振器用の電極３１及びパッド電極３２は、圧電性基板用ウエハ３の表面に、フォトリソグラフィ技術を用いて形成されたものである。これらの電極３１、３２等を圧電性基板用ウエハ３に形成した接合ウエハ１は、ブレードダイシングやレーザ等によって、縦横の分断線３３により、図２０（ｂ）に示すように、非圧電性基板２Ｅと圧電性基板３Ｅとを有する個々のベアチップ３５に分断する。 Next, an embodiment of a method for manufacturing an acoustic wave device using the bonded wafer 1 described above will be described with reference to Figs. 20 and 21. Fig. 20(a) shows a schematic example of an electrode pattern for a plurality of filters, such as that shown in Fig. 14, formed on the bonded wafer 1 manufactured by any of the methods of the first to third embodiments. That is, on the piezoelectric substrate wafer 3 constituting the bonded wafer 1, the resonator electrode 31 and the pad electrode 32 are formed by surface acoustic waves. Here, the resonator electrode 31 means a comb-shaped electrode and a reflector. These resonator electrodes 31 and pad electrodes 32 are formed on the surface of the piezoelectric substrate wafer 3 by photolithography technology. The bonded wafer 1 on which these electrodes 31, 32, etc. are formed on the piezoelectric substrate wafer 3 is divided into individual bare chips 35 having a non-piezoelectric substrate 2E and a piezoelectric substrate 3E by blade dicing, laser, etc., along vertical and horizontal dividing lines 33, as shown in Fig. 20(b).

一方、ベアチップ３５の製造工程とは別の工程で、図２０（ｃ）の下段に示すように、セラミック、ガラス、樹脂等の絶縁材でなる分断前の実装基板４０を準備する。実装基板４０は、内部に配線や素子形成用の導体層４３を設ける場合には、導体層４３を形成した実装基板の素材と、別の1枚または複数枚の実装基板の素材とを重ねて接合したものを用いる。実装基板４０の表裏面に、パッド電極４１、４２を形成する。表裏面のパッド電極４１、４２の間は、導体層４３等を介して直接電気的に接続するか、又は内部に形成した不図示の素子を介して電気的に接続する。 Meanwhile, in a process separate from the manufacturing process of the bare chip 35, as shown in the lower part of FIG. 20(c), a mounting substrate 40 made of an insulating material such as ceramic, glass, or resin is prepared before cutting. When a conductor layer 43 for forming wiring or elements is provided inside the mounting substrate 40, the mounting substrate material on which the conductor layer 43 is formed is layered and joined with the material of one or more other mounting substrates. Pad electrodes 41, 42 are formed on the front and back surfaces of the mounting substrate 40. The pad electrodes 41, 42 on the front and back surfaces are electrically connected directly via the conductor layer 43 or the like, or electrically connected via an element (not shown) formed inside.

このようにしてパッド電極４１、４２を設けた実装基板４０に、図２０（ｃ）に示すように、弾性波デバイスのベアチップ３５をフリップチップ実装する。すなわち、実装基板４０のパッド電極４１に対し、ベアチップ３５のパッド電極３２を、バンプ４４を介して接合する。 As shown in FIG. 20(c), the bare chip 35 of the acoustic wave device is flip-chip mounted on the mounting substrate 40 provided with the pad electrodes 41 and 42 in this way. That is, the pad electrode 32 of the bare chip 35 is bonded to the pad electrode 41 of the mounting substrate 40 via the bump 44.

続いて図２１（ａ）に示すように、ベアチップ３５を実装した実装基板４０を硬化性の樹脂層４５で覆う。この樹脂層４５を設けるため、熱硬化性樹脂又は光硬化性樹脂フィルムを接着するか、あるいはフィルムを接着する代わりに、熱硬化性樹脂又は光硬化性樹脂を塗布する。その後、これらの樹脂層４５を加熱するか又は光照射することにより、樹脂を硬化させる。そして、縦横の分断線４６に沿ってブレードダイシングあるいはレーザにより、図２１（ｂ）に示すように、個々のチップに分断して弾性波デバイス４７とする。 Next, as shown in FIG. 21(a), the mounting substrate 40 on which the bare chip 35 is mounted is covered with a curable resin layer 45. To provide this resin layer 45, a thermosetting resin or photocurable resin film is adhered, or instead of adhering a film, a thermosetting resin or photocurable resin is applied. The resin layer 45 is then heated or irradiated with light to harden the resin. Then, as shown in FIG. 21(b), the substrate is divided into individual chips by blade dicing or laser along the vertical and horizontal dividing lines 46 to form acoustic wave devices 47.

このように、圧電性基板用ウエハの厚みが揃った接合ウエハ１を用い、弾性波デバイス４７を製造することにより、周波数特性が揃った弾性波デバイスを得ることができる。 In this way, by manufacturing an acoustic wave device 47 using a bonded wafer 1 with a uniform thickness of the piezoelectric substrate wafer, an acoustic wave device with uniform frequency characteristics can be obtained.

以上本発明を実施の形態により説明したが、本発明を実施する場合、本発明の範囲において、上記例以外の種々の変更、付加が可能である。 The present invention has been described above using embodiments, but when implementing the present invention, various modifications and additions other than the above examples are possible within the scope of the present invention.

１、１Ｘ 接合ウエハ
２、２Ｘ 非圧電性基板用ウエハ
２ａ 外周
２ａ１ オリフラ
２ｂ マーク
２Ｅ 非圧電性基板
３、３Ｘ、３Ｙ 圧電性基板用ウエハ
３ａ、３ｂ 外周
３ｂ１ オリフラ
３ｃ 表面
３ｄ マーク
３Ｅ 圧電性基板
３ｆ ダブルノッチ
１９Ａ～１９Ｅ 共振器
２０ フィルタ
 1, 1X Bonded wafer 2, 2X Non-piezoelectric substrate wafer 2a Outer periphery 2a1 Orientation flat 2b Mark 2E Non-piezoelectric substrate 3, 3X, 3Y Piezoelectric substrate wafer 3a, 3b Outer periphery 3b1 Orientation flat 3c Surface 3d Mark 3E Piezoelectric substrate 3f Double notch 19A to 19E Resonator 20 Filter

Claims (4)

圧電性基板用ウエハと非圧電性基板用ウエハとが接合された接合ウエハの製造方法において、
外周にオリフラを有する非圧電性基板用ウエハを製造する工程と、
前記非圧電性基板用ウエハより狭い面積を有し、外周にオリフラを有する圧電性基板用ウエハを製造する工程と、
前記非圧電性基板用ウエハと前記圧電性基板用ウエハとを、各ウエハに設けたオリフラの向きが一致し、かつ両ウエハの外周弧状円が同心をなすように両ウエハを接合する工程と、
前記接合した圧電性基板用ウエハの弧状をなす外周を、円弧状の研磨面に沿って、オリフラが消滅する以下のウエハサイズになるまで研磨する工程と、を含む接合ウエハの製造方法。 A method for manufacturing a bonded wafer in which a wafer for a piezoelectric substrate and a wafer for a non-piezoelectric substrate are bonded together, comprising the steps of:
A step of manufacturing a non-piezoelectric substrate wafer having an orientation flat on an outer periphery;
manufacturing a wafer for a piezoelectric substrate having an area smaller than that of the wafer for a non-piezoelectric substrate and an orientation flat on an outer periphery;
a step of bonding the non-piezoelectric substrate wafer and the piezoelectric substrate wafer together such that the orientations of the orientation flats of the wafers match and the peripheral arc-shaped circles of the wafers are concentric;
and polishing the arc-shaped outer periphery of the bonded piezoelectric substrate wafers along an arc-shaped polishing surface until the wafer size becomes equal to or smaller than the wafer size at which the orientation flat disappears. 圧電性基板用ウエハと非圧電性基板用ウエハとが接合された接合ウエハの製造方法において、
外周にオリフラを有する非圧電性基板用ウエハを製造する工程と、
前記非圧電性基板用ウエハより狭い面積を有し、前記非圧電性基板用ウエハとの接合面の反対側である面に、オリフラの代わりにマークを有する圧電性基板用ウエハを製造する工程と、
前記非圧電性基板用ウエハと前記圧電性基板用ウエハとを、２枚のウエハの相対的な向きが予め設定された向きとなり、かつ両ウエハの外周弧状円が同心をなすように接合する工程と、
前記接合した圧電性基板用ウエハの弧状をなす外周を研磨する工程と、を含む接合ウエハの製造方法。 A method for manufacturing a bonded wafer in which a wafer for a piezoelectric substrate and a wafer for a non-piezoelectric substrate are bonded together, comprising the steps of:
A step of manufacturing a non-piezoelectric substrate wafer having an orientation flat on an outer periphery;
manufacturing a wafer for a piezoelectric substrate having an area smaller than that of the wafer for a non-piezoelectric substrate and a mark instead of an orientation flat on a surface opposite to a surface to be bonded to the wafer for a non-piezoelectric substrate;
a step of bonding the non-piezoelectric substrate wafer and the piezoelectric substrate wafer together such that the relative orientations of the two wafers are in a preset orientation and the peripheral arc circles of both wafers are concentric;
and polishing the arc-shaped outer periphery of the bonded piezoelectric substrate wafers. 圧電性基板用ウエハと非圧電性基板用ウエハとが接合された接合ウエハの製造方法において、
外周側にオリフラを有する非圧電性基板用ウエハを製造する工程と、
前記非圧電性基板用ウエハより狭い面積を有し、オリフラの代わりにダブルノッチを有する圧電性基板用ウエハを製造する工程と、
前記非圧電性基板用ウエハと前記圧電性基板用ウエハとを、両ウエハの相対的な向きが予め設定された向きとなり、かつ同心をなすように接合する工程と、
前記接合した圧電性基板用ウエハの弧状をなす外周を、円弧状の研磨面に沿って、前記ダブルノッチが消滅する以下のウエハサイズになるまで研磨する工程と、を含む接合ウエハの製造方法。 A method for manufacturing a bonded wafer in which a wafer for a piezoelectric substrate and a wafer for a non-piezoelectric substrate are bonded together, comprising the steps of:
A step of manufacturing a non-piezoelectric substrate wafer having an orientation flat on an outer periphery side;
manufacturing a wafer for a piezoelectric substrate having an area smaller than that of the wafer for a non-piezoelectric substrate and having a double notch instead of an orientation flat;
bonding the non-piezoelectric substrate wafer and the piezoelectric substrate wafer together so that the wafers are concentric and oriented in a predetermined direction relative to one another;
and polishing the arc-shaped outer periphery of the bonded piezoelectric substrate wafers along an arc-shaped polishing surface until the wafer size becomes equal to or smaller than the size at which the double notch disappears. 接合ウエハとして、請求項１ないし請求項３のいずれか１項に記載の製造方法により製造された接合ウエハを用いる弾性波デバイスの製造方法であって、
前記接合ウエハの前記圧電性基板用ウエハ上に複数の弾性波デバイス用の電極を形成する工程と、
前記複数の弾性波デバイス用の電極を形成した接合ウエハを個々の弾性波デバイス用のベアチップに分断する工程と、
前記ベアチップを実装基板上に実装する工程と、
前記ベアチップを実装した実装基板を個々の弾性波デバイスに分断する工程と、を含む弾性波デバイスの製造方法。 A method for manufacturing an acoustic wave device using a bonded wafer manufactured by the manufacturing method according to any one of claims 1 to 3 as a bonded wafer, comprising:
forming a plurality of electrodes for acoustic wave devices on the piezoelectric substrate wafer of the bonded wafer;
dividing the bonded wafer on which electrodes for the plurality of acoustic wave devices are formed into bare chips for individual acoustic wave devices;
mounting the bare chip on a mounting substrate;
and dividing the mounting substrate on which the bare chip is mounted into individual acoustic wave devices.
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