JP7500157B2 - Multi-stage converter control device - Google Patents
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Description
本発明の実施形態は、多段変換器の制御装置に関する。 An embodiment of the present invention relates to a control device for a multi-stage converter.
インバータに代表される半導体電力変換器の大容量手法として、複数台の電力変換器出力を直列接続し高電圧を得る手法がある。これは多段変換器やＭＭＣ（Modular Multilevel Converter）と呼ばれる系統連系変換器や電動機駆動用変換器等の主に大容量変換器に応用されている。 One method for increasing the capacity of semiconductor power converters, such as inverters, is to connect the outputs of multiple power converters in series to obtain high voltage. This is mainly applied to large-capacity converters, such as grid-connected converters called multistage converters or MMCs (Modular Multilevel Converters) and converters for driving electric motors.
多段変換器は、それぞれキャパシタや整流器等の直流電源を有した単位変換器の出力を多直列接続する回路構成により複数レベルの電圧出力が得られるという特徴を持つ。このような特徴から複数ステップの電圧出力が得られ正弦波に近い出力を直接得ることができる。変換器段数が増えるほどにそのステップ数は増加することから、変換器段数が多い場合は、各スイッチング素子をＰＷＭのような高速スイッチングせずに出力電圧基本波周波数で駆動するワンパルス駆動で歪の少ない出力電圧が得られる。ワンパルス駆動ではＰＷＭと比較しスイッチング周波数を抑制できるため毎スイッチング発生するスイッチング損失を低減でき、変換器損失の低減、冷却器の削減効果が期待することができる。 A multi-stage converter has the characteristic that it can obtain multiple levels of voltage output by a circuit configuration in which the output of multiple unit converters, each of which has a DC power source such as a capacitor or rectifier, is connected in series. This characteristic allows a voltage output in multiple steps to be obtained, and an output close to a sine wave can be directly obtained. Since the number of steps increases as the number of converter stages increases, when there are many converter stages, an output voltage with less distortion can be obtained by one-pulse drive, which drives each switching element at the output voltage fundamental frequency without high-speed switching like PWM. With one-pulse drive, the switching frequency can be suppressed compared to PWM, so the switching loss that occurs with each switching can be reduced, and it is expected that the effect of reducing converter losses and reducing the use of coolers can be expected.
多段変換器を動作させるには、単位電力変換器を単体の変換器と同じように三角波キャリア比較等でＰＷＭ変調を行い動作させることが可能だが、ワンパルス変調を行う場合は従来のキャリア比較で動作させることが困難である。そこで、単位変換器としてＨブリッジを用いた多直列変換器のワンパルス変調法が提案されている。 To operate a multi-stage converter, it is possible to operate the unit power converter in the same way as a single converter by performing PWM modulation using triangular wave carrier comparison, etc., but when performing one-pulse modulation, it is difficult to operate it using conventional carrier comparison. Therefore, a one-pulse modulation method for a multi-series converter using an H-bridge as the unit converter has been proposed.
この方式では多段変換器の出力電圧指令と、正と負とに変換器段数と同一個数の電圧ステップを持つ閾値と比較し、指令と閾値が交差する点で各変換器をスイッチングすることでワンパルス変調を実現する方式である。指令と閾値とを比較するシンプルな構成のため容易にワンパルス制御が実装できる。 In this method, the output voltage command of the multi-stage converter is compared with a threshold value that has the same number of voltage steps for positive and negative as the number of converter stages, and one-pulse modulation is achieved by switching each converter at the point where the command and threshold intersect. One-pulse control can be easily implemented due to the simple configuration of comparing the command and threshold value.
しかしながら、出力電圧指令の大きさに応じて電圧出力する変換器段数が変化するため、出力電圧が小さいときには電圧出力する変換器の段数が少なくなり、変換器利用率が低下する。また、電圧を出力しない変換器は、スイッチングを行わずバイパス状態となるため、出力電圧が小さい領域では出力段数低下に伴い低次高調波が増加し、電圧歪が増加することがあった。 However, because the number of converter stages that output voltage changes depending on the magnitude of the output voltage command, when the output voltage is small the number of converter stages that output voltage decreases, resulting in a lower converter utilization rate. Also, converters that do not output voltage do not perform switching and are in a bypass state, so in areas where the output voltage is small, the lower number of output stages increases low-order harmonics and can increase voltage distortion.
本発明の実施形態は上記事情を鑑みて成されたものであって、高調波の発生を抑制し、電圧歪を低減するワンパルス駆動を実現可能な多段変換器の制御装置を提供する。 The embodiment of the present invention has been made in consideration of the above circumstances, and provides a control device for a multi-stage converter that can achieve one-pulse drive that suppresses the generation of harmonics and reduces voltage distortion.
実施形態による多段変換器の制御装置は、一端が高電位側の直流端子に電気的に接続され、他端が第１リアクトルを介して交流端子に電気的に接続された、複数の単位変換器が直列接続して構成される第１アームと、一端が第２リアクトルを介して前記交流端子に電気的に接続され、他端が低電位側の直流端子に電気的に接続された、複数の単位変換器が直列接続して構成される第２アームと、を有し、前記第１アームおよび前記第２アームの複数の前記単位変換器の各々が、直列接続された上側素子と下側素子と、前記上側素子の高電位側端に一端が接続され、前記下側素子の低電位側端に他端が接続されたキャパシタとを備えるとともに、前記上側素子と前記下側素子との接続点が前記高電位側の直流端子、高電位側で隣接する前記単位変換器の前記下側素子と前記キャパシタの接続点、または前記第２リアクトルに接続され、前記下側素子の低電位側端が前記低電位側の直流端子、低電位側で隣接する前記単位変換器の前記上側素子と前記下側素子との接続点、または、前記第１リアクトルに接続される多段変換器、を制御する制御装置であって、前記多段変換器の出力電圧指令と、前記単位変換器の直流電圧と、を用いて変調率を演算する変調率演算部と、前記変調率に基づいて、複数の前記単位変換器の前記上側素子を駆動するゲート信号の複数の位相シフト量を生成する位相シフト量生成部と、出力電圧基本波周波数に基づき、オンパルス幅とオフパルス幅とが同一で、オンパルス幅の中心が前記出力電圧指令の位相に対して複数の前記位相シフト量の各々進めた複数の第１ゲート信号および複数の前記位相シフト量の各々遅らせた複数の第２ゲート信号を生成するゲート信号生成部と、を備え、複数の前記第１ゲート信号と複数の第２ゲート信号とは、前記第１アームを構成する複数の前記単位変換器を駆動するゲート信号、前記第１アームと前記第２アームとを構成する複数の前記単位変換器は偶数、そして前記位相シフト量はゼロより大きく１８０°未満である。
A control device for a multi-stage converter according to an embodiment has a first arm constituted by a plurality of unit converters connected in series, one end of which is electrically connected to a DC terminal on a high potential side and the other end of which is electrically connected to an AC terminal via a first reactor, and a second arm constituted by a plurality of unit converters connected in series, one end of which is electrically connected to the AC terminal via a second reactor and the other end of which is electrically connected to a DC terminal on a low potential side, and each of the plurality of unit converters in the first arm and the second arm comprises an upper element and a lower element connected in series, and a capacitor having one end connected to a high potential side end of the upper element and the other end connected to a low potential side end of the lower element, and a connection point between the upper element and the lower element is connected to the high potential side DC terminal, a connection point between the lower element and the capacitor of the unit converter adjacent on the high potential side, or the second reactor, and a low potential side end of the lower element is connected to the low potential side DC terminal, A control device for controlling a multi-stage converter connected to a connection point with the lower element or to the first reactor, comprising: a modulation factor calculation unit that calculates a modulation factor using an output voltage command of the multi- stage converter and a DC voltage of the unit converter ; a phase shift amount generation unit that generates a plurality of phase shift amounts of gate signals that drive the upper elements of a plurality of the unit converters based on the modulation factor; and a gate signal generation unit that generates a plurality of first gate signals and a plurality of second gate signals, each of which has the same on-pulse width and off-pulse width and whose center of the on-pulse width is advanced by a plurality of the phase shift amounts relative to the phase of the output voltage command, based on an output voltage fundamental frequency, wherein the plurality of first gate signals and the plurality of second gate signals are gate signals that drive the plurality of unit converters that constitute the first arm, the number of unit converters that constitute the first arm and the second arm is an even number, and the phase shift amount is greater than zero and less than 180°.
以下、実施形態の多段変換器の制御装置について、図面を参照して説明する。
図１は、第１実施形態の多段変換器の制御装置を概略的に示す図である。
本実施形態の制御装置は、例えば、半導体素子とコンデンサとを備えたチョッパセルを単位変換器とした多段変換器１０の動作を制御する制御装置である。
Hereinafter, a control device for a multistage converter according to an embodiment will be described with reference to the drawings.
FIG. 1 is a diagram illustrating a control device for a multistage converter according to a first embodiment.
The control device of the present embodiment is a control device that controls the operation of a multi-stage converter 10 in which a chopper cell including a semiconductor element and a capacitor serves as a unit converter.
多段変換器１０は、直流電源（図示せず）と交流負荷との間に介在し、直流電力を三相交流電力に変換して交流負荷に供給もしくは三相交流電力を直流電力に変換して直流部へ電力供給が可能である。多段変換器１０は、直流電源と接続する直流端子Ｐ、Ｎと、交流ラインＵＬ、ＶＬ、ＷＬを介して交流負荷と電気的に接続する交流端子Ｕ、Ｖ、Ｗと、直流電源に対して並列に接続した３つのレグ４と、電圧センサＳＶと、を備えている。３つのレグ４のそれぞれは、上アーム（第１アーム）３Ｐと下アーム（第２アーム）３Ｎとを備えている。 The multi-stage converter 10 is interposed between a DC power source (not shown) and an AC load, and can convert DC power into three-phase AC power to supply to the AC load, or convert three-phase AC power into DC power to supply to the DC section. The multi-stage converter 10 includes DC terminals P and N that connect to the DC power source, AC terminals U, V, and W that electrically connect to the AC load via AC lines UL, VL, and WL, three legs 4 connected in parallel to the DC power source, and a voltage sensor SV. Each of the three legs 4 includes an upper arm (first arm) 3P and a lower arm (second arm) 3N.
上アーム３Ｐのそれぞれは、高電位側の直流端子Ｐと電気的に接続した高電位側の直流リンクＰＬと、３つの交流ラインＵＬ、ＶＬ、ＷＬのいずれかとの間に電気的に接続している。下アーム３Ｎは、低電位側の直流端子Ｎと電気的に接続した低電位側の直流リンクＮＬと、３つの交流ラインＵＬ、ＶＬ、ＷＬのいずれかとの間に電気的に接続している。上アーム３Ｐと下アーム３Ｎとのそれぞれは、複数のチョッパセル１とバッファリアクトル２とを備えている。 Each of the upper arms 3P is electrically connected between a high-potential side DC link PL electrically connected to a high-potential side DC terminal P and one of the three AC lines UL, VL, WL. The lower arm 3N is electrically connected between a low-potential side DC link NL electrically connected to a low-potential side DC terminal N and one of the three AC lines UL, VL, WL. Each of the upper arm 3P and the lower arm 3N includes a plurality of chopper cells 1 and a buffer reactor 2.
本実施形態では、上アーム３Ｐにおいて、ｎ段のチョッパセル１Ｐ１～１Ｐｎが電気的に直列に接続し、バッファリアクトル（第１リアクトル）２Ｐがチョッパセル１Ｐ１～１Ｐｎと交流ラインＵＬ、ＶＬ、ＷＬとの間に電気的に接続している。 In this embodiment, in the upper arm 3P, n stages of chopper cells 1P1 to 1Pn are electrically connected in series, and a buffer reactor (first reactor) 2P is electrically connected between the chopper cells 1P1 to 1Pn and the AC lines UL, VL, and WL.
下アーム３Ｎにおいて、ｎ段のチョッパセル１Ｎ１～１Ｎｎが直列に接続し、バッファリアクトル（第２リアクトル）２Ｎがチョッパセル１Ｎ１～１Ｎｎと交流ラインＵＬ、ＶＬ、ＷＬとの間に電気的に接続している。
なお、ｎは偶数の正の整数であって、上アーム３Ｐと下アーム３Ｎとは、少なくとも２段のチョッパセル回路を直列接続した構成であればよく、段数の上限を特に設ける必要はない。
In the lower arm 3N, n stages of chopper cells 1N1 to 1Nn are connected in series, and a buffer reactor (second reactor) 2N is electrically connected between the chopper cells 1N1 to 1Nn and the AC lines UL, VL, and WL.
Note that n is an even positive integer, and the upper arm 3P and the lower arm 3N need only be configured with at least two stages of chopper cell circuits connected in series, and there is no need to set an upper limit on the number of stages.
以下の説明おいて、上アーム３Ｐと下アーム３Ｎとのそれぞれにおいて、交流ラインＵＬ、ＶＬ、ＷＬと接続したチョッパセルを１段目とし、直流リンクＰＬ、ＮＬと接続したチョッパセルをｎ段目とし、直列に接続したｎ段の単位変換器が並んだ順に１段目、２段目、…ｎ段目と称する。 In the following description, in each of the upper arm 3P and the lower arm 3N, the chopper cell connected to the AC lines UL, VL, and WL is referred to as the first stage, the chopper cell connected to the DC links PL and NL is referred to as the nth stage, and the n stages of unit converters connected in series are referred to as the first stage, second stage, ..., nth stage in order.
チョッパセル１Ｐ１～１Ｐｎ、１Ｎ１～１Ｎｎは、それぞれ同じ構成である。チョッパセル１Ｐ１～１Ｐｎ、１Ｎ１～１Ｎｎそれぞれは、２つの半導体素子Ｓ１、Ｓ２と、キャパシタＣＰ１～ＣＰｎ、ＣＮ１～ＣＮｎと、を備えている。チョッパセル１Ｐ１～１Ｐｎ、１Ｎ１～１Ｎｎそれぞれにおいて、２つの半導体素子Ｓ１、Ｓ２は直列に接続し、キャパシタＣＰ１～ＣＰｎ、ＣＮ１～ＣＮｎは、２つの半導体素子Ｓ１、Ｓ２と並列に接続している。 The chopper cells 1P1 to 1Pn and 1N1 to 1Nn have the same configuration. Each of the chopper cells 1P1 to 1Pn and 1N1 to 1Nn includes two semiconductor elements S1 and S2 and capacitors CP1 to CPn and CN1 to CNn . In each of the chopper cells 1P1 to 1Pn and 1N1 to 1Nn , the two semiconductor elements S1 and S2 are connected in series, and the capacitors CP1 to CPn and CN1 to CNn are connected in parallel to the two semiconductor elements S1 and S2.
また、チョッパセル１Ｐ１～１Ｐｎ、１Ｎ１～１Ｎｎは、キャパシタＣＰ１～ＣＰｎ、ＣＮ１～ＣＮｎの電圧ＶＣＰ１～ＶＣＰｎ、ＶＣＮ１～ＶＣＮｎおよび直流電圧ＶＤＣを検出する少なくとも１つの電圧センサ（図示せず）を備え、キャパシタＣＰ１～ＣＰｎ、ＣＮ１～ＣＮｎの電圧ＶＣＰ１～ＶＣＰｎ、ＶＣＮ１～ＶＣＮｎおよび直流電圧ＶＤＣの検出値を制御装置２０へ供給するように構成されてもよい。 In addition, chopper cells 1 P1 to 1 Pn , 1 N1 to 1 Nn may be provided with at least one voltage sensor (not shown) that detects the voltages V CP1 to V CPn , V CN1 to V CNn and DC voltage V DC of capacitors C P1 to C Pn , C N1 to C Nn , and may be configured to supply the detected values of the voltages V CP1 to V CPn , V CN1 to V CNn and DC voltage V DC of capacitors C P1 to C Pn, C N1 to C Nn to control device 20.
２つの半導体素子Ｓ１、Ｓ２は、それぞれ、ＩＧＢＴ（絶縁ゲートバイポーラトランジスタ：Insulated Gate Bipolar Transistor）やＭＯＳＦＥＴ（半導体電界効果トランジスタ：metal-oxide semiconductor field-effect transistor）などの半導体スイッチにダイオードを逆並列接続した構成、若しくは、ＭＯＳＦＥＴ（半導体電界効果トランジスタ：metal-oxide semiconductor field-effect transistor）を備える。 The two semiconductor elements S1 and S2 each have a configuration in which a diode is connected in inverse parallel to a semiconductor switch such as an IGBT (insulated gate bipolar transistor) or a MOSFET (metal-oxide semiconductor field-effect transistor), or a MOSFET (metal-oxide semiconductor field-effect transistor).
チョッパセル１Ｐ１～１Ｐｎ、１Ｎ１～１Ｎｎそれぞれにおいて、半導体素子（上側素子）Ｓ１と半導体素子（下側素子）Ｓ２とはそれぞれ反転動作をし、半導体素子Ｓ１がオンしているときに半導体素子Ｓ２はオフ動作となる。ただし、半導体素子Ｓ１と半導体素子Ｓ２との短絡を防止するため、半導体素子Ｓ１と半導体素子Ｓ２との両方をオフにするデットタイム期間を設けるときには、半導体素子Ｓ１と半導体素子Ｓ２とが同時にオフとなるようにデットタイム期間が設けられる。
電圧センサＳＶは、高電位側の直流リンクＰＬと低電位側の直流リンクＮＬとの間の電圧（直流電源電圧）ＶＰＮを検出し、検出値を制御装置２０へ出力する。
In each of the chopper cells 1P1 to 1Pn and 1N1 to 1Nn , the semiconductor element (upper element) S1 and the semiconductor element (lower element) S2 perform inverted operation, and when the semiconductor element S1 is on, the semiconductor element S2 is turned off. However, when a dead time period is provided in which both the semiconductor elements S1 and S2 are turned off in order to prevent a short circuit between the semiconductor elements S1 and S2, the dead time period is provided so that the semiconductor elements S1 and S2 are turned off simultaneously.
The voltage sensor SV detects a voltage (DC power supply voltage) VPN between the high potential side DC link PL and the low potential side DC link NL, and outputs the detected value to the control device 20.
制御装置２０は、変調率演算部２１と、位相シフト量生成部２２と、ゲート信号生成部２３と、を備えている。
本実施形態では、制御装置２０は多段変換器１０をワンパルス駆動にて動作させる。ワンパルス駆動では、チョッパセル１Ｐ１～１Ｐｎ、１Ｎ１～１Ｎｎの半導体素子Ｓ１、Ｓ２を出力電圧基本波周波数にて駆動する。ワンパルス駆動ではＰＷＭ駆動と比較しスイッチング周波数を抑制できるためスイッチングするときに発生する損失を低減することができ、変換器損失の低減、冷却器の削減効果が期待できる。
The control device 20 includes a modulation factor calculation section 21 , a phase shift amount generation section 22 , and a gate signal generation section 23 .
In this embodiment, the control device 20 operates the multistage converter 10 in one-pulse drive. In one-pulse drive, the semiconductor elements S1 and S2 of the chopper cells 1P1 to 1Pn and 1N1 to 1Nn are driven at the output voltage fundamental frequency. In one-pulse drive, the switching frequency can be suppressed compared to PWM drive, so that the loss generated during switching can be reduced, and the reduction of converter loss and the reduction of the cooling device can be expected.
制御装置２０は、チョッパセル１Ｐ１～１Ｐｎ、１Ｎ１～１Ｎｎの半導体素子Ｓ１、Ｓ２を、オンとオフとの時間幅が同一（Ｄｕｔｙ５０％）であるスイッチングパルス（ゲート信号）で駆動し、そのゲート信号の位相を上アーム３Ｐのチョッパセル１Ｐ１～１Ｐｎ間、下アーム３Ｎのチョッパセル１Ｎ１～１Ｎｎ間で調整することにより出力電圧を調整する。 The control device 20 drives the semiconductor elements S1, S2 of the chopper cells 1P1 to 1Pn and 1N1 to 1Nn with switching pulses (gate signals) whose on and off time widths are the same (Duty 50%), and adjusts the output voltage by adjusting the phase of the gate signal between the chopper cells 1P1 to 1Pn of the upper arm 3P and between the chopper cells 1N1 to 1Nn of the lower arm 3N.
具体的には、制御装置２０は、多段変換器１０全体の出力電圧位相（０°の位置）に対して位相シフト量進ませた信号と、位相シフト量遅らせた信号とが同数となるように、上アーム３Ｐの複数のチョッパセル１Ｐ１～１Ｐｎの上側（高電位側）の半導体素子Ｓ１を駆動する複数のゲート信号の位相を調整する。 Specifically, the control device 20 adjusts the phases of multiple gate signals that drive the upper (high potential side) semiconductor elements S1 of the multiple chopper cells 1P1 to 1Pn of the upper arm 3P so that there are the same number of signals that have an advanced phase shift amount relative to the output voltage phase (0° position) of the entire multi-stage converter 10 and signals that have a delayed phase shift amount.
このとき、位相調整量（位相シフト量）は、出力電圧位相（０°の位置）に対して位相シフト量進ませた信号のオンパルス幅の中心と、遅らせた信号のオンパルス幅の中心とが、出力電圧に対して進み遅れ同一位相量（０°に対して対称な波形）になるよう位相操作を行う。 At this time, the phase adjustment amount (phase shift amount) is adjusted so that the center of the on-pulse width of the signal advanced by the phase shift amount relative to the output voltage phase (0° position) and the center of the on-pulse width of the delayed signal are advanced and delayed by the same phase amount relative to the output voltage (waveforms symmetrical with respect to 0°).
また、制御装置２０は、下アーム３Ｎの複数のチョッパセル１Ｎ１～１Ｎｎの上側の半導体素子Ｓ１を駆動する複数のゲート信号は、上アーム３Ｐの複数のチョッパセル１Ｐ１～１Ｐｎの上側の半導体素子Ｓ１を駆動するゲート信号の位相を１８０°ずらしたものとする。 In addition, the control device 20 shifts the phase of the multiple gate signals driving the upper semiconductor elements S1 of the multiple chopper cells 1N1 to 1Nn of the lower arm 3N by 180° from the phase of the gate signals driving the upper semiconductor elements S1 of the multiple chopper cells 1P1 to 1Pn of the upper arm 3P.
すなわち、制御装置２０は、多段変換器１０全体の出力電圧位相（０°の位置）に対して位相シフト量進ませた信号と、位相シフト量遅らせた信号とが同数となるように、下アーム３Ｎの複数のチョッパセル１Ｎ１～１Ｎｎの上側（高電位側）の半導体素子Ｓ１を駆動する複数のゲート信号の位相を調整する。 That is, the control device 20 adjusts the phases of multiple gate signals that drive the upper (high potential side) semiconductor elements S1 of the multiple chopper cells 1N1 to 1Nn of the lower arm 3N so that there are the same number of signals that are advanced by a phase shift amount relative to the output voltage phase (0° position) of the entire multi-stage converter 10 and signals that are delayed by a phase shift amount.
変調率演算部２１は、各チョッパの直流電圧Ｖ
ＤＣ と、電圧指令値Ｖ＊とを用いて、変調率Ｍを演算する。変調率演算部２１にて演算された変調率Ｍは、位相シフト量生成部２２に入力される。変調率演算部２１は、例えば下記（１）式を用いて、上アーム３Ｐ変調率Ｍを演算する。
The modulation factor calculation unit 21 calculates the modulation factor M using the DC voltage VDC of each chopper and the voltage command value V * . The modulation factor M calculated by the modulation factor calculation unit 21 is input to the phase shift amount generation unit 22. The modulation factor calculation unit 21 calculates the upper arm 3P modulation factor M using, for example, the following formula (1).
ここでは、アーム内のチョッパ段数と各チョッパの直流電圧との積と、電圧指令値Ｖ＊との比を変調率Ｍとして下記（１）式の通り定義する。
Ｍ＝（２＊Ｖ
＊ ）／（Ｎ＊ＶＤＣ） （１）
ただし、Ｎはアーム内のチョッパ段数、ＶＤＣは各チョッパの直流電圧とする。
Here, the ratio of the product of the number of chopper stages in an arm and the DC voltage of each chopper to the voltage command value V * is defined as a modulation factor M as shown in the following equation (1).
M = (2 * V * ) / (N * V DC ) (1)
Here, N is the number of chopper stages in an arm, and VDC is the DC voltage of each chopper.
位相シフト量生成部２２は、入力された変調率Ｍに対応する位相シフト量α１～αn/2を出力する。なお、以下では、上アーム３Ｐが８段のチョッパセル１Ｐ１～１Ｐ８を備える場合について説明する。この場合、４つのチョッパセルの位相を進ませて、４つのチョッパセルの位相を遅らせて、４つの進み量と４つの遅れ量との絶対値が等しいものとすると、位相シフト量生成部２２は、４つの位相シフト量α１～α４を出力する。 The phase shift amount generation unit 22 outputs phase shift amounts α 1 to α n/2 corresponding to the input modulation factor M. In the following, a case will be described in which the upper arm 3P includes eight chopper cells 1 P1 to 1 P8 . In this case, if the phases of four chopper cells are advanced and the phases of four chopper cells are delayed and the absolute values of the four advance amounts and the four delay amounts are equal, the phase shift amount generation unit 22 outputs four phase shift amounts α 1 to α 4 .
絶対値が等しい進み量と遅れ量とにより位相をシフトしたときの位相シフト量αｎと、多段変換器の出力電圧の基本波振幅との関係を次式に示す。ただし、ＶＤＣは、各チョッパセルの直流電圧であり、ここでは複数のチョッパセルの直流電圧は等しいものと仮定する。
８段構成の上アーム３Ｐの場合の基本波振幅量は下記（２）式で表される。なお、ｍは上アーム３Ｐを構成するチョッパセルの段数の１／２となる。
The relationship between the amount of phase shift αn when the phase is shifted by a lead amount and a lag amount with equal absolute values and the fundamental wave amplitude of the output voltage of the multistage converter is shown in the following equation: where VDC is the DC voltage of each chopper cell, and it is assumed here that the DC voltages of the multiple chopper cells are equal.
The fundamental wave amplitude amount in the case of the upper arm 3P having eight stages is expressed by the following formula (2): where m is half the number of stages of chopper cells constituting the upper arm 3P.
また、ｋ次の高調波電圧は下記（３）式により求められる。
例えば、各アーム８段の場合、出力電圧基本波と、３次、５次、７次の３（＝Ｎ／２－１）つの高調波に関する式を用いた４つの方程式の連立方程式によれば、４つの位相シフト量α１～α４を連立方程式から求めることができる。
例えば下記式のように、基本波振幅と、３次高調波振幅と、５次高調波振幅と、７次高調波振幅とをそれぞれゼロとする方程式を用いた下記連立方程式により、４つの位相シフト量α１～α４を算出することができる。
For example, in the case of eight arms, four phase shift amounts α 1 to α 4 can be obtained from a simultaneous equation of four equations using equations relating to the output voltage fundamental wave and three (=N/2-1) harmonics of third, fifth , and seventh orders.
For example, the four phase shift amounts α 1 to α 4 can be calculated by the following simultaneous equations using equations in which the fundamental wave amplitude, the third harmonic amplitude, the fifth harmonic amplitude, and the seventh harmonic amplitude are each set to zero , as shown in the following equations.
図２は、変調率と位相シフト量との関係の一例を示す図である。なお、ここでは、位相シフト量α１～α４はα１＜α２＜α３＜α４であるものとしている。ここでは、高調波電流の総和（３次～３９次高調波の和）が最小となるαの組み合わせを求めた結果の一例を示している。 2 is a diagram showing an example of the relationship between the modulation rate and the phase shift amount. Here, the phase shift amounts α 1 to α 4 are assumed to be α 1 < α 2 < α 3 < α 4. Here, an example of the result of determining a combination of α that minimizes the sum of the harmonic currents (the sum of the 3rd to 39th harmonics) is shown.
例えば、図２の変調率Ｍと位相シフト量α１～α４との関係は、変調率Ｍ（若しくは出力電圧振幅Ｖ１）を制約条件として、それを満たす位相シフト量α１～α４の複数の組み合わせの中から高調波量が最小になる位相シフト量α１～α４を最適化アルゴリズムで抽出した値である。また、非線形連立方程式の解から位相シフト量α１～α４を算出することも可能である。なお、本実施形態では、位相シフト量α１～α４はゼロより大きく１８０°未満の範囲とする。 For example, the relationship between the modulation factor M and the phase shift amounts α1 to α4 in Fig . 2 is a value obtained by extracting, using an optimization algorithm, the phase shift amounts α1 to α4 that minimize the amount of harmonics from among multiple combinations of the phase shift amounts α1 to α4 that satisfy the constraint of the modulation factor M (or the output voltage amplitude V1). It is also possible to calculate the phase shift amounts α1 to α4 from the solution of a nonlinear simultaneous equation. In this embodiment, the phase shift amounts α1 to α4 are in the range greater than zero and less than 180°.
位相シフト量生成部２２は、上記（３）式および（４）式を用いて予め演算された位相シフト量α１～α４を利用して、例えば、変調率Ｍに対応する位相シフト量α１～α４のテーブルを備えていてもよい。 The phase shift amount generating section 22 may be provided with, for example, a table of phase shift amounts α 1 to α 4 corresponding to modulation factors M, using the phase shift amounts α 1 to α 4 calculated in advance using the above equations (3) and (4) .
ゲート信号生成部２３は、位相シフト量生成部２２から位相シフト量α１～α４を受信し、上アーム３Ｐの８つのチョッパセル１Ｐ１～１Ｐ８に供給されるゲート信号と、下アーム３Ｎのチョッパセル１Ｎ１～１Ｎ８に供給されるゲート信号とを生成する。本実施形態では、ゲート信号のオン時間とオフ時間とは等しく（Ｄｕｔｙ５０％であり）、それぞれ位相が１８０°の期間とする。 The gate signal generator 23 receives the phase shift amounts α 1 to α 4 from the phase shift amount generator 22, and generates gate signals to be supplied to the eight chopper cells 1 P1 to 1 P8 of the upper arm 3 P and gate signals to be supplied to the chopper cells 1 N1 to 1 N8 of the lower arm 3 N. In this embodiment, the on and off times of the gate signals are equal (Duty 50%), and each has a phase period of 180°.
図３は、上アームのチョッパセルの上側の半導体素子のゲート信号と上アームの出力電圧との一例を示す図である。
ゲート信号生成部２３は、上アーム３Ｐのチョッパセル１Ｐ１～１Ｐ８の８つの上側の半導体素子Ｓ１のゲート信号のうち、４つゲート信号（第１ゲート信号）をオンパルス幅の中心が電圧指令の位相（０°の位置）よりも位相シフト量α１～α４遅らせた信号とし、４つのゲート信号（第２ゲート信号）をオンパルス幅の中心が電圧指令の位相（０°の位置）よりも位相シフト量α１～α４進ませた信号とする。
FIG. 3 is a diagram showing an example of the gate signal of the upper semiconductor element of the upper arm chopper cell and the output voltage of the upper arm.
The gate signal generating unit 23 generates four gate signals (first gate signals) of the eight upper semiconductor elements S1 of the chopper cells 1P1 to 1P8 of the upper arm 3P as signals in which the center of the on-pulse width is delayed by phase shift amounts α1 to α4 from the phase of the voltage command (0° position), and generates four gate signals (second gate signals) as signals in which the center of the on-pulse width is advanced by phase shift amounts α1 to α4 from the phase of the voltage command (0° position).
上記のように、ゲート信号生成部２３は、電圧指令の位相を基準として位相シフト量α１～α４の位相を調整して、上アーム３Ｐのチョッパセル１Ｐ１～１Ｐ８の８つの上側の半導体素子Ｓ１のゲート信号を生成する。ゲート信号生成部２３は、チョッパセル１Ｐ１～１Ｐ８の８つの上側の半導体素子Ｓ１のゲート信号を反転して、下側の半導体素子Ｓ２の８つのゲート信号を生成し、上アーム３Ｐのチョッパセル１Ｐ１～１Ｐ８へ供給する１６のゲート信号を生成する。 As described above, the gate signal generating unit 23 adjusts the phases of the phase shift amounts α1 to α4 based on the phase of the voltage command to generate gate signals for the eight upper semiconductor elements S1 of the chopper cells 1P1 to 1P8 of the upper arm 3P. The gate signal generating unit 23 inverts the gate signals for the eight upper semiconductor elements S1 of the chopper cells 1P1 to 1P8 to generate eight gate signals for the lower semiconductor element S2, and generates 16 gate signals to be supplied to the chopper cells 1P1 to 1P8 of the upper arm 3P.
ゲート信号生成部２３は、上アーム３Ｐのチョッパセル１Ｐ１～１Ｐ８それぞれにおいて、上側の半導体素子Ｓ１と下側の半導体素子Ｓ２とに互いに反転した関係のゲート信号が供給されるように、生成したゲート信号を複数のチョッパセル１Ｐ１～１Ｐ８へ出力する。なお、本実施形態では、ゲート信号生成部２３は、図３に示す８つのゲート信号を、チョッパセル１Ｐ１～１Ｐ８のいずれに割り当ててもよい。 The gate signal generating unit 23 outputs the generated gate signals to the chopper cells 1P1 to 1P8 so that gate signals inverted to each other are supplied to the upper semiconductor element S1 and the lower semiconductor element S2 in each of the chopper cells 1P1 to 1P8 of the upper arm 3P. Note that in this embodiment, the gate signal generating unit 23 may assign the eight gate signals shown in FIG. 3 to any of the chopper cells 1P1 to 1P8 .
図４は、下アームのチョッパセルの上側の半導体素子のゲート信号と下アームの出力電圧との一例を示す図である。
ゲート信号生成部２３は、図３に示す上アーム３Ｐの８つのチョッパセル１Ｐ１～１Ｐ８の上側の半導体素子Ｓ１の８つのゲート信号を反転して、下アーム３Ｎの８つのチョッパセル１Ｎ１～１Ｎ８の上側の半導体素子Ｓ１を駆動するゲート信号を生成する。
すなわち、下アーム３Ｎのチョッパセル１Ｎ１～１Ｎ８の８つの上側の半導体素子Ｓ１のゲート信号のうち、４つゲート信号はオフパルス幅の中心を電圧指令の位相（０°の位置）よりも位相シフト量α１～α４遅らせたものであり、４つのゲート信号はオフパルス幅の中心を電圧指令の位相（０°の位置）よりも位相シフト量α１～α４進ませたものである。
FIG. 4 is a diagram showing an example of the gate signal of the upper semiconductor element of the chopper cell of the lower arm and the output voltage of the lower arm.
The gate signal generating unit 23 inverts eight gate signals of the upper semiconductor elements S1 of the eight chopper cells 1P1 to 1P8 of the upper arm 3P shown in FIG. 3, and generates gate signals that drive the upper semiconductor elements S1 of the eight chopper cells 1N1 to 1N8 of the lower arm 3N.
That is, of the gate signals of the eight upper semiconductor elements S1 of chopper cells 1N1 to 1N8 of the lower arm 3N, four gate signals have the center of the off-pulse width delayed by phase shift amounts α1 to α4 from the phase of the voltage command (0° position), and four gate signals have the center of the off-pulse width advanced by phase shift amounts α1 to α4 from the phase of the voltage command (0° position).
ゲート信号生成部２３は、チョッパセル１Ｎ１～１Ｎ８の８つの上側の半導体素子Ｓ１のゲート信号を反転して、下側の半導体素子Ｓ２の８つのゲート信号を生成し、下アーム３Ｎのチョッパセル１Ｐ１～１Ｐ８へ供給する１６のゲート信号とする。
ゲート信号生成部２３は、下アーム３Ｎのチョッパセル１Ｎ１～１Ｎ８それぞれにおいて、上側の半導体素子Ｓ１と下側の半導体素子Ｓ２とに互いに反転した関係のゲート信号が供給されるように、生成したゲート信号をチョッパセル１Ｎ１～１Ｎ８へ出力する。なお、本実施形態では、ゲート信号生成部２３は、図４に示す８つのゲート信号を、チョッパセル１Ｎ１～１Ｎ８のいずれに割り当ててもよい。
The gate signal generating unit 23 inverts the gate signals of the eight upper semiconductor elements S1 of the chopper cells 1N1 to 1N8 to generate eight gate signals of the lower semiconductor elements S2, resulting in 16 gate signals to be supplied to the chopper cells 1P1 to 1P8 of the lower arm 3N.
The gate signal generating unit 23 outputs the generated gate signals to the chopper cells 1N1 to 1N8 so that gate signals inverted to each other are supplied to the upper semiconductor element S1 and the lower semiconductor element S2 in each of the chopper cells 1N1 to 1N8 of the lower arm 3N. Note that in this embodiment, the gate signal generating unit 23 may assign the eight gate signals shown in FIG. 4 to any of the chopper cells 1N1 to 1N8 .
上記のように、本実施形態では、上アーム３Ｐを構成するチョッパセル１Ｐ１～１Ｐｎそれぞれについて、チョッパセル１Ｐ１～１Ｐｎの上側の半導体素子Ｓ１の位相を出力電圧位相に対して進ませるチョッパセルと遅らせるチョッパセルとが同数となるように、各チョッパセル１Ｐ１～１Ｐｎの上側の半導体素子のゲート信号の位相を調整している。 As described above, in this embodiment, for each of the chopper cells 1P1 to 1Pn constituting the upper arm 3P, the phase of the gate signal of the semiconductor element S1 above the chopper cells 1P1 to 1Pn is adjusted so that the number of chopper cells that advance the phase of the semiconductor element S1 above the chopper cells 1P1 to 1Pn with respect to the output voltage phase is equal to the number of chopper cells that delay the phase.
また、下アーム３Ｎを駆動するゲート信号は上アーム３Ｐを駆動するゲート信号を反転させたものであり、下アーム３Ｎを構成するチョッパセル１Ｎ１～１Ｎｎそれぞれについて、チョッパセル１Ｎ１～１Ｎｎの上側の半導体素子Ｓ１の位相を出力電圧位相に対して進ませるチョッパセルと遅らせるチョッパセルとが同数となる。 In addition, the gate signal that drives the lower arm 3N is an inversion of the gate signal that drives the upper arm 3P, and for each of the chopper cells 1N1 to 1Nn that constitute the lower arm 3N, there are the same number of chopper cells that advance the phase of the semiconductor element S1 above the chopper cells 1N1 to 1Nn with respect to the output voltage phase and chopper cells that delay it.
これにより、例えば多段変換器１０の変調率が変化しても全てのチョッパセル１Ｐ１～１Ｐｎ、１Ｎ１～１Ｎｎの半導体素子Ｓ１、Ｓ２がスイッチングし、各段のチョッパセルをワンパルス駆動にて動作させても、多段変換器１０の出力電圧の総和は疑似的にＰＷＭ変調のような波形となり、低次高調波の発生が抑制できる。 As a result, even if the modulation rate of the multi-stage converter 10 changes, the semiconductor elements S1 and S2 of all chopper cells 1P1 to 1Pn , 1N1 to 1Nn are switched, and even if the chopper cells of each stage are operated by one-pulse drive, the sum of the output voltages of the multi-stage converter 10 has a waveform that is similar to that of a PWM modulation, and the generation of low-order harmonics can be suppressed.
上記のように、本実施形態の多段変換器の制御装置によれば、出力電圧の大小にかかわらず全ての単位変換器を電圧出力に活用することができ、高調波の発生を抑制し、電圧歪を低減するワンパルス駆動を実現可能である。 As described above, the control device for the multi-stage converter of this embodiment can utilize all unit converters for voltage output regardless of the magnitude of the output voltage, and can realize one-pulse drive that suppresses the generation of harmonics and reduces voltage distortion.
本発明のいくつかの実施形態を説明したが、これらの実施形態は、例として提示したものであり、発明の範囲を限定することは意図していない。これら新規な実施形態は、その他の様々な形態で実施されることが可能であり、発明の要旨を逸脱しない範囲で、種々の省略、置き換え、変更を行うことができる。これら実施形態やその変形は、発明の範囲や要旨に含まれるとともに、特許請求の範囲に記載された発明とその均等の範囲に含まれる。 Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the gist of the invention. These embodiments and their modifications are included in the scope and gist of the invention, and are included in the scope of the invention and its equivalents described in the claims.
例えば、上述の実施形態において、制御装置２０は、チョッパセル１Ｐ１～１Ｐ８それぞれの上側半導体素子Ｓ１のゲート信号のオンパルス幅を調整することにより、上アーム電圧ＶＰの直流電圧成分を調整し、上アームと下アームとに共通して流れる循環電流ｉcirを制御することができる。 For example, in the above-described embodiment, the control device 20 adjusts the on-pulse width of the gate signal of the upper semiconductor element S1 of each of the chopper cells 1P1 to 1P8 , thereby adjusting the DC voltage component of the upper arm voltage VP and controlling the circulating current iCir that flows commonly to the upper arm and lower arm.
ここで多直列チョッパから構成される上アーム（第１アーム）の電流をｉＰ、下アーム（第２アーム）の電流をｉＮとすると循環電流ｉｃｉｒは次式で表せる。
ｉｃｉｒ＝（１／２）＊（ｉＰ＋ｉＮ）
ただしｉＰは直流端子Ｐから交流端子方向へ流れる向きを正とし、ｉＮは交流端子から直流端子Ｎへ流れる向きを正とする。
循環電流ｉｃｉｒは直流端子ＰＮに対して各相の上下アーム間に共通して流れる電流成分と定義するため、各相それぞれ個別に循環電流ｉｃｉｒが流れる。そこで、循環電流の制御については、単一の相について説明する。
Here, if the current in the upper arm (first arm) configured by the multiple series choppers is i P and the current in the lower arm (second arm) is i N , the circulating current i cir can be expressed by the following equation.
i cir = (1/2) * (i P + i N )
Here, the direction of i P flowing from DC terminal P to AC terminal is positive, and the direction of i N flowing from AC terminal to DC terminal N is positive.
Since the circulating current i cir is defined as a current component that flows commonly between the upper and lower arms of each phase with respect to the DC terminal PN, the circulating current i cir flows individually in each phase. Therefore, the control of the circulating current will be described for a single phase.
図５は、単一相のＭＭＣ回路における循環電流の制御の一例について説明するための図である。
図５に単一相のＭＭＣ等価回路を示す。なお、ここで示す等価回路では、第１アームおよび第２アームを上下アーム電圧ＶＰ、ＶＮとして、電圧源として置き換えている。
上下アームのそれぞれは、Ｄｕｔｙ５０％のゲート信号にて駆動されたチョッパセルを多直列接続して構成されるため、上下アームの電圧ＶＰ、ＶＮには次式で示される直流電圧成分ＶＰＤＣ、ＶＮＤＣがそれぞれ含まれる。
ＶＰＤＣ＝ＶＮＤＣ＝０．５＊Ｎ＊ＶＤＣ
ただし、Ｎはアーム内のチョッパ段数、ＶＤＣは各チョッパの直流電圧を示す。
FIG. 5 is a diagram for explaining an example of control of circulating current in a single-phase MMC circuit.
An equivalent circuit of a single-phase MMC is shown in Fig. 5. In the equivalent circuit shown here, the first arm and the second arm are replaced as upper and lower arm voltages Vp and VN , respectively, as voltage sources.
Since each of the upper and lower arms is configured by connecting multiple chopper cells in series and driven by a gate signal with a duty of 50%, the voltages V P and V N of the upper and lower arms respectively contain DC voltage components V PDC and V NDC expressed by the following equations.
V PDC = V NDC = 0.5 * N * V DC
Here, N is the number of chopper stages in an arm, and V DC is the DC voltage of each chopper.
また、上下アームの電圧ＶＰ、ＶＮには、上記直流電圧成分ＶＰＤＣ、ＶＮＤＣに加えて、前述した変調率に応じた交流電圧成分が含まれるが、上アームの交流成分については出力電圧指令と同位相であり、下アームの交流電圧成分については逆位相となる。
そこで、循環電流ｉｃｉｒに着目した図５の直流端子ＰＮと上下アームを介した閉回路について考えると、上下アームに含まれる交流電圧成分は逆位相となりそれぞれ打消し合うため、循環電流ｉｃｉｒに対して影響する電圧成分は、直流端子間電圧ＶＰＮと直流電圧成分ＶＰＤＣおよび直流電圧成分ＶＮＤＣとなることがわかる。よって循環電流ｉｃｉｒは次式で示される。
ｉｃｉｒ＝（ＶＰＮ－（ＶＰＤＣ＋ＶＮＤＣ））／ｓ２ｌ
ここでsはラプラス演算子、lはバッファリアクトルインダクタンス値とする。
Furthermore, the upper and lower arm voltages V P , V N contain, in addition to the DC voltage components V PDC , V NDC , an AC voltage component corresponding to the above-mentioned modulation rate, but the AC component of the upper arm is in phase with the output voltage command, and the AC voltage component of the lower arm is in opposite phase.
5, the AC voltage components in the upper and lower arms are in opposite phase and cancel each other out, so it can be seen that the voltage components that affect the circulating current i cir are the DC terminal voltage V PN , the DC voltage component V PDC , and the DC voltage component V NDC . Therefore, the circulating current i cir is expressed by the following equation.
i cir = (V PN - (V PDC + V NDC )) / s2l
Here, s is the Laplace operator and l is the buffer reactor inductance value.
上記の式の通り、循環電流ｉｃｉｒは上下アームそれぞれに設置する２つのバッファリアクトルに印加される電圧となる直流端子間電圧ＶＰＮと上アーム直流電圧成分および下アーム直流電圧成分の差の積分となることがわかる。
そのためＶＰＮに対して上下アームの直流電圧成分ＶＰＤＣおよび直流電圧成分ＶＮＤＣの量を操作することで循環電流ｉｃｉｒを制御できることになる。すなわち、制御装置２０は、循環電流検出値と循環電流指令との差分に応じてＰＩ補償器で得られる直流電圧操作量に応じて、上アームおよび下アームの各チョッパセルのゲート信号のＤｕｔｙを操作することで、電流制御が可能になる。
As shown in the above equation, it can be seen that the circulating current i cir is the integral of the difference between the DC terminal voltage V PN , which is the voltage applied to the two buffer reactors installed in the upper and lower arms, and the upper arm DC voltage component and the lower arm DC voltage component.
Therefore, the circulating current i cir can be controlled by manipulating the amounts of the DC voltage components V PDC and V NDC of the upper and lower arms with respect to V PN . That is, the control device 20 can control the current by manipulating the duty of the gate signals of the chopper cells of the upper and lower arms according to the DC voltage manipulation amount obtained by the PI compensator according to the difference between the circulating current detection value and the circulating current command.
例えば、直流端子間電圧ＶＰＮがＮ＊ＶＤＣと等しい場合、制御装置２０は、上下アームの複数のチョッパセルのＤｕｔｙを５０％とすることで、直流電圧成分ＶＰＤＣおよび直流電圧成分ＶＮＤＣを０．５＊Ｎ＊ＶＤＣとすることができる。このとき、制御装置２０は、上下アームの直流電圧成分の和（ＶＰＤＣ＋ＶＮＤＣ）と直流端子間電圧ＶＰＮとが等しくなるように制御し、循環電流ｉｃｉｒの変化を抑制することができる。
一方、制御装置２０は、上下アームの複数のチョッパセルのＤｕｔｙを５０％より小さい値にして、上下アームの直流電圧成分の和（ＶＰＤＣ＋ＶＮＤＣ）よりも直流端子間電圧ＶＰＮを大きくして、循環電流ｉｃｉｒは上昇させることができる。
また、制御装置２０は、上下アームの複数のチョッパセルのＤｕｔｙを５０％よりも大きい値にして、上下アームの直流電圧成分の和（ＶＰＤＣ＋ＶＮＤＣ）の方が直流端子間電圧ＶＰＮよりも大きくなるように制御し、循環電流ｉｃｉｒを下降させることができる。以上のように、制御装置２０は、上下アームの複数のチョッパセルのＤｕｔｙを操作することで循環電流ｉｃｉｒを制御することができる。
For example, when the DC inter-terminal voltage VPN is equal to N* VDC , the control device 20 can set the DC voltage components VPDC and VNDC to 0.5*N* VDC by setting the duty of the multiple chopper cells of the upper and lower arms to 50%. At this time, the control device 20 controls so that the sum of the DC voltage components of the upper and lower arms ( VPDC + VNDC ) is equal to the DC inter-terminal voltage VPN , thereby suppressing changes in the circulating current iCir .
On the other hand, the control device 20 can increase the circulating current i cir by setting the duty of the multiple chopper cells in the upper and lower arms to a value smaller than 50% and making the DC terminal voltage V PN greater than the sum of the DC voltage components of the upper and lower arms (V PDC + V NDC ).
Furthermore, the control device 20 can control the duties of the multiple chopper cells of the upper and lower arms to a value greater than 50% so that the sum of the DC voltage components of the upper and lower arms (V PDC +V NDC ) is greater than the DC terminal voltage V PN , thereby lowering the circulating current i CIR . As described above, the control device 20 can control the circulating current i CIR by manipulating the duties of the multiple chopper cells of the upper and lower arms.
１０…多段変換器、１Ｐ１～１Ｐ８、１Ｎ１～１Ｎ８…チョッパセル（単位変換器）、ＣＰ１～ＣＰｎ…キャパシタ、Ｓ１…上側の半導体素子（上側素子）、Ｓ２…下側の半導体素子（下側素子）、２、２Ｐ、２Ｎ…バッファリアクトル、３…アーム、３Ｐ…上アーム（第１アーム）、３Ｎ…下アーム（第２アーム）、４…レグ、２０…制御装置、２１…変調率演算部、２２…位相シフト量生成部、２３…ゲート信号生成部、α１～α４…位相シフト量、ＳＶ…電圧センサ、Ｐ…高電位側直流端子、Ｎ…低電位側直流端子、Ｕ、Ｖ、Ｗ…交流端子。 10...multistage converter, 1P1 to 1P8 , 1N1 to 1N8 ...chopper cells (unit converters), CP1 to CPn ...capacitors, S1...upper semiconductor element (upper element), S2...lower semiconductor element (lower element), 2, 2P, 2N...buffer reactors, 3...arm, 3P...upper arm (first arm), 3N...lower arm (second arm), 4...leg, 20...control device, 21...modulation factor calculation unit, 22...phase shift amount generation unit, 23...gate signal generation unit, α1 to α4 ...phase shift amount, SV...voltage sensor, P...high potential side DC terminal, N...low potential side DC terminal, U, V, W...AC terminals.
Claims (3)
前記多段変換器の出力電圧指令と、前記単位変換器の直流電圧と、を用いて、前記第１アームおよび前記第２アームの各々に含まれる複数の前記単位変換器の段数がＮであって、Ｎ段の前記単位変換器各々の直流電圧と出力基本波振幅との比である前記第１アームの変調率を、変調率＝（２＊出力基本波振幅）／（Ｎ＊各前記単位変換器の直流電圧）により演算する変調率演算部と、
前記変調率に基づいて、複数の前記単位変換器の前記上側素子を駆動するゲート信号の複数の位相シフト量を生成する位相シフト量生成部と、
出力電圧基本波周波数に基づき、オンパルス幅とオフパルス幅とが同一で、オンパルス幅の中心が前記出力電圧指令の位相に対して複数の前記位相シフト量の各々進めた複数の第１ゲート信号および複数の前記位相シフト量の各々遅らせた複数の第２ゲート信号を生成するゲート信号生成部であって、前記第１アームの複数の前記単位変換器のＮ個の前記上側素子のゲート信号のうち、Ｎ／２を前記第１ゲート信号とし、他のＮ／２を前記第２ゲート信号とし、前記第１アームの複数の前記単位変換器それぞれにおいて、前記上側素子と前記下側素子とに互いに反転したゲート信号が供給されるように前記第１アームの複数の前記単位変換器へゲート信号を出力し、前記第１アームのＮ個の前記上側素子のゲート信号を反転した信号を前記第２アームの複数の前記単位変換器の前記上側素子のゲート信号とし、前記第２アームの複数の前記単位変換器のそれぞれにおいて、前記上側素子と前記下側素子とに互いに反転したゲート信号が供給されるように前記第２アームの複数の前記単位変換器へゲート信号を出力する前記ゲート信号生成部と、を備え、
複数の前記第１ゲート信号と複数の第２ゲート信号とは、前記第１アームを構成する複数の前記単位変換器を駆動するゲート信号であり、
前記第１アームと前記第２アームとを構成する複数の前記単位変換器は偶数であり、
複数の前記位相シフト量はゼロより大きく１８０°未満である、
多段変換器の制御装置。 a first arm configured by connecting a plurality of unit converters in series, one end of which is electrically connected to a DC terminal on a high potential side and the other end of which is electrically connected to an AC terminal via a first reactor, and a second arm configured by connecting a plurality of unit converters in series, one end of which is electrically connected to the AC terminal via a second reactor and the other end of which is electrically connected to a DC terminal on a low potential side, each of the plurality of unit converters in the first arm and the second arm is configured by connecting an upper element and a lower element in series, a capacitor having one end connected to a low potential side end of the lower element and the other end connected to a low potential side end of the lower element, a connection point between the upper element and the lower element being connected to the high potential side DC terminal, a connection point between the lower element and the capacitor of the adjacent converter unit on the high potential side, or the second reactor, and a low potential side end of the lower element being connected to the low potential side DC terminal, a connection point between the upper element and the lower element of the adjacent converter unit on the low potential side, or the first reactor,
a modulation factor calculation unit that uses an output voltage command of the multi-stage converter and a DC voltage of the converter unit, the number of stages of the converter units included in each of the first arm and the second arm being N, and calculates a modulation factor of the first arm, which is a ratio of the DC voltage of each of the N stages of converter units to an output fundamental wave amplitude, by modulation factor = (2 * output fundamental wave amplitude) / (N * DC voltage of each converter unit);
a phase shift amount generating unit that generates a plurality of phase shift amounts of gate signals that drive the upper elements of the plurality of unit converters based on the modulation factor;
a gate signal generation unit that generates a plurality of first gate signals having the same on-pulse width and off-pulse width, and a plurality of second gate signals having a center of the on-pulse width advanced by each of the plurality of phase shift amounts with respect to a phase of the output voltage command, based on an output voltage fundamental frequency, wherein among the gate signals of the N upper elements of the plurality of unit converters in the first arm, N/2 are set as the first gate signals and the other N/2 are set as the second gate signals, and output gate signals to the plurality of unit converters in the first arm such that gate signals inverted from each other are supplied to the upper element and the lower element in each of the plurality of unit converters in the first arm, signals obtained by inverting the gate signals of the N upper elements of the first arm are set as gate signals of the upper elements of the plurality of unit converters in the second arm, and output gate signals to the plurality of unit converters in the second arm such that gate signals inverted from each other are supplied to the upper element and the lower element in each of the plurality of unit converters in the second arm,
the plurality of first gate signals and the plurality of second gate signals are gate signals for driving the plurality of unit converters constituting the first arm,
the number of the unit converters constituting the first arm and the second arm is an even number,
A plurality of the phase shift amounts are greater than zero and less than 180°.
Multi-stage converter control device.
複数の前記位相シフト量は、所望の出力電圧の基本波振幅を前記単位変換器の直流電圧と複数の前記位相シフト量とを用いて表した方程式と、前記単位変換器の直流電圧と複数の前記位相シフト量とを用いて表した前記多段変換器の出力電圧に含まれるＮ／２－１の高調波電圧の振幅をゼロとする方程式との連立方程式を満たす組み合わせを用いて求められる、請求項１記載の多段変換器の制御装置。 A control device for controlling the multi-stage converter including the first arm and the second arm each including N stages of the unit converter,
The control device for a multi-stage converter according to claim 1, wherein the multiple phase shift amounts are obtained using a combination that satisfies a simultaneous equation including an equation expressing a fundamental wave amplitude of a desired output voltage using the DC voltage of the unit converter and the multiple phase shift amounts, and an equation that sets the amplitude of a harmonic voltage of N/2-1 included in the output voltage of the multi-stage converter expressed using the DC voltage of the unit converter and the multiple phase shift amounts to zero.
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Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002233180A (en) | 2001-01-31 | 2002-08-16 | Toshiba Corp | Power converter |
| JP2011078213A (en) | 2009-09-30 | 2011-04-14 | Tokyo Institute Of Technology | Motor starting method |
| JP2014018028A (en) | 2012-07-11 | 2014-01-30 | Toshiba Corp | Semiconductor power conversion equipment |
| JP2016063687A (en) | 2014-09-19 | 2016-04-25 | 株式会社東芝 | Power conversion system |
| US20160380556A1 (en) | 2015-06-26 | 2016-12-29 | Board Of Trustees Of Michigan State University | System and method for optimizing fundamental frequency modulation for a cascaded multilevel inverter |
| WO2019150443A1 (en) | 2018-01-30 | 2019-08-08 | 三菱電機株式会社 | Serial multiplex inverter |
-
2018
- 2018-06-11 JP JP2018111399A patent/JP7500157B2/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002233180A (en) | 2001-01-31 | 2002-08-16 | Toshiba Corp | Power converter |
| JP2011078213A (en) | 2009-09-30 | 2011-04-14 | Tokyo Institute Of Technology | Motor starting method |
| JP2014018028A (en) | 2012-07-11 | 2014-01-30 | Toshiba Corp | Semiconductor power conversion equipment |
| JP2016063687A (en) | 2014-09-19 | 2016-04-25 | 株式会社東芝 | Power conversion system |
| US20160380556A1 (en) | 2015-06-26 | 2016-12-29 | Board Of Trustees Of Michigan State University | System and method for optimizing fundamental frequency modulation for a cascaded multilevel inverter |
| WO2019150443A1 (en) | 2018-01-30 | 2019-08-08 | 三菱電機株式会社 | Serial multiplex inverter |
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