JP7457886B2 - Multilayer varistor and method for manufacturing same - Google Patents
Multilayer varistor and method for manufacturing same Download PDFInfo
- Publication number
- JP7457886B2 JP7457886B2 JP2020065454A JP2020065454A JP7457886B2 JP 7457886 B2 JP7457886 B2 JP 7457886B2 JP 2020065454 A JP2020065454 A JP 2020065454A JP 2020065454 A JP2020065454 A JP 2020065454A JP 7457886 B2 JP7457886 B2 JP 7457886B2
- Authority
- JP
- Japan
- Prior art keywords
- varistor
- copper
- cuo
- diffusion
- laminated
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000000034 method Methods 0.000 title claims description 9
- 238000004519 manufacturing process Methods 0.000 title claims description 5
- 238000009792 diffusion process Methods 0.000 claims description 27
- 239000000919 ceramic Substances 0.000 claims description 15
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 14
- 229910052802 copper Inorganic materials 0.000 claims description 14
- 239000010949 copper Substances 0.000 claims description 14
- 238000010438 heat treatment Methods 0.000 claims description 5
- 229910044991 metal oxide Inorganic materials 0.000 claims description 5
- 150000004706 metal oxides Chemical class 0.000 claims description 5
- 229910018072 Al 2 O 3 Inorganic materials 0.000 claims description 3
- 238000010304 firing Methods 0.000 claims description 3
- 239000004014 plasticizer Substances 0.000 claims description 3
- 239000002904 solvent Substances 0.000 claims description 3
- 229910002637 Pr6O11 Inorganic materials 0.000 claims description 2
- 239000000654 additive Substances 0.000 claims description 2
- 239000011812 mixed powder Substances 0.000 claims description 2
- 239000000843 powder Substances 0.000 claims description 2
- 239000002003 electrode paste Substances 0.000 claims 2
- 230000000996 additive effect Effects 0.000 claims 1
- 238000005520 cutting process Methods 0.000 claims 1
- 238000003825 pressing Methods 0.000 claims 1
- 239000010410 layer Substances 0.000 description 30
- 238000007747 plating Methods 0.000 description 11
- IRIAEXORFWYRCZ-UHFFFAOYSA-N Butylbenzyl phthalate Chemical compound CCCCOC(=O)C1=CC=CC=C1C(=O)OCC1=CC=CC=C1 IRIAEXORFWYRCZ-UHFFFAOYSA-N 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- QTBSBXVTEAMEQO-UHFFFAOYSA-N Acetic acid Chemical compound CC(O)=O QTBSBXVTEAMEQO-UHFFFAOYSA-N 0.000 description 3
- 238000009413 insulation Methods 0.000 description 3
- 229910015902 Bi 2 O 3 Inorganic materials 0.000 description 2
- 229910004283 SiO 4 Inorganic materials 0.000 description 2
- 239000011230 binding agent Substances 0.000 description 2
- 238000001816 cooling Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 238000002844 melting Methods 0.000 description 2
- 230000008018 melting Effects 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 229920002037 poly(vinyl butyral) polymer Polymers 0.000 description 2
- 229920005989 resin Polymers 0.000 description 2
- 239000011347 resin Substances 0.000 description 2
- 239000002002 slurry Substances 0.000 description 2
- 239000002344 surface layer Substances 0.000 description 2
- 229910020599 Co 3 O 4 Inorganic materials 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 230000002159 abnormal effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- DKPFZGUDAPQIHT-UHFFFAOYSA-N butyl acetate Chemical compound CCCCOC(C)=O DKPFZGUDAPQIHT-UHFFFAOYSA-N 0.000 description 1
- 125000000484 butyl group Chemical group [H]C([*])([H])C([H])([H])C([H])([H])C([H])([H])[H] 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000007606 doctor blade method Methods 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000004453 electron probe microanalysis Methods 0.000 description 1
- 238000011156 evaluation Methods 0.000 description 1
- -1 is diffused Substances 0.000 description 1
- DOIRQSBPFJWKBE-UHFFFAOYSA-N phthalic acid di-n-butyl ester Natural products CCCCOC(=O)C1=CC=CC=C1C(=O)OCCCC DOIRQSBPFJWKBE-UHFFFAOYSA-N 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
Description
本発明は、各種電子機器に用いられる積層バリスタに関するものである。 The present invention relates to a multilayer varistor used in various electronic devices.
電子機器の軽薄短小化に伴い静電気対策部品としてバリスタ層と内部電極を積層した積層バリスタが用いられている。積層バリスタはＺｎＯを主成分として特性を発現させるため粒界成分としてＢｉ2Ｏ3を用いたものと、Ｐｒ6Ｏ11を用いたものが生産販売されている。ＺｎＯは比抵抗が低いため素子表面抵抗が低いためめっき時にめっき流れが発生しやすい。そのため、Ｂｉ2Ｏ3を用いた積層バリスタについてはＺｎ7Ｓｂ2Ｏ12、Ｚｎ2ＳｉＯ4を中心とした高抵抗層を形成させる方法がとられている。一方、Ｐｒ6Ｏ11を用いた積層バリスタではガラス等の絶縁物を表面に形成させ高抵抗層を形成する方法や、Ｌｉをセラミック表面に拡散させ、その原子価制御により主成分であるＺｎＯを高抵抗化させることによりこの問題を解決している。なお、この出願の発明に関連する先行技術文献情報としては、例として、特許文献１、２が知られている。 BACKGROUND OF THE INVENTION As electronic devices become lighter, thinner, and smaller, multilayer varistors, in which varistor layers and internal electrodes are laminated, are being used as static electricity countermeasure components. Laminated varistors are produced and sold in two types: one using Bi 2 O 3 as a grain boundary component and the other using Pr 6 O 11 as a grain boundary component in order to develop characteristics using ZnO as a main component. Since ZnO has a low specific resistance and thus has a low element surface resistance, plating flow tends to occur during plating. Therefore, for a multilayer varistor using Bi 2 O 3 , a method is used in which a high resistance layer is formed mainly of Zn 7 Sb 2 O 12 and Zn 2 SiO 4 . On the other hand, in multilayer varistors using Pr 6 O 11 , the main component ZnO can be reduced by forming an insulator such as glass on the surface to form a high resistance layer, or by diffusing Li on the ceramic surface and controlling its valence. This problem is solved by increasing the resistance. In addition, as prior art document information related to the invention of this application, Patent Documents 1 and 2 are known as examples.
しかしながらＰｒ6Ｏ11を粒界成分とする積層バリスタではＰｒ6Ｏ11の融点が高いためＺｎ7Ｓｂ2Ｏ12、Ｚｎ2ＳｉＯ4といったＳｂ2Ｏ3、ＳｉＯ2とＺｎＯの化合物である高抵抗層の形成方法は中間生成層が形成しづらいため困難である。又、ガラス等による絶縁物の形成はその形成工程で材料費と労力がかかりコストがかかる。一方、Ｌｉをセラミック表面に拡散させる方法については、Ｌｉのイオン半径が小さいため処理条件によっては拡散速度が上がってしまい、結果、内部電極間のバリスタ層まで到達しＺｎＯの抵抗をあげてしまうことから電気特性を悪化させたり、Ｌｉのイオン化傾向が大きいことから耐湿負荷性能が悪化してしまう問題があった。 However, in a laminated varistor containing Pr 6 O 11 as a grain boundary component, since the melting point of Pr 6 O 11 is high, high resistance materials such as Sb 2 O 3 such as Zn 7 Sb 2 O 12 and Zn 2 SiO 4 and compounds of SiO 2 and ZnO are used. The layer formation method is difficult because it is difficult to form an intermediate layer. Further, forming an insulator using glass or the like is expensive because the forming process requires material costs and labor. On the other hand, with regard to the method of diffusing Li onto the ceramic surface, the diffusion rate may increase depending on the processing conditions due to the small ionic radius of Li, and as a result, it may reach the varistor layer between internal electrodes and increase the resistance of ZnO. There have been problems in that the electrical properties are deteriorated due to this, and the moisture resistance load performance is deteriorated due to the large ionization tendency of Li.
本発明はこの課題に対して、表面に高抵抗層を設け電極にメッキ層を形成しやすい積層バリスタを提供することを目的とする。 The present invention aims to address this issue by providing a multilayer varistor that has a high resistance layer on its surface and makes it easy to form a plating layer on the electrode.
本発明は上記課題を解決するために、ＺｎＯを主成分とし粒界成分をＰｒ6Ｏ11とするバリスタ層に少なくとも一対の内部電極を有する積層バリスタであって、積層バリスタの表面から０．０１ｍｍ内側まで設けられた銅の拡散層を有し、拡散層の中にはＣｕＯに換算して５×１０-7ｗｔ％以上、０．５ｗｔ％以下の銅が含まれているように構成したものである。 In order to solve the above problems, the present invention provides a laminated varistor having at least a pair of internal electrodes in a varistor layer whose main component is ZnO and whose grain boundary component is Pr6O11 , and which has a copper diffusion layer extending from the surface of the laminated varistor to a depth of 0.01 mm inward, and which is configured so that the diffusion layer contains 5 x 10-7 wt% or more and 0.5 wt% or less of copper, calculated as CuO.
以上のように構成することにより、内部のバリスタ層に影響を与えることなく、表面の絶縁抵抗を上げることができ、電極へのメッキ等も問題なく行うことができる。 By configuring it in this way, the surface insulation resistance can be increased without affecting the internal varistor layer, and plating of the electrodes can be performed without any problems.
以下、本発明の一実施の形態における積層バリスタについて、図面を参照しながら説明する。 DESCRIPTION OF THE PREFERRED EMBODIMENTS A laminated varistor according to an embodiment of the present invention will be described below with reference to the drawings.
図１は本発明の一実施の形態における積層バリスタ１１の断面図であり、一対の内部電極１３がバリスタ層１２の内部に対向するように積層されて積層体を構成し、一対の内部電極１３はその端部が積層体の対向する両端面に交互に露出するよう積層されており、積層体の両端面に形成された一対の外部電極１４に交互に接続されている。バリスタ層１２はＺｎＯを主成分とし粒界成分をＰｒ6Ｏ11としている。この積層体の表面から内部にかけて銅が拡散された拡散層１５となっている。この拡散層１５は表面から０．０１ｍｍ以上の深さまで拡散され、その拡散濃度をＣｕＯに換算して約０．１ｗｔ％とし、これによって表面の絶縁抵抗を高めている。しかしながら一対の内部電極１３によって形成されるバリスタ領域までは拡散層１５が到達しないようにしている。このようにすることによりバリスタ特性に影響を与えることなく、表面のみを高抵抗にすることができ、メッキ等も問題なく行うことができる。拡散層１５の中にはＣｕＯに換算して５×１０-7ｗｔ％以上、０．５ｗｔ％以下の銅が含まれているようにすることが望ましい。５×１０-7ｗｔ％よりも少なくなると絶縁抵抗を十分に高くすることができず、０．５ｗｔ％より高くするとバリスタ領域まで拡散してバリスタ特性を劣化させる可能性があるためである。 FIG. 1 is a cross-sectional view of a laminated varistor 11 according to an embodiment of the present invention, in which a pair of internal electrodes 13 are stacked to face each other inside a varistor layer 12 to form a laminate. are stacked so that their ends are alternately exposed on both opposing end faces of the laminate, and are alternately connected to a pair of external electrodes 14 formed on both end faces of the laminate. The varistor layer 12 is mainly composed of ZnO and has a grain boundary component of Pr 6 O 11 . This laminate has a diffusion layer 15 in which copper is diffused from the surface to the inside. This diffusion layer 15 is diffused to a depth of 0.01 mm or more from the surface, and its diffusion concentration is approximately 0.1 wt% in terms of CuO, thereby increasing the insulation resistance of the surface. However, the diffusion layer 15 is prevented from reaching the varistor region formed by the pair of internal electrodes 13. By doing so, only the surface can be made high in resistance without affecting the varistor characteristics, and plating etc. can be performed without any problem. It is desirable that the diffusion layer 15 contains copper in an amount of 5×10 -7 wt% or more and 0.5 wt% or less in terms of CuO. This is because if it is less than 5×10 −7 wt%, the insulation resistance cannot be made sufficiently high, and if it is more than 0.5 wt%, it may diffuse into the varistor region and deteriorate the varistor characteristics.
次に本発明の一実施の形態における積層バリスタの製造方法について説明する。 Next, we will explain the manufacturing method of the laminated varistor in one embodiment of the present invention.
まず主成分であるＺｎＯとＰｒ6Ｏ11、Ｃｏ3Ｏ4、Ｋ2ＣＯ3、Ｃｒ2Ｏ3などの添加物を含むバリスタ材料を混合粉砕後、有機バインダーとしてポリビニルブチラール樹脂、溶剤としてノルマル酢酸ブチル、可塑剤としてベンジルブチルフタレートなどを混合してスラリーを得る。そしてこのスラリーをドクターブレード法などにより成形し、バリスタ層となるセラミックシートを作製する。 First, the main component ZnO and varistor material containing additives such as Pr 6 O 11 , Co 3 O 4 , K 2 CO 3 and Cr 2 O 3 are mixed and ground, and then polyvinyl butyral resin is used as an organic binder and normal acetic acid is used as a solvent. Butyl and benzyl butyl phthalate as a plasticizer are mixed to obtain a slurry. This slurry is then molded using a doctor blade method or the like to produce a ceramic sheet that will become the varistor layer.
一方、導電性金属粉末としてＰｄを、有機バインダーとしてポリビニルブチラール樹脂、溶剤としてノルマル酢酸ブチル、可塑剤としてベンジルブチルフタレートなどを混合した後、さらにロールミル等を用いて混練して内部電極を形成するための金属ペーストを作製する。 Meanwhile, Pd is mixed as a conductive metal powder, polyvinyl butyral resin as an organic binder, normal butyl acetate as a solvent, benzyl butyl phthalate as a plasticizer, etc., and then further kneaded using a roll mill or the like to create a metal paste for forming the internal electrodes.
次にセラミックシートを所定の枚数積層し、所望の厚みを有するバリスタ層を積層して形成する。 Next, a predetermined number of ceramic sheets are laminated to form a varistor layer having a desired thickness.
このバリスタ層の上に所定の形状を持つ第１の内部電極を形成する。 A first internal electrode having a predetermined shape is formed on this varistor layer.
次に、この第１の内部電極を形成したセラミックシート上にセラミックシートを積層し、さらにセラミックシート上に所定の形状を持つ第２の内部電極を形成する。 Next, a ceramic sheet is laminated on the ceramic sheet on which the first internal electrode is formed, and a second internal electrode having a predetermined shape is further formed on the ceramic sheet.
ここで、第１、第２の内部電極はセラミックシートを挟んで、対向するように形成され一対の内部電極としているが、この第１、第２の内部電極は各々左右の外部電極に交互に接続されるようにずらして形成される。 Here, the first and second internal electrodes are formed to face each other with a ceramic sheet in between, forming a pair of internal electrodes. Formed in a staggered manner so as to be connected.
次に、前記第２の内部電極の上にセラミックシートを積層して加圧、圧着後、所定の形状に切断して積層チップバリスタ素子の成形体を得る。 Next, a ceramic sheet is laminated on top of the second internal electrode, pressurized and crimped, and then cut into a specified shape to obtain a molded body of a multilayer chip varistor element.
この成形体を１２００℃の温度まで昇温速度２００℃/ｈで昇温し、最高温度で２時間保持した後に、降温速度１００℃/ｈで降温して焼成した。 This molded body was heated to a temperature of 1200°C at a heating rate of 200°C/h, held at the maximum temperature for 2 hours, and then lowered and fired at a cooling rate of 100°C/h.
焼成後、積層チップバリスタ素子の面取りを行い、（表１）記載の酸化物およびＣｕＯを配合し混合した紛体中に焼結体を入れ昇温速度２００℃/ｈで昇温し、（表１）記載の拡散処理温度で２時間保持した後に、降温速度１００℃/ｈで降温してＣｕＯの拡散処理を行った。 After firing, the multilayer chip varistor element was chamfered, and the sintered body was placed in a mixed powder of the oxides and CuO listed in (Table 1), and the temperature was raised at a heating rate of 200°C/h. After maintaining the diffusion treatment temperature described in ) for 2 hours, the temperature was lowered at a cooling rate of 100° C./h to perform a CuO diffusion treatment.
次にＣｕＯの拡散処理を行った焼結体の内部電極が露出した端面にＡｇを主成分とする一対の外部電極を形成して焼付けめっきを行い、一対の外部電極を含む素子外形のＬ寸法１．６ｍｍ×Ｗ、Ｔ寸法０．８ｍｍの（表１）に示す試料番号１～１３の積層バリスタを得た。 Next, a pair of external electrodes containing Ag as a main component are formed on the end face of the sintered body where the internal electrodes are exposed after the CuO diffusion treatment, and baking plating is performed. Laminated varistors with sample numbers 1 to 13 shown in Table 1 having dimensions of 1.6 mm x W and 0.8 mm in T were obtained.
なお試料番号１については比較のためＣｕＯの拡散処理していないものとなっている。 Note that sample number 1 was not subjected to CuO diffusion treatment for comparison.
高抵抗層深さについては素子断面にたいしＥＰＭＡを用い、ＣｕＯが検出される深さを確認するとともに拡散層中のＣｕＯ拡散量についてもバリスタ表面層から０．０１ｍｍ内側の３点の平均値にて算出した。 Regarding the depth of the high resistance layer, we used EPMA on the cross section of the device to confirm the depth at which CuO is detected, and also determined the amount of CuO diffused in the diffusion layer using the average value of three points 0.01 mm inside from the varistor surface layer. Calculated by.
めっき流れについては、めっき後の素子表面のめっき流れ発生状態にたいし金属顕微鏡を用いｎ＝１００中のめっき流れ発生率を算出した。 Regarding the plating flow, the plating flow occurrence rate in n=100 was calculated using a metallurgical microscope with respect to the plating flow occurrence state on the element surface after plating.
次に、得られた積層バリスタのバリスタ電圧、制限電圧の測定方法について述べる。バリスタ電圧は、一対の外部電極に直流定電圧電源を接続し、１ｍＡの電流を流したときの電圧値（Ｖ1mA）を測定した。制限電圧は波高値１Ａの８／２０μｓ標準波形のインパルス電流を印加したときの一対の外部電極端子間電圧波高値(Ｖ1A)を測定した。制限電圧比は波高値１Ａの８／２０μｓ標準波形のインパルス電流を印加したときのＶ1Aを１ｍＡの電流を流したときの電圧値で割ったものであり、異なるバリスタ電圧での制限電圧を比較評価することに用いられる。この制限電圧は１に近いほど望ましい。 Next, a method for measuring the varistor voltage and limiting voltage of the obtained multilayer varistor will be described. The varistor voltage was measured by connecting a DC constant voltage power source to the pair of external electrodes and measuring the voltage value (V 1 mA ) when a current of 1 mA was applied. The limiting voltage was determined by measuring the voltage peak value (V 1A ) between a pair of external electrode terminals when an impulse current of 8/20 μs standard waveform with a peak value of 1 A was applied. The limiting voltage ratio is the V 1A when an impulse current of 8/20 μs standard waveform with a peak value of 1A is applied divided by the voltage value when a current of 1mA is applied, and the limiting voltage at different varistor voltages is compared. Used for evaluation. The closer this limit voltage is to 1, the more desirable it is.
上記の検討により、ＣｕＯを拡散していないものおよびＣｕＯの拡散量が５×１０-7ｗ
ｔ％を下回った場合、素子表面抵抗の低下によりめっき流れが発生する。一方ＣｕＯの拡散量が０．５ｗｔ％を上回った場合バリスタ層内部への拡散深さが深くなるため電気的特性を支配する内部電極間のセラミックまで銅が拡散してしまい、ＺｎＯ中の比抵抗が増加してしまうことにより、制限電圧が悪化してしまう可能性がある。このことから拡散層中のＣｕＯ量は５×１０-7ｗｔ％以上、０．５ｗｔ％以下であることが望ましい。このＣｕＯ拡散量を得るためには金属酸化物中のＣｕＯ量が１×１０-5ｗｔ％以上、１０ｗｔ％以下とすることが望ましい。
Based on the above study, it was found that the amount of diffusion of CuO is 5×10 -7 w in the case where CuO is not diffused.
When it is less than t%, plating flow occurs due to a decrease in element surface resistance. On the other hand, if the amount of CuO diffused exceeds 0.5 wt%, the depth of diffusion into the varistor layer becomes deep, and copper diffuses into the ceramic between the internal electrodes that controls the electrical characteristics, resulting in a decrease in the specific resistance in ZnO. As a result, the limit voltage may deteriorate. From this, it is desirable that the amount of CuO in the diffusion layer is 5×10 -7 wt% or more and 0.5 wt% or less. In order to obtain this amount of CuO diffusion, it is desirable that the amount of CuO in the metal oxide is 1×10 -5 wt% or more and 10 wt% or less.
またＣｕＯを混合する金属酸化物はＺｒＯ2、Ａｌ2Ｏ3、ＺｎＯいずれにおいても効果に差は認められないことからＺｒＯ2、Ａｌ2Ｏ3、ＺｎＯのいずれを使ってもよい。金属酸化物なしで直接ＣｕＯ中で熱処理しても銅を拡散できるが拡散量の制御が困難であることから望ましくない。 In addition, since there is no difference in effect between ZrO 2 , Al 2 O 3 and ZnO as the metal oxide to be mixed with CuO, any of ZrO 2 , Al 2 O 3 and ZnO may be used. Copper can be diffused by heat treatment directly in CuO without a metal oxide, but this is not desirable because it is difficult to control the amount of diffusion.
ＣｕＯを拡散させる拡散処理温度については８００℃～１１００℃までの範囲であれば問題がない。 There is no problem as long as the diffusion treatment temperature for diffusing CuO is in the range of 800°C to 1100°C.
ＺｎＯを主成分とする積層バリスタの材料系としては大きく分けて粒界層にＢｉＯ2とＰｒ6Ｏ11を用いた２つの種類が存在するが、Ｐｒ6Ｏ11に比べＢｉＯ2は融点が低いため銅が拡散しやすいためバリスタ表面層の絶縁に必要な５×１０-7ｗｔ％の銅を拡散させた場合、電気的特性が発生する内部電極に挟まれたバリスタ層にも銅が拡散されてしまうため、内部電極間セラミック層の抵抗まで上げてしまうことから、異常電圧が印加された際の抑制効果が低下（制限電圧の上昇）してしまうことから、融点が高いＰｒ6Ｏ11を粒界成分とする積層バリスタに適用することが望ましい。 There are two main types of materials for multilayer varistors whose main component is ZnO: BiO 2 and Pr 6 O 11 in the grain boundary layer, but BiO 2 has a lower melting point than Pr 6 O 11 . Therefore, when 5×10 -7 wt% of copper, which is necessary for insulating the varistor surface layer, is diffused, copper is easily diffused into the varistor layer sandwiched between the internal electrodes where electrical characteristics occur. This increases the resistance of the internal interelectrode ceramic layer, which reduces the suppressing effect when an abnormal voltage is applied (increases the limiting voltage) . It is desirable to apply it to a laminated varistor in which the grain boundary component is a grain boundary component.
本発明に係る積層バリスタは、バリスタ特性を損なうことなくメッキ可能な積層バリスタを得ることができ、産業上有用である。 The laminated varistor according to the present invention is industrially useful since it is possible to obtain a laminated varistor that can be plated without impairing the varistor properties.
１１ 積層バリスタ
１２ バリスタ層
１３ 内部電極
１４ 外部電極
１５ 拡散層
11 Multilayer varistor 12 Varistor layer 13 Internal electrode 14 External electrode 15 Diffusion layer
Claims (4)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2020065454A JP7457886B2 (en) | 2020-04-01 | 2020-04-01 | Multilayer varistor and method for manufacturing same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2020065454A JP7457886B2 (en) | 2020-04-01 | 2020-04-01 | Multilayer varistor and method for manufacturing same |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2021163894A JP2021163894A (en) | 2021-10-11 |
| JP7457886B2 true JP7457886B2 (en) | 2024-03-29 |
Family
ID=78005119
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2020065454A Active JP7457886B2 (en) | 2020-04-01 | 2020-04-01 | Multilayer varistor and method for manufacturing same |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP7457886B2 (en) |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2000124007A (en) | 1998-10-13 | 2000-04-28 | Murata Mfg Co Ltd | Chip thermistor and method of producing the same |
| JP4170004B2 (en) | 2002-03-28 | 2008-10-22 | 日本板硝子株式会社 | Compound semiconductor multilayer structure |
| JP2008277786A (en) | 2007-03-30 | 2008-11-13 | Tdk Corp | Voltage non-linear resistance porcelain composition and voltage non-linear resistance element |
| JP5121211B2 (en) | 2006-05-11 | 2013-01-16 | コーニング ケーブル システムズ リミテッド ライアビリティ カンパニー | Optical fiber distribution cable and structure thereof |
| JP2014120605A (en) | 2012-12-17 | 2014-06-30 | Tdk Corp | Chip varistor |
-
2020
- 2020-04-01 JP JP2020065454A patent/JP7457886B2/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2000124007A (en) | 1998-10-13 | 2000-04-28 | Murata Mfg Co Ltd | Chip thermistor and method of producing the same |
| JP4170004B2 (en) | 2002-03-28 | 2008-10-22 | 日本板硝子株式会社 | Compound semiconductor multilayer structure |
| JP5121211B2 (en) | 2006-05-11 | 2013-01-16 | コーニング ケーブル システムズ リミテッド ライアビリティ カンパニー | Optical fiber distribution cable and structure thereof |
| JP2008277786A (en) | 2007-03-30 | 2008-11-13 | Tdk Corp | Voltage non-linear resistance porcelain composition and voltage non-linear resistance element |
| JP2014120605A (en) | 2012-12-17 | 2014-06-30 | Tdk Corp | Chip varistor |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2021163894A (en) | 2021-10-11 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR102089692B1 (en) | Multilayered ceramic electronic component | |
| JP4715248B2 (en) | Multilayer ceramic electronic components | |
| US20080238605A1 (en) | Voltage non-linear resistance ceramic composition and voltage non-linear resistance element | |
| JP4915153B2 (en) | Multilayer varistor | |
| JP5452244B2 (en) | Multilayer ceramic electronic component and manufacturing method thereof | |
| CN112820543A (en) | Ceramic electronic component and method for manufacturing same | |
| US20080241585A1 (en) | Voltage non-linear resistance ceramic composition and voltage non-linear resistance element | |
| JP5527404B2 (en) | Multilayer ceramic electronic components | |
| JP7457886B2 (en) | Multilayer varistor and method for manufacturing same | |
| JP2004022976A (en) | Stacked voltage nonlinear resistor and method of manufacturing the same | |
| JP5830715B2 (en) | Multilayer varistor and manufacturing method thereof | |
| JP4184172B2 (en) | Voltage nonlinear resistor ceramic composition, electronic component and multilayer chip varistor | |
| JP5833929B2 (en) | Varistor ceramic, multilayer component including varistor ceramic, and method for producing varistor ceramic | |
| JP5527400B2 (en) | Multilayer ceramic electronic components | |
| JP5527403B2 (en) | Multilayer ceramic electronic components | |
| WO2020213320A1 (en) | Laminated varistor | |
| JP5282332B2 (en) | Manufacturing method of zinc oxide laminated chip varistor | |
| KR20090112005A (en) | Composite chip device of thermistor-varistor and manufacturing method thereof | |
| JP4539671B2 (en) | Electronic component and manufacturing method thereof | |
| JP2666605B2 (en) | Stacked varistor | |
| JP5034640B2 (en) | Multilayer varistor and manufacturing method thereof | |
| JPH0547508A (en) | Laminated semiconductor porcelain and manufacture thereof | |
| CN112408975B (en) | Ceramic composition, ceramic sintered body, multilayer ceramic electronic component and method for producing the same | |
| JP4292801B2 (en) | Manufacturing method of laminated varistor | |
| JP2504226B2 (en) | Stacked Varistor |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| RD01 | Notification of change of attorney |
Free format text: JAPANESE INTERMEDIATE CODE: A7421 Effective date: 20221020 |
|
| A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20230215 |
|
| A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20231215 |
|
| TRDD | Decision of grant or rejection written | ||
| A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20240206 |
|
| A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20240219 |
|
| R151 | Written notification of patent or utility model registration |
Ref document number: 7457886 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R151 |