JP7430843B1 - Oxide semiconductor thin film, semiconductor device and method for manufacturing the same, sputtering target and method for manufacturing the sputtering target - Google Patents
Oxide semiconductor thin film, semiconductor device and method for manufacturing the same, sputtering target and method for manufacturing the sputtering target Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 128
- 239000010409 thin film Substances 0.000 title claims abstract description 88
- 238000000034 method Methods 0.000 title claims abstract description 24
- 238000005477 sputtering target Methods 0.000 title claims abstract description 22
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 15
- 238000004544 sputter deposition Methods 0.000 title description 8
- 239000000203 mixture Substances 0.000 claims abstract description 36
- 229910052782 aluminium Inorganic materials 0.000 claims abstract description 20
- 229910052733 gallium Inorganic materials 0.000 claims abstract description 18
- 229910052738 indium Inorganic materials 0.000 claims abstract description 16
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims abstract description 12
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 claims abstract description 10
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 claims abstract description 10
- 238000010587 phase diagram Methods 0.000 claims abstract description 4
- 239000010408 film Substances 0.000 claims description 45
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 claims description 12
- 238000005530 etching Methods 0.000 claims description 9
- 239000000843 powder Substances 0.000 claims description 8
- 229910000147 aluminium phosphate Inorganic materials 0.000 claims description 6
- AJNVQOSZGJRYEI-UHFFFAOYSA-N digallium;oxygen(2-) Chemical compound [O-2].[O-2].[O-2].[Ga+3].[Ga+3] AJNVQOSZGJRYEI-UHFFFAOYSA-N 0.000 claims description 4
- 229910001195 gallium oxide Inorganic materials 0.000 claims description 4
- 229910003437 indium oxide Inorganic materials 0.000 claims description 4
- PJXISJQVUVHSOJ-UHFFFAOYSA-N indium(iii) oxide Chemical compound [O-2].[O-2].[O-2].[In+3].[In+3] PJXISJQVUVHSOJ-UHFFFAOYSA-N 0.000 claims description 4
- 238000002156 mixing Methods 0.000 claims description 4
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 claims description 4
- 238000010304 firing Methods 0.000 claims description 3
- 238000001354 calcination Methods 0.000 claims description 2
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- 238000000231 atomic layer deposition Methods 0.000 description 5
- 230000001681 protective effect Effects 0.000 description 5
- 238000001771 vacuum deposition Methods 0.000 description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 229910052814 silicon oxide Inorganic materials 0.000 description 4
- 239000010936 titanium Substances 0.000 description 4
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- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
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- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 description 1
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- 229910004205 SiNX Inorganic materials 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 229910007541 Zn O Inorganic materials 0.000 description 1
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Abstract
【課題】キャリア濃度が低く、ホール移動度が高い酸化物半導体薄膜であり、これを活性層とした薄膜半導体デバイスは、高温でも閾値電圧がネガティブシフトしない、酸化物半導体薄膜及びそれを用いた半導体デバイス、このような酸化物半導体薄膜を形成できるスパッタリングターゲット及びその製造方法を実現する。【解決手段】 インジウム、ガリウム、及びアルミニウムを下記組成で含む酸化物を主成分とする酸化物半導体で構成され、前記酸化物半導体のＸ、Ｙ及びＺの組成比は、Ｉｎ、Ｇａ及びＡｌの３成分系相図の下記Ａ点とＢ点を結ぶ線分、下記Ｂ点とＣ点とを結ぶ線分、下記Ｃ点とＤ点とを結ぶ線分、及び下記Ｄと下記Ａ点とを結ぶ線分とで囲まれる領域の組成比である酸化物半導体薄膜。組成：ＩｎＸＧａＹＡｌＺＡ点：Ｉｎ１０Ｇａ９0Ａｌ０Ｂ点：Ｉｎ３０Ｇａ３０Ａｌ４０Ｃ点：Ｉｎ４５Ｇａ１５Ａｌ４０Ｄ点：Ｉｎ４５Ｇａ５５Ａｌ０【選択図】 図１[Problem] An oxide semiconductor thin film with low carrier concentration and high hole mobility, and a thin film semiconductor device using this as an active layer, an oxide semiconductor thin film whose threshold voltage does not shift negatively even at high temperatures, and a semiconductor using the same. A device, a sputtering target capable of forming such an oxide semiconductor thin film, and a method for manufacturing the same are realized. [Solution] The oxide semiconductor is composed of an oxide containing indium, gallium, and aluminum in the following composition as a main component, and the composition ratio of X, Y, and Z of the oxide semiconductor is equal to that of In, Ga, and Al. A line segment connecting points A and B below in the three-component system phase diagram, a line segment connecting point B and C below, a line segment connecting point C and D below, and D and A point below. The composition ratio of the area surrounded by the connecting line segments is the oxide semiconductor thin film. Composition: InXGaYAlZA point: In10Ga90Al0B point: In30Ga30Al40C point: In45Ga15Al40D point: In45Ga55Al0 [Selection diagram] Figure 1
Description
本発明は、酸化物半導体薄膜、半導体デバイス及びその製造方法、並びにスパッタリングターゲット及びスパッタリングターゲットの製造方法に関する。 The present invention relates to an oxide semiconductor thin film, a semiconductor device, a method for manufacturing the same, a sputtering target, and a method for manufacturing the sputtering target.
Ｉｎ－Ｇａ－Ｚｎ－Ｏ系酸化物半導体膜（ＩＧＺＯ）を活性層に用いた薄膜トランジスタ（ＴＦＴ：Thin-Film Transistor）は、従来のアモルファスシリコン膜を活性層に用いたＴＦＴと比較して、高移動度を得ることができることから、近年、種々のディスプレイに幅広く適用されている（例えば、特許文献１参照）。 Thin-film transistors (TFTs) that use an In-Ga-Zn-O-based oxide semiconductor film (IGZO) as an active layer have higher performance than conventional TFTs that use an amorphous silicon film as an active layer. Since it is possible to obtain high mobility, it has been widely applied to various displays in recent years (see, for example, Patent Document 1).
また、ディスプレイ以外の半導体デバイスにＩＧＺＯを適用する研究が、近年活発化している。しかしながら、デバイスの信頼性試験において閾値電圧がネガティブシフト（Negative Shift）することが問題になっている（非特許文献１、２参照）。 Furthermore, research on applying IGZO to semiconductor devices other than displays has become active in recent years. However, negative shift of the threshold voltage has become a problem in device reliability tests (see Non-Patent Documents 1 and 2).
半導体デバイスでは、ディスプレイデバイスよりもプロセス温度が高く、酸化物半導体が還元され易いことや、ディスプレイデバイスより高い信頼性が要求されるため、高温でも閾値電圧がネガティブシフト（Negative Shift）しない酸化物半導体材料が必要となる。 Semiconductor devices require higher process temperatures than display devices, and oxide semiconductors are more easily reduced, and require higher reliability than display devices. Therefore, oxide semiconductors do not have a negative shift in threshold voltage even at high temperatures. Materials are required.
以上のような事情に鑑み、本発明の目的は、キャリア濃度が低く、ホール移動度が高い酸化物半導体薄膜であり、これを活性層とした薄膜半導体デバイスは、高温でも閾値電圧がネガティブシフトしない、酸化物半導体薄膜及びそれを用いた半導体デバイス、このような酸化物半導体薄膜を形成できるスパッタリングターゲット及びその製造方法を実現することにある。 In view of the above circumstances, an object of the present invention is to provide an oxide semiconductor thin film with a low carrier concentration and high hole mobility, and a thin film semiconductor device using this as an active layer has a threshold voltage that does not shift negatively even at high temperatures. An object of the present invention is to realize an oxide semiconductor thin film, a semiconductor device using the same, a sputtering target capable of forming such an oxide semiconductor thin film, and a method for manufacturing the same.
前記目的を達成するために種々研究を重ねた結果、所定の組成比を有するインジウム、ガリウム、及びアルミニウムを含む酸化物半導体薄膜が高温プロセス後も低いキャリア濃度を維持し、閾値電圧がネガティブシフトしないことを知見し、本発明を完成させた。
かかる本発明は、以下のとおりである。
As a result of various studies to achieve the above objective, we have found that an oxide semiconductor thin film containing indium, gallium, and aluminum with a predetermined composition ratio maintains a low carrier concentration even after high-temperature processing, and the threshold voltage does not shift negatively. Based on this knowledge, the present invention was completed.
The present invention is as follows.
本発明の第１の態様は、インジウム、ガリウム、及びアルミニウを下記組成で含む酸化物を主成分とする酸化物半導体で構成され、前記酸化物半導体が、Ｉｎ、Ｇａ及びＡｌの３成分系相図の下記Ａ点とＢ点を結ぶ線分、下記Ｂ点とＣ点とを結ぶ線分、下記Ｃ点とＤ点とを結ぶ線分、及び下記Ｄと下記Ａ点とを結ぶ線分とで囲まれる領域の組成比である酸化物半導体薄膜である。
組成：ＩｎＸＧａＹＡｌＺ
Ａ点：Ｉｎ１０Ｇａ９０Ａｌ０
Ｂ点：Ｉｎ３０Ｇａ３０Ａｌ４０
Ｃ点：Ｉｎ４５Ｇａ１５Ａｌ４０
Ｄ点：Ｉｎ４５Ｇａ５５Ａｌ０
本発明の第２の態様は、キャリア濃度が１×１０１８ｃｍ－３以下である第１の態様に記載の酸化物半導体薄膜である。
本発明の第３の態様は、ホール移動度が、１ｃｍ２／Ｖｓ以上である第１の態様に記載の酸化物半導体薄膜である。
本発明の第４の態様は、リン酸系エッチャントでエッチングした際のエッチングレートが１ｎｍ／ｓｅｃ以上である第１の態様に記載の酸化物半導体薄膜である。
本発明の第５の態様は、酸化物半導体薄膜を具備する半導体デバイスであって、前記酸化物半導体薄膜の少なくとも一部が、第１～４のいずれかの態様に記載の酸化物半導体薄膜である半導体デバイスである。
本発明の第６の態様は、ゲート電極、ゲート絶縁膜、活性層、ソース電極及びドレイン電極を有する半導体デバイスであり、前記酸化物半導体薄膜が前記活性層である第５の態様に記載の半導体デバイスである。
本発明の第７の態様は、酸化物半導体薄膜を具備する半導体デバイスの製造方法であって、前記酸化物半導体薄膜の少なくとも一部として、第１～４のいずれかの態様に記載の酸化物半導体薄膜を成膜する工程と、前記酸化物半導体薄膜の酸化物半導体の還元処理を含む工程と、を具備する半導体デバイスの製造方法である。
本発明の第８の態様は、インジウム、ガリウム、及びアルミニウムを下記組成で含む酸化物を主成分とする酸化物焼結体で構成され、前記酸化物半導体が、Ｉｎ、Ｇａ及びＡｌの３成分系相図の下記Ａ点とＢ点を結ぶ線分、下記Ｂ点とＣ点とを結ぶ線分、下記Ｃ点とＤ点とを結ぶ線分、及び下記Ｄと下記Ａ点とを結ぶ線分とで囲まれる領域の組成比であるスパッタリングターゲットである。
組成：ＩｎＸＧａＹＡｌＺ
Ａ点：Ｉｎ１０Ｇａ９０Ａｌ０
Ｂ点：Ｉｎ３０Ｇａ３０Ａｌ４０
Ｃ点：Ｉｎ４５Ｇａ１５Ａｌ４０
Ｄ点：Ｉｎ４５Ｇａ５５Ａｌ０
本発明の第９の態様は、スパッタリングターゲットにおいて、相対密度が９０％以上である第８の態様に記載のスパッタリングターゲットである。
本発明の第１０の態様は、酸化インジウム粉末、酸化ガリウム粉末、及び酸化アルミニウム粉末を混合して成形体を形成し、１１００℃以上１６５０℃以下で前記成形体を焼成して、第８又は９の態様に記載の酸化物焼結体を有するスパッタリングターゲットを製造するスパッタリングターゲットの製造方法である。
本発明の第１１の態様は、インジウム、ガリウム、及びアルミニウムの酸化物、水酸化物または炭酸塩を混合して１０００℃～１５００℃で仮焼成した前駆体粉末を成形して成形体とし、１１００℃以上１６５０℃以下で前記成形体を焼成して、第８又は９の態様に記載の酸化物焼結体を有するスパッタリングターゲットを製造するスパッタリングターゲットの製造方法である。
A first aspect of the present invention is composed of an oxide semiconductor mainly composed of an oxide containing indium, gallium, and aluminum in the following composition, wherein the oxide semiconductor has a ternary phase of In, Ga, and Al. A line segment connecting points A and B below, a line segment connecting points B and C below, a line segment connecting point C and D below, and a line segment connecting D below and A point below in the diagram. This is an oxide semiconductor thin film whose composition ratio is in the region surrounded by .
Composition: In X Ga Y Al Z
Point A: In 10 Ga 90 Al 0
Point B: In 30 Ga 30 Al 40
Point C: In 45 Ga 15 Al 40
Point D: In 45 Ga 55 Al 0
A second aspect of the present invention is the oxide semiconductor thin film according to the first aspect, which has a carrier concentration of 1×10 18 cm −3 or less.
A third aspect of the present invention is the oxide semiconductor thin film according to the first aspect, which has a hole mobility of 1 cm 2 /Vs or more.
A fourth aspect of the present invention is the oxide semiconductor thin film according to the first aspect, which has an etching rate of 1 nm/sec or more when etched with a phosphoric acid-based etchant.
A fifth aspect of the present invention is a semiconductor device comprising an oxide semiconductor thin film, wherein at least a portion of the oxide semiconductor thin film is the oxide semiconductor thin film according to any one of the first to fourth aspects. It is a certain semiconductor device.
A sixth aspect of the present invention is a semiconductor device having a gate electrode, a gate insulating film, an active layer, a source electrode, and a drain electrode, and the semiconductor according to the fifth aspect, wherein the oxide semiconductor thin film is the active layer. It is a device.
A seventh aspect of the present invention is a method for manufacturing a semiconductor device including an oxide semiconductor thin film, wherein the oxide semiconductor according to any one of the first to fourth aspects is used as at least a part of the oxide semiconductor thin film. A method for manufacturing a semiconductor device, comprising a step of forming a semiconductor thin film, and a step of reducing an oxide semiconductor of the oxide semiconductor thin film.
An eighth aspect of the present invention is composed of an oxide sintered body mainly composed of an oxide containing indium, gallium, and aluminum in the following composition, and the oxide semiconductor is composed of three components of In, Ga, and Al. A line segment connecting points A and B below in the system phase diagram, a line segment connecting point B and C below, a line segment connecting point C and D below, and a line connecting D below and point A below. This is a sputtering target whose composition ratio is in the area surrounded by .
Composition: In X Ga Y Al Z
Point A: In 10 Ga 90 Al 0
Point B: In 30 Ga 30 Al 40
Point C: In 45 Ga 15 Al 40
Point D: In 45 Ga 55 Al 0
A ninth aspect of the present invention is the sputtering target according to the eighth aspect, wherein the sputtering target has a relative density of 90% or more.
A tenth aspect of the present invention is to form a molded body by mixing indium oxide powder, gallium oxide powder, and aluminum oxide powder, and to sinter the molded body at a temperature of 1100° C. or more and 1650° C. or less. A sputtering target manufacturing method for manufacturing a sputtering target having the oxide sintered body according to the embodiment.
An eleventh aspect of the present invention is to mold a precursor powder obtained by mixing oxides, hydroxides or carbonates of indium, gallium, and aluminum and calcining the mixture at 1000°C to 1500°C to form a molded body. This is a method for manufacturing a sputtering target, in which a sputtering target having the oxide sintered body according to the eighth or ninth aspect is manufactured by firing the molded body at a temperature of not less than 1,650 degrees Celsius.
かかる本発明は、インジウム、ガリウム、及びアルミニウムからなる所定の組成を有する酸化物焼結体は、キャリア濃度が１×１０１８ｃｍ－３以下と低く、ホール移動度が１ｃｍ２／Ｖｓ以上の酸化物半導体薄膜となり、これを半導体デバイスの活性層とすると、高温でも閾値電圧がネガティブシフトしない半導体デバイスが実現できる。 According to the present invention, an oxide sintered body having a predetermined composition consisting of indium, gallium, and aluminum has a low carrier concentration of 1×10 18 cm -3 or less and a hole mobility of 1 cm 2 /Vs or more. This results in a physical semiconductor thin film, and if this is used as the active layer of a semiconductor device, a semiconductor device whose threshold voltage does not shift negatively even at high temperatures can be realized.
以下、図面を参照しながら、本発明の実施形態を説明する。 Embodiments of the present invention will be described below with reference to the drawings.
［酸化物半導体薄膜］
本発明の酸化物半導体薄膜は、インジウム、ガリウム、及びアルミニウムを下記組成で含む酸化物を主成分とする酸化物半導体で構成され、前記酸化物半導体が、Ｉｎ、Ｇａ及びＡｌの３成分系相図の下記Ａ点とＢ点を結ぶ線分、下記Ｂ点とＣ点とを結ぶ線分、下記Ｃ点とＤ点とを結ぶ線分、及び下記Ｄと下記Ａ点とを結ぶ線分とで囲まれる領域の組成比であるものである。
組成：ＩｎＸＧａＹＡｌＺ
Ａ点：Ｉｎ１０Ｇａ９０Ａｌ０
Ｂ点：Ｉｎ３０Ｇａ３０Ａｌ４０
Ｃ点：Ｉｎ４５Ｇａ１５Ａｌ４０
Ｄ点：Ｉｎ４５Ｇａ５５Ａｌ０
[Oxide semiconductor thin film]
The oxide semiconductor thin film of the present invention is composed of an oxide semiconductor whose main component is an oxide containing indium, gallium, and aluminum in the following composition, wherein the oxide semiconductor has a three-component phase of In, Ga, and Al. A line segment connecting points A and B below, a line segment connecting points B and C below, a line segment connecting point C and D below, and a line segment connecting D below and A point below in the diagram. This is the composition ratio of the area surrounded by .
Composition: In X Ga Y Al Z
Point A: In 10 Ga 90 Al 0
Point B: In 30 Ga 30 Al 40
Point C: In 45 Ga 15 Al 40
Point D: In 45 Ga 55 Al 0
この組成範囲を図１に示す。
Ｉｎ含有酸化物は酸素欠損を生じやすく、Ｉｎが４５％を超えると、高温でキャリア濃度が高くなりすぎるため使用不可となる。一方、Ｇａ、Ａｌは、酸素欠損の発生を抑制するが、Ａｌが４０％を超えると、キャリア濃度が低すぎ、導電性が得られないため使用不可となる。また、Ｇａ及びＡｌの両方が多い領域では、導電性が得られ難くなるので使用不可となる。
This composition range is shown in FIG.
In-containing oxides tend to cause oxygen vacancies, and if In exceeds 45%, the carrier concentration becomes too high at high temperatures, making them unusable. On the other hand, Ga and Al suppress the occurrence of oxygen vacancies, but if Al exceeds 40%, the carrier concentration is too low and conductivity cannot be obtained, making them unusable. Further, in a region containing a large amount of both Ga and Al, it becomes difficult to obtain conductivity, and therefore it cannot be used.
そして、上述したＡ点、Ｂ点、Ｃ点およびＤ点をそれぞれ結ぶ線分で囲まれた範囲の組成では、キャリア濃度が１×１０１８ｃｍ－３以下と低く、ホール移動度が１ｃｍ２／Ｖｓ以上の酸化物半導体薄膜となることがわかった。 In the composition range surrounded by the line segments connecting points A, B, C, and D mentioned above, the carrier concentration is as low as 1×10 18 cm -3 or less, and the hole mobility is 1 cm 2 / It was found that the oxide semiconductor thin film had a temperature of Vs or higher.
かかる酸化物半導体を用いて形成した酸化物半導体薄膜は、上述したキャリア濃度とホール移動度とを有するので、本発明の酸化物半導体薄膜を活性層とした半導体デバイス、すなわち、ＴＦＴなどのゲート電極、ゲート絶縁膜、活性層、ソース電極及びドレイン電極を有する半導体デバイスでは、キャリア濃度をあげるために還元処理が必要となるが、還元処理を施した後でも、キャリア濃度が１×１０１８ｃｍ－３以下を維持できることもわかった。 Since the oxide semiconductor thin film formed using such an oxide semiconductor has the above-mentioned carrier concentration and hole mobility, it can be used as a gate electrode of a semiconductor device, such as a TFT, in which the oxide semiconductor thin film of the present invention is used as an active layer. In a semiconductor device having a gate insulating film, an active layer, a source electrode, and a drain electrode, a reduction treatment is required to increase the carrier concentration, but even after the reduction treatment, the carrier concentration is 1×10 18 cm − It was also found that it was possible to maintain a score of 3 or less.
かかる還元処理は、還元するために特別に行う必要はなく、酸化物半導体薄膜形成後、３００℃程度又は３００℃を超えるようなプロセス、例えば、ＣＶＤでのＳｉＯ成膜処理プロセスなどにより、同時に酸化物半導体薄膜の還元処理を行うことができる。 Such reduction treatment does not need to be performed specifically for reduction, and after forming the oxide semiconductor thin film, oxidation can be performed at the same time by a process at about 300°C or above 300°C, such as a CVD SiO film formation process. It is possible to perform a reduction treatment on a semiconductor thin film.
また、本発明の酸化物半導体薄膜は、ウェットエッチングでパターニングでき、例えば、リン酸系エッチャントでエッチングした際のエッチングレートが１ｎｍ／ｓｅｃ以上である。ここで、リン酸系エッチャントとしては、リン酸７０～８０％、硝酸１～９％、および酢酸１～１０％の成分を有するＰＡＮ系エッチング液を挙げることができる。 Further, the oxide semiconductor thin film of the present invention can be patterned by wet etching, and has an etching rate of 1 nm/sec or more when etched with a phosphoric acid-based etchant, for example. Here, examples of the phosphoric acid-based etchant include a PAN-based etching solution having components of 70 to 80% phosphoric acid, 1 to 9% nitric acid, and 1 to 10% acetic acid.
ここで、本発明の酸化物半導体の好ましい範囲を図１の三元系図に示す。
この三元系図に示す通り、下記Ｐ点、Ｑ点、Ｒ点およびＳ点で囲まれる範囲の酸化物半導体は、ホール移動度が２ｃｍ２／Ｖｓ以上であり、キャリア濃度が５×１０１６ｃｍ－３以下であり、比較的高移動度を維持することができ、より好ましい組成範囲となる。
Ｐ点：Ｉｎ１５Ｇａ８５Ａｌ０
Ｑ点：Ｉｎ３０Ｇａ４５Ａｌ２５
Ｒ点：Ｉｎ４５Ｇａ３５Ａｌ２５
Ｓ点：Ｉｎ４０Ｇａ６０Ａｌ０
Here, a preferable range of the oxide semiconductor of the present invention is shown in the ternary diagram of FIG.
As shown in this ternary diagram, the oxide semiconductor in the range surrounded by points P, Q, R, and S below has a hole mobility of 2 cm 2 /Vs or more and a carrier concentration of 5 x 10 16 cm. -3 or less, a relatively high mobility can be maintained, and this is a more preferable composition range.
Point P: In 15 Ga 85 Al 0
Q point: In 30 Ga 45 Al 25
R point: In 45 Ga 35 Al 25
Point S: In 40 Ga 60 Al 0
本発明の酸化物半導体薄膜の成膜方法は、特に限定されない。例えば、成膜する組成と同じ組成のスパッタリングターゲットを用いたスパッタリングにより成膜してもよいし、原子層堆積（ＡＬＤ）法や真空蒸着法などによって成膜してもよく、アモルファスな酸化物半導体薄膜が成膜できれば成膜方法は特に限定されない。 The method for forming the oxide semiconductor thin film of the present invention is not particularly limited. For example, a film may be formed by sputtering using a sputtering target with the same composition as the film to be formed, or a film may be formed by an atomic layer deposition (ALD) method, a vacuum evaporation method, etc. The film forming method is not particularly limited as long as a thin film can be formed.
また、本発明の酸化物半導体薄膜は、ＴＦＴなどの薄膜半導体トランジスタである薄膜半導体デバイス（単に、半導体デバイスともいう）の活性層として用いることができる。 Further, the oxide semiconductor thin film of the present invention can be used as an active layer of a thin film semiconductor device (also simply referred to as a semiconductor device) that is a thin film semiconductor transistor such as a TFT.
本発明の酸化物半導体薄膜を備える薄膜半導体デバイスは、アモルファス酸化物半導体薄膜からなる活性層と、前記活性層の一方の面にゲート絶縁膜を介して設けられたゲート電極と、前記活性層に接続するソース電極及びドレイン電極と、を具備する薄膜半導体装置であって、前記活性層が上述した本発明の酸化物半導体薄膜からなるものである。 A thin film semiconductor device including an oxide semiconductor thin film of the present invention includes: an active layer made of an amorphous oxide semiconductor thin film; a gate electrode provided on one surface of the active layer with a gate insulating film interposed therebetween; A thin film semiconductor device comprising a source electrode and a drain electrode connected to each other, wherein the active layer is made of the above-mentioned oxide semiconductor thin film of the present invention.
具体的な半導体デバイスは、前記ゲート絶縁膜及び前記ゲート電極は、前記活性層の上面に設けられ、前記ソース電極及び前記ドレイン電極は、前記活性層の上面側に設けられている構造を挙げることができる。
かかる薄膜半導体装置の一例の構造を図３に示す。
A specific semiconductor device may have a structure in which the gate insulating film and the gate electrode are provided on the upper surface of the active layer, and the source electrode and the drain electrode are provided on the upper surface of the active layer. I can do it.
The structure of an example of such a thin film semiconductor device is shown in FIG.
図２に本発明に係る薄膜トランジスタの一例の概略構成を示す。
本実施形態の薄膜トランジスタ１１０は、基板１０上に、活性層１１と、ゲート絶縁膜１２と、ゲート電極１３と、保護膜（パッシベーション）１４とを具備し、活性層１１から保護膜１４を介して引き出されたソース電極１５Ｓ及びドレイン電極１５Ｄを有する。
FIG. 2 shows a schematic configuration of an example of a thin film transistor according to the present invention.
The thin film transistor 110 of this embodiment includes an active layer 11 , a gate insulating film 12 , a gate electrode 13 , and a protective film (passivation) 14 on a substrate 10 . It has a source electrode 15S and a drain electrode 15D that are drawn out.
基板１０は、典型的には、Ｓｉ基板やガラス基板である。ゲート電極１３は、典型的には、モリブデン（Ｍｏ）、チタン（Ｔｉ）、アルミニウム（Ａｌ）、銅（Ｃｕ）などの金属単層膜あるいは多層膜、またはＴｉＮ、Ｗ、ＷＳｉなど半導体デバイスに使用される一般的なゲート電極材料で構成され、例えばスパッタリング法によって形成される。本実施形態では、ゲート電極１３は、モリブデンで構成される。ゲート電極１３の厚さは特に限定されず、例えば、２００ｎｍである。ゲート電極１３は、例えば、スパッタリング法、ＡＬＤ法、真空蒸着法等で成膜される。 The substrate 10 is typically a Si substrate or a glass substrate. The gate electrode 13 is typically a single layer or multilayer film of a metal such as molybdenum (Mo), titanium (Ti), aluminum (Al), or copper (Cu), or a semiconductor device such as TiN, W, or WSi. The gate electrode is made of a general gate electrode material, and is formed by, for example, a sputtering method. In this embodiment, the gate electrode 13 is made of molybdenum. The thickness of the gate electrode 13 is not particularly limited, and is, for example, 200 nm. The gate electrode 13 is formed by, for example, a sputtering method, an ALD method, a vacuum evaporation method, or the like.
活性層１１は、薄膜トランジスタ１１０のチャネル層として機能する。活性層１１の膜厚は、例えば５ｎｍ～２００ｎｍである。活性層１１は、上述した本発明の酸化物半導体薄膜で構成される。活性層１１は、例えば、スパッタリング法、ＡＬＤ法、真空蒸着法等で成膜される。 The active layer 11 functions as a channel layer of the thin film transistor 110. The thickness of the active layer 11 is, for example, 5 nm to 200 nm. The active layer 11 is composed of the oxide semiconductor thin film of the present invention described above. The active layer 11 is formed by, for example, a sputtering method, an ALD method, a vacuum evaporation method, or the like.
ゲート絶縁膜１２は、ゲート電極１３と活性層１１との間に形成される。ゲート絶縁膜１２は、例えば、シリコン酸化膜（ＳｉＯｘ）、シリコン窒化膜（ＳｉＮｘ）又はこれらの積層膜で構成される。成膜方法は特に限定されず、ＣＶＤ法でもよいし、スパッタリング法、蒸着法等であってもよい。ゲート絶縁膜１２の膜厚は特に限定されず、例えば、２００ｎｍ～４００ｎｍである。 Gate insulating film 12 is formed between gate electrode 13 and active layer 11 . The gate insulating film 12 is composed of, for example, a silicon oxide film (SiOx), a silicon nitride film (SiNx), or a laminated film thereof. The film forming method is not particularly limited, and may be a CVD method, a sputtering method, a vapor deposition method, or the like. The thickness of the gate insulating film 12 is not particularly limited, and is, for example, 200 nm to 400 nm.
ソース電極１５Ｓ及びドレイン電極１５Ｄは、保護膜１４及びキャップ層１３の上に相互に離間して形成される。ソース電極１５Ｓ及びドレイン電極１５Ｄは、例えば、アルミニウム、モリブデン、銅、チタンなどの金属単層膜あるいはこれら金属の多層膜で構成することができる。後述するように、ソース電極１５Ｓ及びドレイン電極１５Ｄは、金属膜をパターニングすることで同時に形成することができる。当該金属膜の厚さは、例えば、１００ｎｍ～２００ｎｍである。ソース電極１５Ｓ及びドレイン電極１５Ｄは、例えば、スパッタリング法、真空蒸着法等で成膜される。 The source electrode 15S and the drain electrode 15D are formed on the protective film 14 and the cap layer 13 so as to be spaced apart from each other. The source electrode 15S and the drain electrode 15D can be made of, for example, a single layer film of a metal such as aluminum, molybdenum, copper, or titanium, or a multilayer film of these metals. As described later, the source electrode 15S and the drain electrode 15D can be formed simultaneously by patterning a metal film. The thickness of the metal film is, for example, 100 nm to 200 nm. The source electrode 15S and the drain electrode 15D are formed by, for example, a sputtering method, a vacuum evaporation method, or the like.
薄膜トランジスタ１１０の活性層１１の上面及び下面の少なくとも一方に、活性層１１よりもキャリア密度が小さい半導体薄膜を具備するようにしてもよい。 A semiconductor thin film having a lower carrier density than the active layer 11 may be provided on at least one of the upper surface and the lower surface of the active layer 11 of the thin film transistor 110.
このような薄膜トランジスタの一例を図３に示す。
図３の薄膜トランジスタ１１０Ａは、活性層１１の下面及び上面の両方にキャリア密度が小さい半導体薄膜１１Ａ及び１１Ｂを有するものである。
半導体薄膜１１Ａ及び１１Ｂとしては、例えば、ＩｎＧａＡｌ酸化物（ＩＧＡ）でキャリア濃度の大きな膜を挙げることができる。また、半導体薄膜１１Ａ及び１１Ｂは、活性層１１と同様に、例えば、スパッタリング法、ＡＬＤ法、真空蒸着法等で成膜される。
An example of such a thin film transistor is shown in FIG.
The thin film transistor 110A in FIG. 3 has semiconductor thin films 11A and 11B with low carrier density on both the lower and upper surfaces of the active layer 11.
Examples of the semiconductor thin films 11A and 11B include films of InGaAl oxide (IGA) with a high carrier concentration. Further, like the active layer 11, the semiconductor thin films 11A and 11B are formed by, for example, a sputtering method, an ALD method, a vacuum evaporation method, or the like.
本発明の薄膜トランジスタとしてはこのような構造に限定されず、図４～図６に示すような構造の薄膜トランジスタとしてもよい。 The thin film transistor of the present invention is not limited to such a structure, but may be a thin film transistor having a structure as shown in FIGS. 4 to 6.
図４の薄膜トランジスタ１１０Ｂは、活性層１１の下面にゲート電極１３が設けられた構造であり、基板１０上にゲート電極１３、ゲート絶縁膜１２及び活性層１１と積層された構造を有し、ソース電極１５Ｓ及びドレイン電極１５Ｄは、ゲート絶縁膜１２及び活性層１１上から引き出されている。 The thin film transistor 110B in FIG. 4 has a structure in which a gate electrode 13 is provided on the lower surface of an active layer 11, a structure in which the gate electrode 13, a gate insulating film 12, and an active layer 11 are stacked on a substrate 10, and a source The electrode 15S and the drain electrode 15D are drawn out from above the gate insulating film 12 and the active layer 11.
図５の薄膜トランジスタ１１０Ｃは、図４の薄膜トランジスタ１１０Ｂのゲート絶縁膜１２及び活性層１１の上にエッチングストップ層１６を設けた構造を有する。 The thin film transistor 110C in FIG. 5 has a structure in which an etching stop layer 16 is provided on the gate insulating film 12 and the active layer 11 of the thin film transistor 110B in FIG.
図６の薄膜トランジスタ１１０Ｄは、デュアルゲートタイプＴＦＴであり、活性層１１の下面側にゲート絶縁層１２Ａを介してボトムゲート電極１３Ａを有し、上面側にゲート絶縁層１２Ｂを介してトップゲート電極１３Ｂを具備するものであり、ソース電極１５Ｓ及びドレイン電極１５Ｄは、活性層１１に連続して設けられたｎ-層１１Ａ、すなわち、Ｎ型不純物濃度の薄いＮ型層を介して引き出されている。 The thin film transistor 110D in FIG. 6 is a dual gate type TFT, and has a bottom gate electrode 13A on the lower surface side of the active layer 11 via a gate insulating layer 12A, and a top gate electrode 13B on the upper surface side via a gate insulating layer 12B. The source electrode 15S and drain electrode 15D are drawn out through the n- layer 11A provided continuously to the active layer 11, that is, the N-type layer with a low concentration of N-type impurities.
なお、以上説明した具体例は横型トランジスタを例示したいが、これらに限定されず、縦型トランジスタであってもよいことは言うまでもない。 Note that although the specific example described above is a horizontal transistor, the present invention is not limited to these, and it goes without saying that a vertical transistor may also be used.
［半導体デバイス１－１６］
下記表に示す組成の各種酸化物半導体薄膜を用いて、図６に示すエッチングストップ層（ＥＳＬ）を有するＥＳＬタイプの薄膜トランジスタを製造した。酸化膜半導体薄膜は、活性層として利用した。
[Semiconductor device 1-16]
An ESL type thin film transistor having an etching stop layer (ESL) shown in FIG. 6 was manufactured using various oxide semiconductor thin films having compositions shown in the table below. An oxide semiconductor thin film was used as an active layer.
下記表に示す組成の酸化物半導体薄膜は、Ｉｎ２Ｏ３、Ｇａ２Ｏ３、およびＡｌ２Ｏ３のスパッタリングターゲットを用い、マルチカソードで各種組成のＩｎ-Ｇａ-Ａｌ-Ｏ薄膜を成膜した。 Oxide semiconductor thin films with the compositions shown in the table below are formed by forming In-Ga-Al-O thin films with various compositions using a multi-cathode using sputtering targets of In 2 O 3 , Ga 2 O 3 , and Al 2 O 3 did.
図５のＥＳＬタイプの半導体デバイスは、以下の手順で製造した。
まず、基板１０上にゲート電極用金属としてＭｏ層を成膜し、パターニングしてゲート電極１３を形成した。
The ESL type semiconductor device shown in FIG. 5 was manufactured using the following procedure.
First, a Mo layer was formed as a gate electrode metal on the substrate 10 and patterned to form the gate electrode 13.
次いで、ゲート絶縁膜１３として、ＳｉＯ（上）／ＳｉＮ（下）の積層膜を成膜した。 Next, a laminated film of SiO (top)/SiN (bottom) was formed as the gate insulating film 13.
次いで、上述したとおり、各種組成の酸化物半導体薄膜（表1のサンプル１－１６）からなる活性層１１を成膜し、４００℃でアニールして、リン酸系エッチャントを用いてウェットエッチングによりパターニングした。 Next, as described above, an active layer 11 consisting of oxide semiconductor thin films of various compositions (Samples 1-16 in Table 1) is formed, annealed at 400° C., and patterned by wet etching using a phosphoric acid-based etchant. did.
次に、ＥＳＬとして、ＣＶＤによりＳｉＯｘを成膜し、エッチングストップ層１６とした。このＣＶＤ成膜プロセスでは３００℃程度の加熱状態となり、この工程により、活性層１１を形成する酸化物半導体は還元処理される。 Next, as an ESL, a film of SiOx was formed by CVD to form an etching stop layer 16. In this CVD film-forming process, the heating state is about 300° C., and the oxide semiconductor forming the active layer 11 is reduced through this step.
この後、エッチングストップ層１６をパターニングし、ソースドレイン用金属膜としてＴｉを成膜し、パターニングし、次いで、保護膜（パッシベーション）１４を成膜し、アニールした後、保護膜１４をパターニングし、最後にソース電極１５Ｓ、ドレイン電極１５Ｄを形成した。 After that, the etching stop layer 16 is patterned, a Ti film is formed as a source/drain metal film, patterned, a protective film (passivation) 14 is formed, and after annealing, the protective film 14 is patterned, Finally, a source electrode 15S and a drain electrode 15D were formed.
（サンプル１－１７）
表１の組成を有するサンプル１－１７について、ＣＶＤによるＳｉＯｘ成膜後のホール移動度とキャリア濃度を測定した。
(Sample 1-17)
For sample 1-17 having the composition shown in Table 1, the hole mobility and carrier concentration were measured after the SiOx film was formed by CVD.
具体的には、ガラス基板に成膜した酸化物半導体膜５０ｎｍ上にＳｉＯ１００ｎｍをＣＶＤで成膜した後、７ｍｍ角にカットして、４隅をドライエッチング装置にてエッチングし、ホール効果測定用サンプルとした。 Specifically, a 100 nm thick film of SiO was formed by CVD on a 50 nm thick oxide semiconductor film formed on a glass substrate, and then cut into 7 mm squares, and the four corners were etched using a dry etching device to obtain a sample for Hall effect measurement. And so.
ホール効果測定用サンプルを比抵抗/ホール測定システム(ResiTest8400AC；東陽テクニカ社製）にセットし、室温においてホール効果を評価し、キャリア密度及び移動度を測定した。
結果は表１に示す。
The sample for Hall effect measurement was set in a resistivity/Hall measurement system (ResiTest8400AC; manufactured by Toyo Technica), the Hall effect was evaluated at room temperature, and the carrier density and mobility were measured.
The results are shown in Table 1.
この結果、サンプル１、２、５～１１及び１５の酸化物半導体薄膜は、キャリア濃度が１×１０１８ｃｍ－３以下と低く、ホール移動度が１ｃｍ２／Ｖｓ以上となることがわかった。
また、特に、サンプル１、５、７～１１酸化物半導体薄膜は、特に好ましいことがわかった。
一方、サンプル３、４は絶縁体となり、サンプル１２、１４は、ホール移動度が１ｃｍ２／Ｖｓより小さくなり、サンプル１３は、キャリア濃度が１×１０１８ｃｍ－３より大きく、それぞれ好ましくなかった。
As a result, it was found that the oxide semiconductor thin films of Samples 1, 2, 5 to 11, and 15 had a low carrier concentration of 1×10 18 cm −3 or less and a hole mobility of 1 cm 2 /Vs or more.
In addition, it was found that the oxide semiconductor thin films of Samples 1, 5, 7 to 11 were particularly preferable.
On the other hand, samples 3 and 4 were insulators, samples 12 and 14 had hole mobilities smaller than 1 cm 2 /Vs, and sample 13 had a carrier concentration larger than 1×10 18 cm -3 , which were unfavorable. .
（半導体デバイス８）
サンプル８の酸化物半導体薄膜を活性層とする図６の構造の半導体デバイス８について、ゲート電圧とドレイン電流との関係を示す伝達特性を測定した
活性層１１の上にＣＶＤにより設けたＳｉＯからなるゲート絶縁層１２Ｂの成膜温度は３００℃とした。
閾値電圧（ドレイン電流が１ｎＡとなるときのゲート電圧）はＡ～Ｄの４箇所で測定した。結果は図７に示すとおり、何れも閾値電圧は－０．５～３Ｖであり、ネガティブシフトしていないことが確認された。
(Semiconductor device 8)
The transfer characteristics showing the relationship between gate voltage and drain current were measured for the semiconductor device 8 having the structure shown in FIG. 6 with the oxide semiconductor thin film of sample 8 as the active layer. The film formation temperature of the gate insulating layer 12B was 300°C.
The threshold voltage (gate voltage when the drain current becomes 1 nA) was measured at four locations A to D. As the results are shown in FIG. 7, the threshold voltages were −0.5 to 3 V in all cases, and it was confirmed that there was no negative shift.
（比較半導体デバイス）
活性層をＩＧＺＯ１１１（Ｉｎ：Ｇａ：Ｚｎ＝33.3：33.3：33.3）と、ＣＶＤの成膜温度を２７０℃と低くした以外は、同様にしたデバイスを作成し、閾値電圧を測定した。結果は図８に示すとおり、スイッチング動作しないノーマリーオン状態となり、閾値電圧が測定できなかった。
(Comparison semiconductor device)
A similar device was fabricated, except that the active layer was IGZO111 (In:Ga:Zn=33.3:33.3:33.3) and the CVD film formation temperature was lowered to 270°C, and the threshold voltage was measured. As shown in FIG. 8, the result was a normally-on state in which switching did not occur, and the threshold voltage could not be measured.
図７，図８の結果より、本発明の酸化物半導体を用いた半導体デバイスは、高温処理をしても閾値電圧がネガティブシフトせず、耐熱性に優れていることがわかった。 From the results shown in FIGS. 7 and 8, it was found that the semiconductor device using the oxide semiconductor of the present invention did not undergo a negative shift in threshold voltage even when subjected to high temperature treatment, and had excellent heat resistance.
（スパッタリングターゲット）
上記表１のサンプル８の組成となるように、酸化インジウム、酸化ガリウム、酸化アルミニウムを秤量し、ボールミルを用いて混合した。混合された粒末を、大気下で、１０００℃で１０時間保持することにより焼結し、焼結体を得た。
(sputtering target)
Indium oxide, gallium oxide, and aluminum oxide were weighed and mixed using a ball mill so as to have the composition of Sample 8 in Table 1 above. The mixed powder was sintered by holding it at 1000° C. for 10 hours in the atmosphere to obtain a sintered body.
実施例において酸化インジウム、酸化ガリウム、酸化アルミニウムを原料とし、大気中で焼結することで、９６．４％の相対密度を持った焼結体が得られた。この焼結体は絶縁体であるが、ＲＦスパッタリングによって本発明の酸化物半導体薄膜の成膜が可能である。 In the example, a sintered body having a relative density of 96.4% was obtained by using indium oxide, gallium oxide, and aluminum oxide as raw materials and sintering in the atmosphere. Although this sintered body is an insulator, the oxide semiconductor thin film of the present invention can be formed by RF sputtering.
１０ 基板
１１ 活性層
１１Ａ，Ｂ 半導体薄膜
１２ ゲート絶縁膜
１２Ａ ゲート絶縁層
１２Ｂ ゲート絶縁層
１３ ゲート電極
１３Ａ ボトムゲート電極
１３Ｂ トップゲート電極
１４ 保護膜
１５Ｄ ドレイン電極
１５Ｓ ソース電極
１６ エッチングストップ層
１１０ 薄膜トランジスタ
10 Substrate 11 Active layer 11A, B Semiconductor thin film 12 Gate insulating film 12A Gate insulating layer 12B Gate insulating layer 13 Gate electrode 13A Bottom gate electrode 13B Top gate electrode 14 Protective film 15D Drain electrode 15S Source electrode 16 Etching stop layer 110 Thin film transistor
Claims (11)
前記酸化物のＸ、Ｙ及びＺの組成比は、Ｉｎ、Ｇａ及びＡｌの３成分系相図の下記Ａ点とＢ点を結ぶ線分、下記Ｂ点とＥ点とを結ぶ線分、下記Ｅ点とＤ点とを結ぶ線分、及び下記Ｄ点と下記Ａ点とを結ぶ線分とで囲まれる領域の組成比である
酸化物半導体薄膜。
組成：ＩｎＸＧａＹＡｌＺ
Ａ点：Ｉｎ１０Ｇａ９0Ａｌ０
Ｂ点：Ｉｎ３０Ｇａ３０Ａｌ４０
Ｅ点：Ｉｎ ４０ Ｇａ ４５ Ａｌ １５
Ｄ点：Ｉｎ４５Ｇａ５５Ａｌ０ It is composed of an oxide semiconductor whose main component is an oxide containing indium, gallium, and aluminum with the following composition,
The composition ratios of X, Y, and Z of the oxide are as follows: a line segment connecting points A and B below in the ternary phase diagram of In, Ga, and Al; a line segment connecting point B and E below; This is the composition ratio of the region surrounded by a line segment connecting point E and point D, and a line segment connecting point D below and point A below. Oxide semiconductor thin film.
Composition: In X Ga Y Al Z
Point A: In 10 Ga 90 Al 0
Point B: In 30 Ga 30 Al 40
Point E: In 40 Ga 45 Al 15
Point D: In 45 Ga 55 Al 0
請求項１記載の酸化物半導体薄膜。 The oxide semiconductor thin film according to claim 1, wherein the oxide semiconductor thin film has a carrier concentration of 1×10 18 cm −3 or less after high-temperature treatment at 300° C. or higher .
請求項１記載の酸化物半導体薄膜。 The oxide semiconductor thin film according to claim 1, wherein the oxide semiconductor thin film has a mobility of 1 cm 2 /Vs or more after high-temperature treatment at 300° C. or higher .
請求項１記載の酸化物半導体薄膜。 The oxide semiconductor thin film according to claim 1, wherein the oxide semiconductor thin film has an etching rate of 1 nm/sec or more when etched with a phosphoric acid-based etchant.
前記酸化物半導体薄膜の少なくとも一部として、請求項１～４のいずれか一項に記載の酸化物半導体薄膜を成膜する工程と、
前記酸化物半導体薄膜の酸化物半導体の還元処理を含む工程と、を具備する
半導体デバイスの製造方法。 A method for manufacturing a semiconductor device comprising an oxide semiconductor thin film, the method comprising:
forming the oxide semiconductor thin film according to any one of claims 1 to 4 as at least a part of the oxide semiconductor thin film;
A method of manufacturing a semiconductor device, comprising: a step of reducing an oxide semiconductor of the oxide semiconductor thin film.
前記酸化物のＸ、Ｙ及びＺの組成比は、Ｉｎ、Ｇａ及びＡｌの３成分系相図の下記Ａ点とＢ点を結ぶ線分、下記Ｂ点とＥ点とを結ぶ線分、下記Ｅ点とＤ点とを結ぶ線分、及び下記Ｄ点と下記Ａ点とを結ぶ線分とで囲まれる領域の組成比である
スパッタリングターゲット。
組成：ＩｎＸＧａＹＡｌＺ
Ａ点：Ｉｎ１０Ｇａ９０Ａｌ０
Ｂ点：Ｉｎ３０Ｇａ３０Ａｌ４０
Ｅ点：Ｉｎ ４０ Ｇａ ４５ Ａｌ １５
Ｄ点：Ｉｎ４５Ｇａ５５Ａｌ０ It is composed of an oxide sintered body whose main component is an oxide containing indium, gallium, and aluminum with the following composition,
The composition ratios of X, Y, and Z of the oxide are as follows: a line segment connecting points A and B below in the ternary phase diagram of In, Ga, and Al; a line segment connecting point B and E below; This is the composition ratio of the area surrounded by the line segment connecting point E and point D, and the line segment connecting point D below and point A below. Sputtering target.
Composition: In X Ga Y Al Z
Point A: In 10 Ga 90 Al 0
Point B: In 30 Ga 30 Al 40
Point E: In 40 Ga 45 Al 15
Point D: In 45 Ga 55 Al 0
相対密度が９０％以上である
請求項８に記載のスパッタリングターゲット。 In sputtering targets,
The sputtering target according to claim 8, having a relative density of 90% or more.
スパッタリングターゲットの製造方法。 The oxide sintered body according to claim 8 or 9, by mixing indium oxide powder, gallium oxide powder, and aluminum oxide powder to form a compact, and firing the compact at a temperature of 1100° C. or higher and 1650° C. or lower. A method for manufacturing a sputtering target.
スパッタリングターゲットの製造方法。
A precursor powder obtained by mixing oxides, hydroxides or carbonates of indium, gallium, and aluminum and calcining the mixture at 1000°C to 1500°C is molded into a molded body, and the molded body is heated at 1100°C to 1650°C. A method for producing a sputtering target, comprising: producing a sputtering target having the oxide sintered body according to claim 8 or 9 by firing.
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