JP7430482B2 - ライト動作方法 - Google Patents
ライト動作方法 Download PDFInfo
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- JP7430482B2 JP7430482B2 JP2018194291A JP2018194291A JP7430482B2 JP 7430482 B2 JP7430482 B2 JP 7430482B2 JP 2018194291 A JP2018194291 A JP 2018194291A JP 2018194291 A JP2018194291 A JP 2018194291A JP 7430482 B2 JP7430482 B2 JP 7430482B2
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- data
- parity
- memory
- cache memory
- main memory
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- 230000015654 memory Effects 0.000 claims description 419
- 238000000034 method Methods 0.000 claims description 23
- 230000003936 working memory Effects 0.000 description 15
- PCTMTFRHKVHKIS-BMFZQQSSSA-N (1s,3r,4e,6e,8e,10e,12e,14e,16e,18s,19r,20r,21s,25r,27r,30r,31r,33s,35r,37s,38r)-3-[(2r,3s,4s,5s,6r)-4-amino-3,5-dihydroxy-6-methyloxan-2-yl]oxy-19,25,27,30,31,33,35,37-octahydroxy-18,20,21-trimethyl-23-oxo-22,39-dioxabicyclo[33.3.1]nonatriaconta-4,6,8,10 Chemical compound C1C=C2C[C@@H](OS(O)(=O)=O)CC[C@]2(C)[C@@H]2[C@@H]1[C@@H]1CC[C@H]([C@H](C)CCCC(C)C)[C@@]1(C)CC2.O[C@H]1[C@@H](N)[C@H](O)[C@@H](C)O[C@H]1O[C@H]1/C=C/C=C/C=C/C=C/C=C/C=C/C=C/[C@H](C)[C@@H](O)[C@@H](C)[C@H](C)OC(=O)C[C@H](O)C[C@H](O)CC[C@@H](O)[C@H](O)C[C@H](O)C[C@](O)(C[C@H](O)[C@H]2C(O)=O)O[C@H]2C1 PCTMTFRHKVHKIS-BMFZQQSSSA-N 0.000 description 11
- 238000004891 communication Methods 0.000 description 8
- 238000010586 diagram Methods 0.000 description 6
- 229920001621 AMOLED Polymers 0.000 description 2
- 238000013500 data storage Methods 0.000 description 2
- 230000005540 biological transmission Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 230000007774 longterm Effects 0.000 description 1
- 238000010295 mobile communication Methods 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 230000001360 synchronised effect Effects 0.000 description 1
- 239000002699 waste material Substances 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
- G06F11/1068—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices in sector programmable memories, e.g. flash disk
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
- G06F11/1064—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices in cache or content addressable memories
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
- G06F12/023—Free address space management
- G06F12/0238—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
- G06F12/0246—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory in block erasable memory, e.g. flash memory
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0804—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with main memory updating
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/10—Providing a specific technical effect
- G06F2212/1032—Reliability improvement, data loss prevention, degraded operation etc
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/40—Specific encoding of data in memory or cache
- G06F2212/403—Error protection encoding, e.g. using parity or ECC codes
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/52—Protection of memory contents; Detection of errors in memory contents
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Quality & Reliability (AREA)
- Memory System Of A Hierarchy Structure (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
- Detection And Correction Of Errors (AREA)
Description
120、220、420:プロセッサ
160、260、460:メインメモリー
162、262:データ領域
164、264、464:パリティ領域
240,1150:キャッシュメモリー
242、342、440:データキャッシュメモリー
244、442:パリティキャッシュメモリー
320、322:タグ情報
450: ECCエンジン
462: データを貯蔵するための領域
464: パリティを貯蔵するための領域
1000: 電子システム
1101: メインプロペッサ
1200: ワーキングメモリー
1300: ストレージ装置
1400: 通信ブロック
1500: ユーザーインターフェース
1600: バス
Claims (1)
- メインメモリーに現在のデータをライトするためにコンピューティング装置により遂行される方法において、
前記現在のデータのライトが遂行される第1アドレスにより指示される前記メインメモリーの領域のデータが第1キャッシュメモリーにキャッシングされているか否かを判定する動作を含み、
前記第1アドレスにより指示される前記メインメモリーの前記領域の前記データが前記第1キャッシュメモリーにキャッシングされている場合において、前記方法は、
前記第1キャッシュメモリーに前記現在のデータを貯蔵する動作と、
前記現在のデータを基準サイズに変更して、前記第1キャッシュメモリーから前記メインメモリーに出力する動作を包含し、
前記現在のデータは前記基準サイズより小さいサイズであり、前記基準サイズは前記データ及びパリティを前記メインメモリーから送信及び受信するためのサイズと同一であり、前記方法は、
前記メインメモリーに出力する前記基準サイズに変更された前記現在のデータに対するパリティを生成する動作と、
その生成されたパリティを前記メインメモリーにライトする動作であって、
前記生成されたパリティのライトが遂行される第2アドレスにより指示される前記メインメモリーの領域のパリティが第2キャッシュメモリーにキャッシングされているか否かを判定し、
前記第2アドレスにより指示される前記メインメモリーの領域のパリティが前記第2キャッシュメモリーにキャッシングされている場合に、前記第2キャッシュメモリーに、前記生成されたパリティを貯蔵し、
前記生成されたパリティを前記基準サイズに変更して、前記第2キャッシュメモリーから前記メインメモリーに出力する動作と、をさらに包含する方法。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR10-2017-0142670 | 2017-10-30 | ||
KR1020170142670A KR102490104B1 (ko) | 2017-10-30 | 2017-10-30 | 데이터 보호를 사용하는 인-밴드 메모리에 액세스하기 위한 장치 및 방법 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2019083005A JP2019083005A (ja) | 2019-05-30 |
JP7430482B2 true JP7430482B2 (ja) | 2024-02-13 |
Family
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Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2018194291A Active JP7430482B2 (ja) | 2017-10-30 | 2018-10-15 | ライト動作方法 |
Country Status (5)
Country | Link |
---|---|
US (1) | US10783033B2 (ja) |
JP (1) | JP7430482B2 (ja) |
KR (1) | KR102490104B1 (ja) |
CN (1) | CN109726147B (ja) |
DE (1) | DE102018121994A1 (ja) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US11194494B2 (en) * | 2020-04-24 | 2021-12-07 | Western Digital Technologies, Inc. | Storage devices hiding parity swapping behavior |
US11055176B1 (en) * | 2020-04-24 | 2021-07-06 | Western Digital Technologies, Inc. | Storage devices hiding parity swapping behavior |
TWI755739B (zh) * | 2020-05-26 | 2022-02-21 | 慧榮科技股份有限公司 | 記憶體控制器與資料處理方法 |
Citations (3)
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JP2008158779A (ja) | 2006-12-22 | 2008-07-10 | Toshiba Corp | 情報処理装置、ecc制御装置およびecc制御方法 |
WO2013132806A1 (ja) | 2012-03-06 | 2013-09-12 | 日本電気株式会社 | 不揮発性論理集積回路と不揮発性レジスタの誤りビットの訂正方法 |
JP6115740B1 (ja) | 2015-12-17 | 2017-04-19 | ウィンボンド エレクトロニクス コーポレーション | 半導体記憶装置 |
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-
2017
- 2017-10-30 KR KR1020170142670A patent/KR102490104B1/ko active IP Right Grant
-
2018
- 2018-05-16 US US15/981,429 patent/US10783033B2/en active Active
- 2018-09-10 DE DE102018121994.6A patent/DE102018121994A1/de active Pending
- 2018-10-10 CN CN201811176645.5A patent/CN109726147B/zh active Active
- 2018-10-15 JP JP2018194291A patent/JP7430482B2/ja active Active
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JP2008158779A (ja) | 2006-12-22 | 2008-07-10 | Toshiba Corp | 情報処理装置、ecc制御装置およびecc制御方法 |
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Also Published As
Publication number | Publication date |
---|---|
KR102490104B1 (ko) | 2023-01-19 |
US20190129793A1 (en) | 2019-05-02 |
CN109726147A (zh) | 2019-05-07 |
DE102018121994A1 (de) | 2019-05-02 |
KR20190048121A (ko) | 2019-05-09 |
JP2019083005A (ja) | 2019-05-30 |
CN109726147B (zh) | 2024-06-18 |
US10783033B2 (en) | 2020-09-22 |
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