JP7417498B2 - 半導体装置及びその製造方法 - Google Patents
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- 239000004065 semiconductor Substances 0.000 title claims description 86
- 238000004519 manufacturing process Methods 0.000 title claims description 18
- 238000000034 method Methods 0.000 claims description 22
- 239000012535 impurity Substances 0.000 claims description 20
- 238000005530 etching Methods 0.000 claims description 6
- 108091006146 Channels Proteins 0.000 description 10
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 8
- 238000007254 oxidation reaction Methods 0.000 description 8
- 229910052814 silicon oxide Inorganic materials 0.000 description 8
- 238000005468 ion implantation Methods 0.000 description 7
- 238000009792 diffusion process Methods 0.000 description 4
- 238000001459 lithography Methods 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 238000001020 plasma etching Methods 0.000 description 4
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 230000003647 oxidation Effects 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 238000002513 implantation Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 229910002601 GaN Inorganic materials 0.000 description 1
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 1
- 102000004129 N-Type Calcium Channels Human genes 0.000 description 1
- 108090000699 N-Type Calcium Channels Proteins 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
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Description
前記埋め込み電極部内に設けられ、前記メサ部の第1の側壁の一部を形成する前記第2半導体領域の側面に対向するゲート電極と、前記埋め込み電極部内に設けられ、前記ゲート電極よりも下方まで延びる第1のフィールドプレート電極と、前記ゲート電極と、前記第2半導体領域の前記側面との間に設けられたゲート絶縁膜と、前記半導体構造部上に設けられた主部と、前記主部から前記埋め込み電極部内に延び前記メサ部の前記第1の側壁の反対側の第2の側壁に達し、前記第2半導体領域および前記第4半導体領域に接するコンタクト部とを有する上部電極と、を備えている。
図1は、第1実施形態の半導体装置1の模式断面図である。
図2は、図1におけるA-A’断面図である。
図9は、第2実施形態の半導体装置2の模式断面図である。
図10は、図9におけるB-B’断面図である。
図12は、第3実施形態の半導体装置3の模式断面図である。
図13は、図12におけるC-C’断面図である。
図18は、第4実施形態の半導体装置4の模式断面図である。
図19は、図18におけるD-D’断面図である。
Claims (7)
- 複数の埋め込み電極部と、前記複数の埋め込み電極部の間に設けられ前記埋め込み電極部に隣接するメサ部とを有する半導体構造部であって、前記メサ部は、第1導電型の第1半導体領域と、前記第1半導体領域上に設けられた第2導電型の第2半導体領域と、前記第2半導体領域上に設けられた第1導電型の第3半導体領域と、前記埋め込み電極部と前記第2半導体領域との間に設けられ、前記第2半導体領域よりも第2導電型不純物濃度が高い第2導電型の第4半導体領域とを有する、半導体構造部と、
前記埋め込み電極部内に設けられ、前記メサ部の第1の側壁の一部を形成する前記第2半導体領域の側面に対向するゲート電極と、
前記埋め込み電極部内に設けられ、前記ゲート電極よりも下方まで延びる第1のフィールドプレート電極と、
前記ゲート電極と、前記第2半導体領域の前記側面との間に設けられたゲート絶縁膜と、
前記半導体構造部上に設けられた主部と、前記主部から前記埋め込み電極部内に延び前記メサ部の前記第1の側壁の反対側の第2の側壁に達し、前記第2半導体領域および前記第4半導体領域に接するコンタクト部とを有する上部電極と、
を備えた半導体装置。 - 第1の埋め込み電極部と第2の埋め込み電極部と第3の埋め込み電極部と第4の埋め込み電極部とを含む4以上の前記埋め込み電極部と、第1のメサ部と第2のメサ部と第3のメサ部とを含む3以上の前記メサ部が設けられ、
前記第1のメサ部は、前記第1の埋め込み電極部と前記第2の埋め込み電極部との間に設けられ、前記第1の埋め込み電極部と前記第2の埋め込み電極部に隣接し、
前記第2のメサ部は、前記第2の埋め込み電極部と前記第3の埋め込み電極部との間に設けられ、前記第2の埋め込み電極部と前記第3の埋め込み電極部に隣接し、
前記第3のメサ部は、前記第3の埋め込み電極部と前記第4の埋め込み電極部との間に設けられ、前記第3の埋め込み電極部と前記第4の埋め込み電極部に隣接し、
前記第1の埋め込み電極部に、前記第1のメサ部の第1の側壁に対向する前記ゲート電極と、前記第1のフィールドプレート電極とが設けられ、
前記第2の埋め込み電極部に、前記第1のメサ部の第2の側壁に接する前記コンタクト部と、前記第2のメサ部の第2の側壁に接する前記コンタクト部と、前記コンタクト部よりも下方まで延びる第2のフィールドプレート電極とが設けられ、
前記第3の埋め込み電極部に、前記第2のメサ部の第1の側壁に対向する前記ゲート電極と、前記第3のメサ部の第1の側壁に対向する前記ゲート電極と、前記第1のフィールドプレート電極とが設けられ、
前記第4の埋め込み電極部に、前記第3のメサ部の第2の側壁に接する前記コンタクト部と、前記コンタクト部よりも下方まで延びる第3のフィールドプレート電極とが設けられている請求項1記載の半導体装置。 - 前記第1のメサ部の前記第2の側壁に接する前記コンタクト部と、前記第2のメサ部の前記第2の側壁に接する前記コンタクト部は、前記第2の埋め込み電極部で互いにつながっている請求項2記載の半導体装置。
- 前記第2の埋め込み電極部に設けられた前記第2のフィールドプレート電極は、前記コンタクト部と接する請求項3記載の半導体装置。
- 1つの前記埋め込み電極部内に、前記ゲート電極と前記コンタクト部の両方が設けられている請求項1記載の半導体装置。
- 前記コンタクト部が接する前記第4半導体領域の側面は、前記第1半導体領域の側面に対して傾斜している請求項1~5のいずれか1つに記載の半導体装置。
- 半導体層に複数のトレンチを形成するとともに、前記複数のトレンチの間に前記半導体層のメサ部を形成する工程と、
前記トレンチの下部にフィールドプレート電極を形成する工程と、
前記メサ部の第1の側壁に対向するように、前記フィールドプレート電極が形成された前記トレンチの上部にゲート電極を形成する工程と、
前記メサ部および前記ゲート電極を覆う絶縁膜を形成する工程と、
前記絶縁膜をエッチングし、前記メサ部の前記第1の側壁の反対側の第2の側壁に達するコンタクト用トレンチを形成する工程と、
前記コンタクト用トレンチ内に、前記メサ部の前記第2の側壁に接する電極を形成する工程と、
を備えた半導体装置の製造方法。
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US20120319199A1 (en) | 2011-06-20 | 2012-12-20 | Maxpower Semiconductor, Inc. | Trench Gated Power Device With Multiple Trench Width and its Fabrication Process |
US20150041962A1 (en) | 2013-08-09 | 2015-02-12 | Infineon Technologies Ag | Semiconductor Device with Cell Trench Structures and Contacts and Method of Manufacturing a Semiconductor Device |
US20170104095A1 (en) | 2015-10-07 | 2017-04-13 | International Onizuka Electronics Limited | Vdmos and method for making the same |
US20180366569A1 (en) | 2016-06-10 | 2018-12-20 | Maxpower Semiconductor Inc. | Trench-Gated Heterostructure and Double-Heterostructure Active Devices |
US20180204918A1 (en) | 2017-01-19 | 2018-07-19 | Sii Semiconductor Corporation | Semiconductor device and method of manufacturing the same |
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