JP7387003B2 - 半導体構造及び半導体構造の作製方法 - Google Patents
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- 239000004065 semiconductor Substances 0.000 title claims description 72
- 238000000034 method Methods 0.000 title claims description 31
- 238000004519 manufacturing process Methods 0.000 title claims description 27
- 239000010410 layer Substances 0.000 claims description 423
- 238000004891 communication Methods 0.000 claims description 40
- 229910052710 silicon Inorganic materials 0.000 claims description 32
- 239000010703 silicon Substances 0.000 claims description 32
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 30
- 239000000758 substrate Substances 0.000 claims description 28
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims description 22
- 229910021389 graphene Inorganic materials 0.000 claims description 22
- 239000004020 conductor Substances 0.000 claims description 18
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 15
- 229910052802 copper Inorganic materials 0.000 claims description 15
- 239000010949 copper Substances 0.000 claims description 15
- 239000002346 layers by function Substances 0.000 claims description 14
- 238000010586 diagram Methods 0.000 description 18
- 229910052581 Si3N4 Inorganic materials 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 238000003825 pressing Methods 0.000 description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 3
- 229910052721 tungsten Inorganic materials 0.000 description 3
- 239000010937 tungsten Substances 0.000 description 3
- 229910004298 SiO 2 Inorganic materials 0.000 description 2
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 2
- 238000000231 atomic layer deposition Methods 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 238000005240 physical vapour deposition Methods 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- 230000006978 adaptation Effects 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 238000005338 heat storage Methods 0.000 description 1
- 238000011065 in-situ storage Methods 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 239000012774 insulation material Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 229910052594 sapphire Inorganic materials 0.000 description 1
- 239000010980 sapphire Substances 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5226—Via connections in a multilevel interconnection structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
- H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53276—Conductive materials containing carbon, e.g. fullerenes
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Description
本開示は、2021年03月10日に提出された出願番号が202110265111.5であり、名称が「半導体構造及び半導体構造の作製方法」である中国特許出願の優先権を主張し、該中国特許出願の全てが参照によって本開示に組み込まれる。
ベースと、
ベース内に位置し、第1接続層、第2接続層及び第3接続層を含む連通部であって、第2接続層が第1接続層上に位置し、第3接続層が第2接続層上に位置する連通部と、を含み、
第1接続層、第2接続層及び第3接続層は異なる導電材料を含み、第2接続層及び第3接続層の熱膨張係数はいずれも第1接続層の熱膨張係数よりも小さい。
ベースと、
ベース内に位置し、第1接続層、第2接続層及び第3接続層を含む連通部であって、第2接続層が第1接続層上に位置し、第3接続層が第2接続層上に位置する連通部と、を含み、
第2接続層及び第3接続層はいずれもグラフェンを含み、第2接続層及び第3接続層の熱膨張係数はいずれも第1接続層の熱膨張係数よりも小さい。
基体を提供するステップと、
基体に連通部を形成するステップであって、連通部は第1接続層、第2接続層及び第3接続層を含み、第2接続層は第1接続層上に形成され、第3接続層は第2接続層上に形成されるステップと、を含み、
第1接続層、第2接続層及び第3接続層は異なる導電材料を含み、第2接続層及び第3接続層の熱膨張係数はいずれも第1接続層の熱膨張係数よりも小さい。
11:シリコン基板
111:機能層
12:絶縁層
13:基体
14:開口
15:第1絶縁層
16:開孔
17:第2絶縁層
18:第3絶縁層
19:第1初期接続層
20:導電部
21:連通部
211:第1接続層
212:第2接続層
213:第3接続層
22:第1導電層
30:第2導電層
31:接続柱
32:第2初期接続層
33:第3初期接続層
Claims (14)
- 半導体構造であって、
ベースと、
前記ベース内に位置し、第1接続層、第2接続層及び第3接続層を含む連通部であって、前記第2接続層は前記第1接続層上に位置し、前記第3接続層は前記第2接続層上に位置する連通部と、を含み、
前記第1接続層、前記第2接続層及び前記第3接続層は異なる導電材料を含み、前記第2接続層及び前記第3接続層の熱膨張係数はいずれも前記第1接続層の熱膨張係数よりも小さく、前記第2接続層の熱膨張係数は前記第3接続層の熱膨張係数よりも小さい、半導体構造。 - 前記第2接続層又は前記第3接続層はグラフェンを含み、前記第1接続層は銅を含み、又は、
前記第2接続層は前記第1接続層内に位置し、前記第3接続層は前記第1接続層内に位置する
請求項1に記載の半導体構造。 - 前記第2接続層及び前記第3接続層は、前記ベースに垂直な方向での投影が重なり、
前記第3接続層の頂端は前記第1接続層の頂端と面一になる
請求項2に記載の半導体構造。 - 前記第1接続層及び前記第3接続層は、前記ベースに垂直な方向での投影が重なる
請求項2に記載の半導体構造。 - 前記第3接続層の底端は、前記第2接続層の頂端及び前記第1接続層の頂端と面一になる
請求項2に記載の半導体構造。 - 前記第1接続層、前記第2接続層及び前記第3接続層は、前記ベースに垂直な方向での投影が重なる
請求項1に記載の半導体構造。 - 前記ベースは、
シリコン基板であって、前記第2接続層の底端は前記シリコン基板の上面よりも低いシリコン基板と、
前記シリコン基板の上面を覆い、前記連通部の外面を覆う絶縁層と、を含む
請求項1に記載の半導体構造。 - 前記シリコン基板内に機能層が形成されており、前記第2接続層の底端は前記機能層の下面よりも低く、又は、
前記第2接続層の頂端は前記シリコン基板の上面よりも高く、又は、
前記第2接続層は前記シリコン基板に入り込む深さが1μm以上である
請求項7に記載の半導体構造。 - 前記連通部はシリコン貫通ビアであり、又は、
前記第2接続層の直径は200nm~10μmであり、前記第2接続層の深さは1μm~20μmである
請求項1に記載の半導体構造。 - 半導体構造であって、
ベースと、
ベース内に位置し、第1接続層、第2接続層及び第3接続層を含む連通部であって、前記第2接続層は前記第1接続層上に位置し、前記第3接続層は前記第2接続層上に位置する連通部と、を含み、
前記第2接続層及び前記第3接続層はいずれもグラフェンを含み、前記第2接続層及び前記第3接続層の熱膨張係数はいずれも前記第1接続層の熱膨張係数よりも小さく、前記第2接続層の熱膨張係数は前記第3接続層の熱膨張係数よりも小さい、半導体構造。 - 半導体構造の作製方法であって、
基体を提供するステップと、
前記基体に連通部を形成するステップであって、前記連通部は第1接続層、第2接続層及び第3接続層を含み、前記第2接続層は前記第1接続層上に形成され、前記第3接続層は前記第2接続層上に形成されるステップと、を含み、
前記第1接続層、前記第2接続層及び前記第3接続層は異なる導電材料を含み、前記第2接続層及び前記第3接続層の熱膨張係数はいずれも前記第1接続層の熱膨張係数よりも小さく、前記第2接続層の熱膨張係数は前記第3接続層の熱膨張係数よりも小さい、半導体構造の作製方法。 - 前記第2接続層又は前記第3接続層はグラフェンを含み、前記第1接続層は銅を含む
請求項11に記載の半導体構造の作製方法。 - 前記第1接続層には開口が形成されており、前記第2接続層及び前記第3接続層は順次、前記開口内に形成される
請求項11又は12に記載の半導体構造の作製方法。 - 前記第1接続層、前記第2接続層及び前記第3接続層は順次、前記基体内に形成され、
前記第1接続層、前記第2接続層及び前記第3接続層は、前記基体に垂直な方向での投影が重なる
請求項11又は12に記載の半導体構造の作製方法。
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CN202110265111.5 | 2021-03-10 | ||
CN202110265111.5A CN115084000A (zh) | 2021-03-10 | 2021-03-10 | 半导体结构及半导体结构的制作方法 |
PCT/CN2021/112594 WO2022188358A1 (zh) | 2021-03-10 | 2021-08-13 | 半导体结构及半导体结构的制作方法 |
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JP2013247139A (ja) | 2012-05-23 | 2013-12-09 | Ps4 Luxco S A R L | 半導体装置及びその製造方法 |
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JP2020109452A (ja) | 2019-01-07 | 2020-07-16 | 株式会社ジャパンディスプレイ | 表示装置及び表示装置の製造方法 |
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US20140145332A1 (en) * | 2012-11-26 | 2014-05-29 | Globalfoundries Inc. | Methods of forming graphene liners and/or cap layers on copper-based conductive structures |
US9466569B2 (en) * | 2014-11-12 | 2016-10-11 | Freescale Semiconductor, Inc. | Though-substrate vias (TSVs) and method therefor |
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Patent Citations (7)
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JP2008135482A (ja) | 2006-11-27 | 2008-06-12 | Matsushita Electric Works Ltd | 貫通孔配線構造およびその形成方法 |
JP2009111061A (ja) | 2007-10-29 | 2009-05-21 | Elpida Memory Inc | 半導体装置およびその製造方法 |
JP2013247139A (ja) | 2012-05-23 | 2013-12-09 | Ps4 Luxco S A R L | 半導体装置及びその製造方法 |
JP2015005659A (ja) | 2013-06-21 | 2015-01-08 | 独立行政法人産業技術総合研究所 | 導電構造及びその製造方法、電子装置及びその製造方法 |
US20150115462A1 (en) | 2013-10-31 | 2015-04-30 | Nanya Technology Corporation | Integrated circuit device |
JP2019503580A (ja) | 2016-12-23 | 2019-02-07 | 蘇州能訊高能半導体有限公司Dynax Semiconductor,Inc. | 半導体チップ、半導体ウエハー及び半導体ウエハーの製造方法 |
JP2020109452A (ja) | 2019-01-07 | 2020-07-16 | 株式会社ジャパンディスプレイ | 表示装置及び表示装置の製造方法 |
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JP2023521264A (ja) | 2023-05-24 |
EP4086945A1 (en) | 2022-11-09 |
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