JP7262322B2 - 半導体装置 - Google Patents
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- 239000004065 semiconductor Substances 0.000 title claims description 110
- 230000015654 memory Effects 0.000 claims description 185
- 239000000758 substrate Substances 0.000 claims description 24
- 239000010410 layer Substances 0.000 description 61
- 229910052581 Si3N4 Inorganic materials 0.000 description 14
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 14
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 12
- 239000011229 interlayer Substances 0.000 description 12
- 238000000034 method Methods 0.000 description 12
- 229910052814 silicon oxide Inorganic materials 0.000 description 12
- 238000009792 diffusion process Methods 0.000 description 11
- 230000000052 comparative effect Effects 0.000 description 8
- 238000002347 injection Methods 0.000 description 8
- 239000007924 injection Substances 0.000 description 8
- 238000002955 isolation Methods 0.000 description 8
- 230000004048 modification Effects 0.000 description 6
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- 239000008186 active pharmaceutical agent Substances 0.000 description 5
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- 239000002784 hot electron Substances 0.000 description 5
- 230000006870 function Effects 0.000 description 4
- 239000012535 impurity Substances 0.000 description 4
- 229910021332 silicide Inorganic materials 0.000 description 4
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 238000009825 accumulation Methods 0.000 description 2
- 239000000969 carrier Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 230000001590 oxidative effect Effects 0.000 description 2
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- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 2
- 229910010271 silicon carbide Inorganic materials 0.000 description 2
- 238000009751 slip forming Methods 0.000 description 2
- 125000006850 spacer group Chemical group 0.000 description 2
- 230000005641 tunneling Effects 0.000 description 2
- QNRATNLHPGXHMA-XZHTYLCXSA-N (r)-(6-ethoxyquinolin-4-yl)-[(2s,4s,5r)-5-ethyl-1-azabicyclo[2.2.2]octan-2-yl]methanol;hydrochloride Chemical compound Cl.C([C@H]([C@H](C1)CC)C2)CN1[C@@H]2[C@H](O)C1=CC=NC2=CC=C(OCC)C=C21 QNRATNLHPGXHMA-XZHTYLCXSA-N 0.000 description 1
- 229910005883 NiSi Inorganic materials 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000000470 constituent Substances 0.000 description 1
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- 238000005530 etching Methods 0.000 description 1
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- 229910021334 nickel silicide Inorganic materials 0.000 description 1
- RUFLMLWJRZAWLJ-UHFFFAOYSA-N nickel silicide Chemical compound [Ni]=[Si]=[Ni] RUFLMLWJRZAWLJ-UHFFFAOYSA-N 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
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Description
次に、不揮発性メモリの動作例について、図8を参照して説明する。
図9に本発明者が検討した比較例の半導体装置の平面図を示す。図1に示す本実施の形態のメモリセルアレイにおいて、1つのプラグSCは2つのメモリセルのみに接続されており、3以上のメモリセルには接続されていない。これに対し、図9に示すメモリセルアレイの平面レイアウトでは、図1に示す平面レイアウトと異なり、各メモリセルMC1~MC4のソース領域に接続された1つのプラグ(ソースコンタクトプラグ)SC1がY方向に延在しており、Y方向に並ぶ3以上のメモリセルのそれぞれが接続されている。
図7に示すように、ダミーのフィンは形成されていなくてもよい。図7は、本実施の形態の半導体装置を示す平面図である。
CG 制御ゲート電極
DC、SC プラグ
DR ドレイン領域
F1~F4、FD0~FD4 フィン
MC1~MC16 メモリセル
MG メモリゲート電極
SB 半導体基板
SR ソース領域
Claims (7)
- 半導体基板と、
前記半導体基板の一部分であって、前記半導体基板の上面から突出し、前記半導体基板の前記上面に沿う第1方向に延在する複数の第1突出部と、
前記複数の第1突出部のそれぞれの上面上および側面上に第1絶縁膜を介して形成され、前記第1方向に交差する第2方向に延在する第1ゲート電極と、
前記複数の第1突出部のそれぞれの前記上面上および前記側面上に電荷蓄積部である第2絶縁膜を介して形成され、前記第1ゲート電極の一方の側面に絶縁膜を介して隣接し、前記第2方向に延在する第2ゲート電極と、
平面視において、前記第1ゲート電極と隣り合うように、前記複数の第1突出部のそれぞれの内部に形成された第1半導体領域と、
平面視において、前記第2ゲート電極と隣り合うように、前記複数の第1突出部のそれぞれの内部に形成された第2半導体領域と、
前記複数の第1突出部上に形成され、前記第2方向に並ぶ複数の第1プラグと、
前記複数の第1突出部上に形成され、前記第2方向に並ぶ複数の第2プラグと、
を有し、
前記第1ゲート電極、前記第2ゲート電極、前記第1半導体領域および前記第2半導体領域は、不揮発性記憶素子を構成し、
前記第2方向に並ぶ複数の前記第1プラグのうち、N番目の前記第1プラグは、前記第2方向における2N-1番目および2N番目の前記第1突出部のそれぞれの内部に形成された前記第1半導体領域に電気的に接続され、
前記第2方向に並ぶ複数の前記第2プラグのうち、N番目の前記第2プラグは、前記第2方向における2N番目および2N+1番目の前記第1突出部のそれぞれの内部に形成された前記第2半導体領域に電気的に接続されている、半導体装置。 - 請求項1記載の半導体装置において、
前記第2方向に並んで形成された複数の第1半導体層と、
前記第2方向に並んで形成された複数の第2半導体層と、
を有し、
前記第2方向に並ぶ複数の前記第1半導体層のうち、N番目の前記第1半導体層は、前記第2方向における2N-1番目および2N番目の前記第1突出部のそれぞれの内部に形成された前記第1半導体領域の上面および側面に接し、
前記第2方向に並ぶ複数の前記第2半導体層のうち、N番目の前記第2半導体層は、前記第2方向における2N番目および2N+1番目の前記第1突出部のそれぞれの内部に形成された前記第2半導体領域の上面および側面に接し、
前記第1プラグは、前記第1半導体層を介して前記第1半導体領域に電気的に接続され、前記第2プラグは、前記第2半導体層を介して前記第2半導体領域に電気的に接続されている、半導体装置。 - 請求項1記載の半導体装置において、
前記第2方向に並ぶ複数の前記第1突出部同士の間に形成され、前記半導体基板の一部分であって、前記半導体基板の上面から突出し、前記第1方向に延在する複数の第2突出部をさらに有し、
前記第2方向に並ぶ複数の前記第1プラグのうち、N番目の前記第1プラグは、前記第2方向における2N-1番目の前記第1突出部と2N番目の前記第1突出部との相互間に位置する前記第2突出部に電気的に接続され、
前記第2方向に並ぶ複数の前記第2プラグのうち、N番目の前記第2プラグは、前記第2方向における2N番目の前記第1突出部および2N+1番目の前記第1突出部との相互間に位置する前記第2突出部に電気的に接続されている、半導体装置。 - 請求項3記載の半導体装置において、
複数の前記第2突出部のうち、前記第1プラグに電気的に接続された前記第2突出部は、平面視で前記第2プラグと離間しており、
前記第2プラグに電気的に接続された前記第2突出部は、平面視で前記第1プラグと離間している、半導体装置。 - 請求項1記載の半導体装置において、
前記第2方向に並ぶ複数の前記第1プラグ同士は、互いに離間しており、
前記第2方向に隣り合う前記第2プラグ同士は、互いに離間している、半導体装置。 - 請求項5記載の半導体装置において、
前記第2方向に並ぶ複数の前記第2プラグのうち、2N-1番目の前記第2プラグと、2N番目の前記第2プラグとのそれぞれの電位は、別々に制御される、半導体装置。 - 請求項1記載の半導体装置において、
前記第2方向に並ぶ前記複数の第1突出部のうち、N番目の前記第1突出部内に形成された一対の前記第2半導体領域および前記第1半導体領域を含む第1不揮発性記憶素子と、
前記第2方向に並ぶ前記複数の第1突出部のうち、N+1番目の前記第1突出部内に形成された一対の前記第2半導体領域および前記第1半導体領域を含む第2不揮発性記憶素子とは、互いに別々に動作が制御される、半導体装置。
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JP2004095048A (ja) | 2002-08-30 | 2004-03-25 | Toshiba Corp | 不揮発性半導体メモリ |
JP2009130210A (ja) | 2007-11-26 | 2009-06-11 | Toshiba Corp | 半導体装置 |
JP2019050314A (ja) | 2017-09-11 | 2019-03-28 | ルネサスエレクトロニクス株式会社 | 半導体装置およびその製造方法 |
JP2019050255A (ja) | 2017-09-08 | 2019-03-28 | ルネサスエレクトロニクス株式会社 | 半導体装置およびその製造方法 |
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JP2004095048A (ja) | 2002-08-30 | 2004-03-25 | Toshiba Corp | 不揮発性半導体メモリ |
JP2009130210A (ja) | 2007-11-26 | 2009-06-11 | Toshiba Corp | 半導体装置 |
JP2019050255A (ja) | 2017-09-08 | 2019-03-28 | ルネサスエレクトロニクス株式会社 | 半導体装置およびその製造方法 |
JP2019050314A (ja) | 2017-09-11 | 2019-03-28 | ルネサスエレクトロニクス株式会社 | 半導体装置およびその製造方法 |
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