JP7240921B2 - Display device - Google Patents

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Publication number
JP7240921B2
JP7240921B2 JP2019059314A JP2019059314A JP7240921B2 JP 7240921 B2 JP7240921 B2 JP 7240921B2 JP 2019059314 A JP2019059314 A JP 2019059314A JP 2019059314 A JP2019059314 A JP 2019059314A JP 7240921 B2 JP7240921 B2 JP 7240921B2
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Prior art keywords
light
insulating layer
display device
switching element
array substrate
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JP2019059314A
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Japanese (ja)
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JP2020160253A (en
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善英 大植
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Japan Display Inc
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Japan Display Inc
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Priority to JP2019059314A priority Critical patent/JP7240921B2/en
Priority to PCT/JP2020/010109 priority patent/WO2020195757A1/en
Publication of JP2020160253A publication Critical patent/JP2020160253A/en
Priority to US17/484,606 priority patent/US11402713B2/en
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Publication of JP7240921B2 publication Critical patent/JP7240921B2/en
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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/133345—Insulating layers
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1334—Constructional arrangements; Manufacturing methods based on polymer dispersed liquid crystals, e.g. microencapsulated liquid crystals
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
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    • G02F1/1335—Structural association of cells with optical devices, e.g. polarisers or reflectors
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    • G02F1/133615—Edge-illuminating devices, i.e. illuminating from the side
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    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/13439—Electrodes characterised by their electrical, optical, physical properties; materials therefor; method of making
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136209—Light shielding layers, e.g. black matrix, incorporated in the active matrix substrate, e.g. structurally associated with the switching element
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/3406—Control of illumination source
    • G09G3/342—Control of illumination source using several illumination sources separately controlled corresponding to different display panel areas, e.g. along one dimension such as lines
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1335—Structural association of cells with optical devices, e.g. polarisers or reflectors
    • G02F1/1336—Illuminating devices
    • G02F1/133616—Front illuminating devices
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • G02F1/13685—Top gates
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2203/00—Function characteristic
    • G02F2203/03—Function characteristic scattering
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/06—Adjustment of display parameters
    • G09G2320/0626—Adjustment of display parameters for control of overall brightness
    • G09G2320/0646—Modulation of illumination source brightness and image signal correlated to each other
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2360/00—Aspects of the architecture of display systems
    • G09G2360/16—Calculation or use of calculated indices related to luminance levels in display data
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement

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  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • General Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • Optics & Photonics (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Mathematical Physics (AREA)
  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
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  • Dispersion Chemistry (AREA)
  • Liquid Crystal (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Computer Hardware Design (AREA)

Description

本開示は、表示装置に関する。 The present disclosure relates to display devices.

特許文献１には、第１透光性基板と、第１透光性基板と対向して配置される第２透光性基板と、第１透光性基板と第２透光性基板との間に封入される高分子分散型液晶を有する液晶層と、第１透光性基板及び第２透光性基板の少なくとも１つの側面に対向して配置される少なくとも１つの発光部とを備える表示装置が記載されている。 In Patent Document 1, a first light-transmitting substrate, a second light-transmitting substrate arranged to face the first light-transmitting substrate, and a combination of the first light-transmitting substrate and the second light-transmitting substrate A display comprising a liquid crystal layer having a polymer-dispersed liquid crystal enclosed therebetween, and at least one light-emitting portion arranged to face at least one side surface of a first light-transmitting substrate and a second light-transmitting substrate. A device is described.

特開２０１８－０２１９７４号公報JP 2018-021974 A

特許文献１に記載されている表示装置では、表示パネルの一方の面から、反対側の他方の面側の背景を視認可能である。光源が第１透光性基板及び第２透光性基板の少なくとも１つの側面に対向して配置されるため、光源によるスイッチング素子の光リークを低減する必要がある。 In the display device described in Patent Literature 1, the background on the opposite side of the display panel can be viewed from one side of the display panel. Since the light source is arranged to face at least one side surface of the first translucent substrate and the second translucent substrate, it is necessary to reduce light leakage of the switching element due to the light source.

本発明の目的は、光源を用いて表示した画像が表示パネルの一方の面から、反対側の他方の面側の背景とともに視認可能であり、スイッチング素子の光リークを低減できる、表示装置を提供することにある。 An object of the present invention is to provide a display device in which an image displayed using a light source can be viewed from one side of a display panel together with a background on the other side of the opposite side, and light leakage from switching elements can be reduced. to do.

一態様に係る表示装置は、アレイ基板と、対向基板と、前記アレイ基板と前記対向基板との間の液晶層と、前記アレイ基板の側面又は前記対向基板の側面に光が入るように配置される光源と、を備え、前記アレイ基板は、第１方向に間隔をおいて並ぶ複数の信号線と、第２方向に間隔をおいて並ぶ複数の走査線と、前記走査線と前記信号線とに接続されたスイッチング素子と、少なくとも前記スイッチング素子を覆う有機絶縁層と、前記有機絶縁層の上方に重畳して設けられた金属層と、を有し、前記走査線と前記信号線とに囲まれた領域には、平面視で前記走査線及び前記信号線に重なる前記有機絶縁層の厚さよりも前記有機絶縁層の厚さが小さい領域があり、前記スイッチング素子よりも前記光源に近い側にある前記有機絶縁層の第１斜面が前記金属層で覆われ、前記スイッチング素子よりも前記光源から遠い側にある前記有機絶縁層の第２斜面が前記金属層で覆われている。 A display device according to one aspect is arranged such that light enters an array substrate, a counter substrate, a liquid crystal layer between the array substrate and the counter substrate, and a side surface of the array substrate or a side surface of the counter substrate. the array substrate includes a plurality of signal lines spaced apart in a first direction; a plurality of scanning lines spaced apart in a second direction; and the scanning lines and the signal lines. an organic insulating layer covering at least the switching element; and a metal layer provided over the organic insulating layer, surrounded by the scanning line and the signal line. In the area where the organic insulating layer overlaps with the scanning line and the signal line, there is an area in which the thickness of the organic insulating layer is smaller than the thickness of the organic insulating layer overlapping the scanning line and the signal line in a plan view, and the area is closer to the light source than the switching element. A first slope of one of the organic insulating layers is covered with the metal layer, and a second slope of the organic insulating layer farther from the light source than the switching element is covered with the metal layer.

図１は、本実施形態に係る表示装置の一例を表す斜視図である。FIG. 1 is a perspective view showing an example of a display device according to this embodiment. 図２は、実施形態１の表示装置を表すブロック図である。FIG. 2 is a block diagram showing the display device of Embodiment 1. FIG. 図３は、実施形態１のフィールドシーケンシャル方式において、光源が発光するタイミングを説明するタイミングチャートである。FIG. 3 is a timing chart for explaining the timing at which the light source emits light in the field sequential method of the first embodiment. 図４は、画素電極への印加電圧と画素の散乱状態との関係を示す説明図である。FIG. 4 is an explanatory diagram showing the relationship between the voltage applied to the pixel electrode and the scattering state of the pixel. 図５は、図１の表示装置の断面の一例を示す断面図である。5 is a cross-sectional view showing an example of a cross section of the display device of FIG. 1. FIG. 図６は、図１の表示装置の平面を示す平面図である。6 is a plan view showing a plane of the display device of FIG. 1. FIG. 図７は、図５の液晶層部分を拡大した拡大断面図である。FIG. 7 is an enlarged cross-sectional view of the liquid crystal layer portion of FIG. 図８は、液晶層において非散乱状態を説明するための断面図である。FIG. 8 is a cross-sectional view for explaining the non-scattering state in the liquid crystal layer. 図９は、液晶層において散乱状態を説明するための断面図である。FIG. 9 is a cross-sectional view for explaining the scattering state in the liquid crystal layer. 図１０は、画素において、走査線、信号線及びスイッチング素子を示す平面図である。FIG. 10 is a plan view showing scanning lines, signal lines and switching elements in a pixel. 図１１は、画素において、保持容量層を示す平面図である。FIG. 11 is a plan view showing a storage capacitor layer in a pixel. 図１２は、画素において、補助金属層及び開口領域を示す平面図である。FIG. 12 is a plan view showing auxiliary metal layers and opening regions in a pixel. 図１３は、画素において、画素電極を示す平面図である。FIG. 13 is a plan view showing a pixel electrode in a pixel. 図１４は、画素において、遮光層を示す平面図である。FIG. 14 is a plan view showing a light shielding layer in a pixel. 図１５は、図１４のＸＶ－ＸＶ’の断面図である。15 is a cross-sectional view taken along line XV-XV' of FIG. 14. FIG. 図１６は、図１４のＸＶＩ－ＸＶＩ’の断面図である。16 is a cross-sectional view taken along line XVI-XVI' of FIG. 14. FIG. 図１７は、図１４のＸＶＩＩ－ＸＶＩＩ’の断面図である。17 is a cross-sectional view taken along line XVII-XVII' of FIG. 14. FIG. 図１８は、周辺領域の断面図である。FIG. 18 is a cross-sectional view of the peripheral area. 図１９は、実施形態２の画素を示す平面図である。FIG. 19 is a plan view showing a pixel of Embodiment 2. FIG. 図２０は、実施形態３の表示装置の平面を示す平面図である。20 is a plan view showing the plane of the display device of Embodiment 3. FIG. 図２１は、実施形態３の画素において、走査線、信号線及びスイッチング素子を示す平面図である。21 is a plan view showing scanning lines, signal lines, and switching elements in the pixel of Embodiment 3. FIG. 図２２は、図２１のＸＸＩＩ－ＸＸＩＩ’の断面図である。22 is a cross-sectional view taken along line XXII-XXII' of FIG. 21. FIG.

本開示を実施するための形態（実施形態）につき、図面を参照しつつ詳細に説明する。以下の実施形態に記載した内容により本開示が限定されるものではない。また、以下に記載した構成要素には、当業者が容易に想定できるもの、実質的に同一のものが含まれる。さらに、以下に記載した構成要素は適宜組み合わせることが可能である。なお、開示はあくまで一例にすぎず、当業者において、開示の主旨を保っての適宜変更について容易に想到し得るものについては、当然に本開示の範囲に含有されるものである。また、図面は説明をより明確にするため、実際の態様に比べ、各部の幅、厚さ、形状等について模式的に表される場合があるが、あくまで一例であって、本開示の解釈を限定するものではない。また、本明細書と各図において、既出の図に関して前述したものと同様の要素には、同一の符号を付して、詳細な説明を適宜省略することがある。 A form (embodiment) for carrying out the present disclosure will be described in detail with reference to the drawings. The present disclosure is not limited by the contents described in the following embodiments. In addition, the components described below include those that can be easily assumed by those skilled in the art and those that are substantially the same. Furthermore, the components described below can be combined as appropriate. It should be noted that the disclosure is merely an example, and those that a person skilled in the art can easily conceive of appropriate modifications while maintaining the gist of the disclosure are naturally included in the scope of the present disclosure. In addition, in order to make the description clearer, the drawings may schematically show the width, thickness, shape, etc. of each part compared to the actual embodiment, but this is only an example, and the interpretation of the present disclosure is not intended. It is not limited. In addition, in this specification and each figure, the same reference numerals may be given to the same elements as those described above with respect to the existing figures, and detailed description thereof may be omitted as appropriate.

（実施形態１）
図１は、本実施形態に係る表示装置の一例を表す斜視図である。図２は、図１の表示装置を表すブロック図である。図３は、フィールドシーケンシャル方式において、光源が発光するタイミングを説明するタイミングチャートである。 (Embodiment 1)
FIG. 1 is a perspective view showing an example of a display device according to this embodiment. FIG. 2 is a block diagram representing the display device of FIG. FIG. 3 is a timing chart for explaining the timing at which the light source emits light in the field sequential method.

図１に示すように、表示装置１は、表示パネル２と、光源３と、駆動回路４とを有する。ここで、表示パネル２の平面の一方向がＰＸ方向とされ、ＰＸ方向と直交する方向が第２方向ＰＹとされ、ＰＸ－ＰＹ平面に直交する方向が第３方向ＰＺとされている。 As shown in FIG. 1 , the display device 1 has a display panel 2 , a light source 3 and a drive circuit 4 . Here, one direction of the plane of the display panel 2 is the PX direction, a direction orthogonal to the PX direction is the second direction PY, and a direction orthogonal to the PX-PY plane is the third direction PZ.

表示パネル２は、アレイ基板１０と、対向基板２０と、液晶層５０（図５参照）とを備えている。対向基板２０は、アレイ基板１０の表面に垂直な方向（図１に示すＰＺ方向）に対向する。液晶層５０（図５参照）は、アレイ基板１０と、対向基板２０と、封止部１８とで、後述する高分子分散型液晶ＬＣが封止されている。 The display panel 2 includes an array substrate 10, a counter substrate 20, and a liquid crystal layer 50 (see FIG. 5). The counter substrate 20 faces the surface of the array substrate 10 in a direction perpendicular to it (the PZ direction shown in FIG. 1). In the liquid crystal layer 50 (see FIG. 5), the array substrate 10, the opposing substrate 20, and the sealing portion 18 are sealed with polymer-dispersed liquid crystal LC, which will be described later.

図１に示すように、表示パネル２において、画像を表示可能な表示領域ＡＡと、表示領域ＡＡの外側の周辺領域ＦＲと、がある。表示領域ＡＡには、複数の画素Ｐｉｘがマトリクス状に配置されている。なお、本開示において、行とは、一方向に配列されるｍ個の画素Ｐｉｘを有する画素行をいう。また、列とは、行が配列される方向と直交する方向に配列されるｎ個の画素Ｐｉｘを有する画素列をいう。そして、ｍとｎとの値は、垂直方向の表示解像度と水平方向の表示解像度に応じて定まる。また、複数の走査線ＧＬが行毎に配線され、複数の信号線ＳＬが列毎に配線されている。 As shown in FIG. 1, the display panel 2 has a display area AA capable of displaying an image and a peripheral area FR outside the display area AA. A plurality of pixels Pix are arranged in a matrix in the display area AA. In the present disclosure, a row refers to a pixel row having m pixels Pix arranged in one direction. A column refers to a pixel column having n pixels Pix arranged in a direction orthogonal to the direction in which rows are arranged. The values of m and n are determined according to the vertical display resolution and the horizontal display resolution. Also, a plurality of scanning lines GL are wired for each row, and a plurality of signal lines SL are wired for each column.

光源３は、複数の発光部３１を備えている。図２に示すように、光源制御部３２は、駆動回路４に含まれる。なお、光源制御部３２は、駆動回路４の回路とは別の回路にしてもよい。発光部３１と、光源制御部３２とは、アレイ基板１０内の配線で電気的に接続されている。 The light source 3 has a plurality of light-emitting portions 31 . As shown in FIG. 2, the light source control section 32 is included in the drive circuit 4 . Note that the light source control unit 32 may be a circuit different from the circuit of the drive circuit 4 . The light emitting section 31 and the light source control section 32 are electrically connected by wiring in the array substrate 10 .

図１に示すように、駆動回路４は、アレイ基板１０の表面に固定されている。図２に示すように、駆動回路４は、信号処理回路４１、画素制御回路４２、ゲート駆動回路４３、ソース駆動回路４４及び共通電位駆動回路４５を備えている。アレイ基板１０は、対向基板２０よりもＸＹ平面の面積が大きく、対向基板２０から露出したアレイ基板１０の張り出し部分に、駆動回路４が設けられる。 As shown in FIG. 1, the drive circuit 4 is fixed on the surface of the array substrate 10. As shown in FIG. As shown in FIG. 2, the drive circuit 4 includes a signal processing circuit 41, a pixel control circuit 42, a gate drive circuit 43, a source drive circuit 44 and a common potential drive circuit 45. The array substrate 10 has a larger area in the XY plane than the opposing substrate 20 , and the drive circuit 4 is provided on the projecting portion of the array substrate 10 exposed from the opposing substrate 20 .

信号処理回路４１には、外部の上位制御部９の画像出力部９１から、フレキシブル基板９２を介して、入力信号（ＲＧＢ信号など）ＶＳが入力される。 An input signal (such as an RGB signal) VS is input to the signal processing circuit 41 from the image output unit 91 of the external upper control unit 9 via the flexible substrate 92 .

信号処理回路４１は、入力信号解析部４１１と、記憶部４１２と、信号調整部４１３とを備える。入力信号解析部４１１は、外部から入力された第１入力信号ＶＳに基づいて第２入力信号ＶＣＳを生成する。 The signal processing circuit 41 includes an input signal analysis section 411 , a storage section 412 and a signal adjustment section 413 . The input signal analysis unit 411 generates a second input signal VCS based on the first input signal VS input from the outside.

第２入力信号ＶＣＳは、第１入力信号ＶＳに基づいて、表示パネル２の各画素Ｐｉｘにどのような階調値を与えるかを定める信号である。言い換えると、第２入力信号ＶＣＳは、各画素Ｐｉｘの階調値に関する階調情報を含む信号である。 The second input signal VCS is a signal that determines what gradation value to give to each pixel Pix of the display panel 2 based on the first input signal VS. In other words, the second input signal VCS is a signal containing gradation information regarding the gradation value of each pixel Pix.

信号調整部４１３は、第２入力信号ＶＣＳから第３入力信号ＶＣＳＡを生成する。信号調整部４１３は、第３入力信号ＶＣＳＡを画素制御回路４２へ送出し、光源制御信号ＬＣＳＡを光源制御部３２へ送出する。光源制御信号ＬＣＳＡは、例えば、画素Ｐｉｘへの入力階調値に応じて設定される発光部３１の光量の情報を含む信号である。例えば、暗い画像が表示される場合、発光部３１の光量は小さく設定される。明るい画像が表示される場合、発光部３１の光量は大きく設定される。 The signal adjuster 413 generates a third input signal VCSA from the second input signal VCS. The signal adjustment unit 413 sends the third input signal VCSA to the pixel control circuit 42 and sends the light source control signal LCSA to the light source control unit 32 . The light source control signal LCSA is, for example, a signal containing information on the light amount of the light emitting unit 31 that is set according to the input gradation value to the pixel Pix. For example, when a dark image is displayed, the light intensity of the light emitting unit 31 is set small. When a bright image is displayed, the light intensity of the light emitting unit 31 is set large.

そして、画素制御回路４２は、第３入力信号ＶＣＳＡに基づいて水平駆動信号ＨＤＳと垂直駆動信号ＶＤＳとを生成する。本実施形態では、フィールドシーケンシャル方式で駆動されるので、水平駆動信号ＨＤＳと垂直駆動信号ＶＤＳとが発光部３１が発光可能な色毎に生成される。 Then, the pixel control circuit 42 generates the horizontal drive signal HDS and the vertical drive signal VDS based on the third input signal VCSA. In the present embodiment, since driving is performed by the field sequential method, the horizontal drive signal HDS and the vertical drive signal VDS are generated for each color that the light emitting section 31 can emit light.

ゲート駆動回路４３は水平駆動信号ＨＤＳに基づいて１垂直走査期間内に表示パネル２の走査線ＧＬを順次選択する。走査線ＧＬの選択の順番は任意である。 The gate drive circuit 43 sequentially selects the scanning lines GL of the display panel 2 within one vertical scanning period based on the horizontal drive signal HDS. The order of selection of the scanning lines GL is arbitrary.

ソース駆動回路４４は垂直駆動信号ＶＤＳに基づいて１水平走査期間内に表示パネル２の各信号線ＳＬに各画素Ｐｉｘの出力階調値に応じた階調信号を供給する。 The source drive circuit 44 supplies a gradation signal corresponding to the output gradation value of each pixel Pix to each signal line SL of the display panel 2 within one horizontal scanning period based on the vertical drive signal VDS.

本実施形態において、表示パネル２はアクティブマトリクス型パネルである。このため、平面視で第２方向ＰＹに延在する信号（ソース）線ＳＬ及び第１方向ＰＸに延在する走査（ゲート）線ＧＬを有し、信号線ＳＬと走査線ＧＬとの交差部にスイッチング素子Ｔｒを有する。 In this embodiment, the display panel 2 is an active matrix panel. Therefore, in plan view, signal (source) lines SL extending in the second direction PY and scanning (gate) lines GL extending in the first direction PX are provided, and intersections of the signal lines SL and the scanning lines GL has a switching element Tr.

スイッチング素子Ｔｒとして薄膜トランジスタが用いられる。薄膜トランジスタの例としては、ボトムゲート型トランジスタ又はトップゲート型トランジスタを用いてもよい。スイッチング素子Ｔｒとして、シングルゲート薄膜トランジスタを例示するが、ダブルゲートトランジスタでもよい。スイッチング素子Ｔｒのソース電極及びドレイン電極のうち一方は信号線ＳＬに接続され、ゲート電極は走査線ＧＬに接続され、ソース電極及びドレイン電極のうち他方は、後述する高分子分散型液晶ＬＣの容量の一端に接続されている。高分子分散型液晶ＬＣの容量は、一端がスイッチング素子Ｔｒに画素電極ＰＥを介して接続され、他端が共通電極ＣＥを介してコモン電位配線ＣＯＭＬに接続されている。また、画素電極ＰＥと、コモン電位配線ＣＯＭＬに電気的に接続されている保持容量電極ＩＯとの間には、保持容量ＨＣが生じる。なお、コモン電位配線ＣＯＭＬは、共通電位駆動回路４５より供給される。 A thin film transistor is used as the switching element Tr. A bottom-gate transistor or a top-gate transistor may be used as an example of a thin film transistor. A single-gate thin film transistor is exemplified as the switching element Tr, but a double-gate transistor may be used. One of the source electrode and the drain electrode of the switching element Tr is connected to the signal line SL, the gate electrode is connected to the scanning line GL, and the other of the source electrode and the drain electrode is connected to the capacitor of polymer dispersed liquid crystal LC described later. connected to one end of the One end of the capacitance of the polymer-dispersed liquid crystal LC is connected to the switching element Tr via the pixel electrode PE, and the other end is connected to the common potential line COML via the common electrode CE. A storage capacitor HC is generated between the pixel electrode PE and the storage capacitor electrode IO electrically connected to the common potential line COML. Note that the common potential wiring COML is supplied from the common potential driving circuit 45 .

発光部３１は、第１色（例えば、赤色）の発光体３３Ｒと、第２色（例えば、緑色）の発光体３３Ｇと、第３色（例えば、青色）の発光体３３Ｂを備えている。光源制御部３２は、光源制御信号ＬＣＳＡに基づいて、第１色の発光体３３Ｒ、第２色の発光体３３Ｇ及び第３色の発光体３３Ｂのそれぞれを時分割で発光するように制御する。このように、第１色の発光体３３Ｒ、第２色の発光体３３Ｇ及び第３色の発光体３３Ｂは、フィールドシーケンシャル方式で駆動される。 The light emitting unit 31 includes a first color (eg, red) light emitter 33R, a second color (eg, green) light emitter 33G, and a third color (eg, blue) light emitter 33B. Based on the light source control signal LCSA, the light source control unit 32 controls the light emitters 33R of the first color, the light emitters 33G of the second color, and the light emitters 33B of the third color to emit light in a time division manner. Thus, the first color emitter 33R, the second color emitter 33G, and the third color emitter 33B are driven in a field sequential manner.

図３に示すように、第１サブフレーム（第１所定時間）ＲＦにおいて、第１色の発光期間ＲＯＮで第１色の発光体３３Ｒが発光するとともに、１垂直走査期間ＧａｔｅＳｃａｎ内に選択された画素Ｐｉｘが光を散乱させて表示する。表示パネル２全体では、１垂直走査期間ＧａｔｅＳｃａｎ内に選択された画素Ｐｉｘに、上述した各信号線ＳＬに各画素Ｐｉｘの出力階調値に応じた階調信号が供給されていれば、第１色の発光期間ＲＯＮにおいて第１色のみ点灯している。 As shown in FIG. 3, in the first subframe (first predetermined time) RF, the light emitter 33R of the first color emits light during the light emission period RON of the first color, and the light emitter 33R is selected within one vertical scanning period GateScan. Pixel Pix scatters light for display. In the display panel 2 as a whole, if a grayscale signal corresponding to the output grayscale value of each pixel Pix is supplied to each signal line SL to the pixel Pix selected within one vertical scanning period GateScan, the first Only the first color is lit during the color emission period RON.

次に、第２サブフレーム（第２所定時間）ＧＦにおいて、第２色の発光期間ＧＯＮで第２色の発光体３３Ｇが発光するとともに、１垂直走査期間ＧａｔｅＳｃａｎ内に選択された画素Ｐｉｘが光を散乱させて表示する。表示パネル２全体では、１垂直走査期間ＧａｔｅＳｃａｎ内に選択された画素Ｐｉｘに、上述した各信号線ＳＬに各画素Ｐｉｘの出力階調値に応じた階調信号が供給されていれば、第２色の発光期間ＧＯＮにおいて第２色のみ点灯している。 Next, in the second subframe (second predetermined time) GF, the second color light emitter 33G emits light during the second color light emission period GON, and the pixel Pix selected within one vertical scanning period GateScan emits light. are scattered and displayed. In the display panel 2 as a whole, if a grayscale signal corresponding to the output grayscale value of each pixel Pix is supplied to each signal line SL to the pixel Pix selected within one vertical scanning period GateScan, the second Only the second color is lit during the color emission period GON.

さらに、第３サブフレーム（第３所定時間）ＢＦにおいて、第３色の発光期間ＢＯＮで第３色の発光体３３Ｂが発光するとともに、１垂直走査期間ＧａｔｅＳｃａｎ内に選択された画素Ｐｉｘが光を散乱させて表示する。表示パネル２全体では、１垂直走査期間ＧａｔｅＳｃａｎ内に選択された画素Ｐｉｘに、上述した各信号線ＳＬに各画素Ｐｉｘの出力階調値に応じた階調信号が供給されていれば、第３色の発光期間ＢＯＮにおいて第３色のみ点灯している。 Further, in the third sub-frame (third predetermined time) BF, the light emitter 33B of the third color emits light during the light emission period BON of the third color, and the pixel Pix selected within one vertical scanning period GateScan emits light. Display scattered. In the display panel 2 as a whole, if a grayscale signal corresponding to the output grayscale value of each pixel Pix is supplied to each signal line SL to the pixel Pix selected within one vertical scanning period GateScan, the third Only the third color is lit during the color emission period BON.

人間の眼には、時間的な分解能の制限があり、残像が発生するので、１フレーム（１Ｆ）の期間に３色の合成された画像が認識される。フィールドシーケンシャル方式では、カラーフィルタを不要とすることができ、カラーフィルタでの吸収ロスが低減するので、高い透過率が実現できる。カラーフィルタ方式では、第１色、第２色、第３色毎に画素Ｐｉｘを分割したサブピクセルで一画素を作るのに対し、フィールドシーケンシャル方式では、このようなサブピクセル分割をしなくてもよい。なお、第４サブフレームをさらに有し、第１色、第２色及び第３色とは異なる第４色を発光するようにしてもよい。 Since the human eye has a limited temporal resolution and an afterimage occurs, an image composed of three colors is recognized in one frame (1F) period. The field sequential method can eliminate the need for color filters and reduce the absorption loss in the color filters, thereby achieving high transmittance. In the color filter method, one pixel is made up of sub-pixels obtained by dividing the pixel Pix for each of the first, second, and third colors. good. It should be noted that a fourth sub-frame may be further provided to emit light in a fourth color different from the first, second and third colors.

図４は、画素電極への印加電圧と画素の散乱状態との関係を示す説明図である。図５は、図１の表示装置の断面の一例を示す断面図である。図６は、図１の表示装置の平面を示す平面図である。図５は、図６のＶ－Ｖ’断面である。図７は、図５の液晶層部分を拡大した拡大断面図である。図８は、液晶層において非散乱状態を説明するための断面図である。図９は、液晶層において散乱状態を説明するための断面図である。 FIG. 4 is an explanatory diagram showing the relationship between the voltage applied to the pixel electrode and the scattering state of the pixel. 5 is a cross-sectional view showing an example of a cross section of the display device of FIG. 1. FIG. 6 is a plan view showing a plane of the display device of FIG. 1. FIG. FIG. 5 is a cross section taken along line V-V' of FIG. FIG. 7 is an enlarged cross-sectional view of the liquid crystal layer portion of FIG. FIG. 8 is a cross-sectional view for explaining the non-scattering state in the liquid crystal layer. FIG. 9 is a cross-sectional view for explaining the scattering state in the liquid crystal layer.

１垂直走査期間ＧａｔｅＳｃａｎ内に選択された画素Ｐｉｘに、上述した各信号線ＳＬに各画素Ｐｉｘの出力階調値に応じた階調信号が供給されていれば、階調信号に応じて画素電極ＰＥへの印加電圧が変わる。画素電極ＰＥへの印加電圧が変わると、画素電極ＰＥと、共通電極ＣＥとの間の電圧が変化する。そして、図４に示すように、画素電極ＰＥへの印加電圧に応じて、画素Ｐｉｘ毎の液晶層５０の散乱状態が制御され、画素Ｐｉｘ内の散乱割合が変化する。 If a grayscale signal corresponding to the output grayscale value of each pixel Pix is supplied to each signal line SL to the pixel Pix selected within one vertical scanning period GateScan, the pixel electrode The applied voltage to PE changes. When the voltage applied to the pixel electrode PE changes, the voltage between the pixel electrode PE and common electrode CE changes. Then, as shown in FIG. 4, the scattering state of the liquid crystal layer 50 for each pixel Pix is controlled according to the voltage applied to the pixel electrode PE, and the scattering ratio within the pixel Pix changes.

図４に示すように、画素電極ＰＥへの印加電圧が飽和電圧Ｖｓａｔ以上となると、画素Ｐｉｘ内の散乱割合の変化が小さくなる。そこで、駆動回路４は、飽和電圧Ｖｓａｔよりも低い電圧範囲Ｖｄｒにおいて、垂直駆動信号ＶＤＳに応じた画素電極ＰＥへの印加電圧を変化させる。 As shown in FIG. 4, when the voltage applied to the pixel electrode PE becomes equal to or higher than the saturation voltage Vsat, the change in the scattering rate within the pixel Pix becomes small. Therefore, the drive circuit 4 changes the voltage applied to the pixel electrode PE according to the vertical drive signal VDS in the voltage range Vdr lower than the saturation voltage Vsat.

図５及び図６に示すように、アレイ基板１０は、第１主面１０Ａ、第２主面１０Ｂ、第１側面１０Ｃ、第２側面１０Ｄ、第３側面１０Ｅ及び第４側面１０Ｆを備える。第１主面１０Ａと第２主面１０Ｂとは、平行な平面である。また、第１側面１０Ｃと第２側面１０Ｄとは、平行な平面である。第３側面１０Ｅと第４側面１０Ｆとは、平行な平面である。 As shown in FIGS. 5 and 6, the array substrate 10 has a first main surface 10A, a second main surface 10B, a first side surface 10C, a second side surface 10D, a third side surface 10E and a fourth side surface 10F. The first main surface 10A and the second main surface 10B are parallel planes. Also, the first side surface 10C and the second side surface 10D are parallel planes. The third side surface 10E and the fourth side surface 10F are parallel planes.

図５及び図６に示すように、対向基板２０は、第１主面２０Ａ、第２主面２０Ｂ、第１側面２０Ｃ、第２側面２０Ｄ、第３側面２０Ｅ及び第４側面２０Ｆを備える。第１主面２０Ａと第２主面２０Ｂとは、平行な平面である。第１側面２０Ｃと第２側面２０Ｄとは、平行な平面である。第３側面２０Ｅと第４側面２０Ｆとは、平行な平面である。 As shown in FIGS. 5 and 6, the opposing substrate 20 has a first main surface 20A, a second main surface 20B, a first side surface 20C, a second side surface 20D, a third side surface 20E and a fourth side surface 20F. The first main surface 20A and the second main surface 20B are parallel planes. The first side surface 20C and the second side surface 20D are parallel planes. The third side surface 20E and the fourth side surface 20F are parallel planes.

図５及び図６に示すように、光源３は、対向基板２０の第２側面２０Ｄに対向する。光源３は、サイド光源と呼ばれることもある。図５に示すように、光源３は、対向基板２０の第２側面２０Ｄへ光源光Ｌを照射する。光源３と対向する対向基板２０の第２側面２０Ｄは、光入射面となる。 As shown in FIGS. 5 and 6, the light source 3 faces the second side surface 20D of the counter substrate 20. As shown in FIGS. The light source 3 is sometimes called a side light source. As shown in FIG. 5, the light source 3 irradiates the second side surface 20D of the counter substrate 20 with the light source light L. As shown in FIG. A second side surface 20D of the counter substrate 20 facing the light source 3 serves as a light incident surface.

図５に示すように、光源３から照射された光源光Ｌは、アレイ基板１０の第１主面１０Ａ及び対向基板２０の第１主面２０Ａで反射しながら、第２側面２０Ｄから遠ざかる方向（第２方向ＰＹ）に伝播する。アレイ基板１０の第１主面１０Ａ又は対向基板２０の第１主面２０Ａから外部へ光源光Ｌが向かうと、屈折率の大きな媒質から屈折率の小さな媒質へ進むことになるので、光源光Ｌがアレイ基板１０の第１主面１０Ａ又は対向基板２０の第１主面２０Ａへ入射する入射角が臨界角よりも大きければ、光源光Ｌがアレイ基板１０の第１主面１０Ａ又は対向基板２０の第１主面２０Ａで全反射する。 As shown in FIG. 5, the light source light L emitted from the light source 3 is reflected by the first main surface 10A of the array substrate 10 and the first main surface 20A of the counter substrate 20 in a direction away from the second side surface 20D ( propagate in the second direction PY). When the light source light L travels from the first main surface 10A of the array substrate 10 or the first main surface 20A of the counter substrate 20 to the outside, the light source light L travels from a medium with a large refractive index to a medium with a small refractive index. is incident on the first main surface 10A of the array substrate 10 or the first main surface 20A of the counter substrate 20 is larger than the critical angle, the light source light L is incident on the first main surface 10A of the array substrate 10 or the counter substrate 20 is totally reflected by the first main surface 20A of

図５に示すように、アレイ基板１０及び対向基板２０の内部を伝播した光源光Ｌは、散乱状態となっている液晶がある画素Ｐｉｘで散乱され、散乱光の入射角が臨界角よりも小さな角度となって、放射光６８、６８Ａがそれぞれ対向基板２０の第１主面２０Ａ、アレイ基板１０の第１主面１０Ａから外部に放射される。対向基板２０の第１主面２０Ａ、アレイ基板１０の第１主面１０Ａからそれぞれ外部に放射された放射光６８、６８Ａは、観察者に観察される。以下、図７から図９を用いて、散乱状態となっている高分子分散型液晶と、非散乱状態の高分子分散型液晶とについて説明する。 As shown in FIG. 5, the light source light L propagating inside the array substrate 10 and the counter substrate 20 is scattered by the pixel Pix where the liquid crystal is in the scattering state, and the incident angle of the scattered light is smaller than the critical angle. At an angle, emitted lights 68 and 68A are radiated to the outside from the first main surface 20A of the opposing substrate 20 and the first main surface 10A of the array substrate 10, respectively. Radiation lights 68 and 68A radiated to the outside from the first main surface 20A of the counter substrate 20 and the first main surface 10A of the array substrate 10, respectively, are observed by an observer. The polymer-dispersed liquid crystal in the scattering state and the polymer-dispersed liquid crystal in the non-scattering state will be described below with reference to FIGS. 7 to 9. FIG.

図７に示すように、アレイ基板１０には、第１配向膜ＡＬ１が設けられている。対向基板２０には、第２配向膜ＡＬ２が設けられている。第１配向膜ＡＬ１及び第２配向膜ＡＬ２は、例えば、垂直配向膜である。 As shown in FIG. 7, the array substrate 10 is provided with a first alignment film AL1. The opposing substrate 20 is provided with a second alignment film AL2. The first alignment film AL1 and the second alignment film AL2 are, for example, vertical alignment films.

液晶とモノマーを含む溶液がアレイ基板１０と対向基板２０との間に封入されている。次に、モノマー及び液晶を第１配向膜ＡＬ１及び第２配向膜ＡＬ２によって配向させた状態で、紫外線又は熱によってモノマーを重合させ、バルク５１を形成する。これにより、網目状に形成された高分子のネットワークの隙間に液晶が分散されたリバースモードの高分子分散型液晶ＬＣを有する液晶層５０が形成される。 A solution containing liquid crystal and monomer is sealed between the array substrate 10 and the counter substrate 20 . Next, while the monomers and the liquid crystal are oriented by the first alignment film AL1 and the second alignment film AL2, the monomers are polymerized by ultraviolet light or heat to form the bulk 51 . As a result, the liquid crystal layer 50 having the reverse mode polymer-dispersed liquid crystal LC in which the liquid crystal is dispersed in the gaps of the polymer network formed in a mesh shape is formed.

このように、高分子分散型液晶ＬＣは、高分子によって形成されたバルク５１と、バルク５１内に分散された複数の微粒子５２と、を有する。微粒子５２は、液晶によって形成されている。バルク５１及び微粒子５２は、それぞれ光学異方性を有している。 Thus, the polymer-dispersed liquid crystal LC has a bulk 51 made of polymer and a plurality of fine particles 52 dispersed within the bulk 51 . The fine particles 52 are made of liquid crystal. The bulk 51 and fine particles 52 each have optical anisotropy.

微粒子５２に含まれる液晶の配向は、画素電極ＰＥと共通電極ＣＥとの間の電圧差によって制御される。画素電極ＰＥへの印加電圧により、液晶の配向が変化する。液晶の配向が変化することにより、画素Ｐｉｘを通過する光の散乱の度合いが変化する。 The orientation of the liquid crystal contained in the fine particles 52 is controlled by the voltage difference between the pixel electrode PE and the common electrode CE. The orientation of the liquid crystal changes depending on the voltage applied to the pixel electrode PE. By changing the orientation of the liquid crystal, the degree of scattering of light passing through the pixel Pix changes.

例えば、図８に示すように、画素電極ＰＥと共通電極ＣＥとの間に電圧が印加されていない状態では、バルク５１の光軸Ａｘ１と微粒子５２の光軸Ａｘ２の向きは互いに等しい。微粒子５２の光軸Ａｘ２は、液晶層５０のＰＺ方向と平行である。バルク５１の光軸Ａｘ１は、電圧の有無に関わらず、液晶層５０のＰＺ方向と平行である。 For example, as shown in FIG. 8, when no voltage is applied between the pixel electrode PE and the common electrode CE, the directions of the optical axis Ax1 of the bulk 51 and the optical axis Ax2 of the fine particles 52 are the same. The optical axis Ax2 of the fine particles 52 is parallel to the PZ direction of the liquid crystal layer 50 . The optical axis Ax1 of the bulk 51 is parallel to the PZ direction of the liquid crystal layer 50 regardless of the presence or absence of voltage.

バルク５１と微粒子５２の常光屈折率は互いに等しい。画素電極ＰＥと共通電極ＣＥとの間に電圧が印加されていない状態では、あらゆる方向においてバルク５１と微粒子５２との間の屈折率差がゼロになる。液晶層５０は、光源光Ｌを散乱しない非散乱状態となる。光源光Ｌは、アレイ基板１０の第１主面１０Ａ及び対向基板２０の第１主面２０Ａで反射しながら、光源３（発光部３１）から遠ざかる方向に伝播する。液晶層５０が光源光Ｌを散乱しない非散乱状態であると、アレイ基板１０の第１主面１０Ａから対向基板２０の第１主面２０Ａ側の背景が視認され、対向基板２０の第１主面２０Ａからアレイ基板１０の第１主面１０Ａ側の背景が視認される。 The bulk 51 and fine particles 52 have the same ordinary refractive index. When no voltage is applied between the pixel electrode PE and the common electrode CE, the refractive index difference between the bulk 51 and the fine particles 52 is zero in all directions. The liquid crystal layer 50 becomes a non-scattering state in which the light source light L is not scattered. The light source light L propagates away from the light source 3 (light emitting section 31) while being reflected by the first main surface 10A of the array substrate 10 and the first main surface 20A of the counter substrate 20. FIG. When the liquid crystal layer 50 is in a non-scattering state in which the light source light L is not scattered, the background on the side of the first main surface 20A of the counter substrate 20 from the first main surface 10A of the array substrate 10 is visible. The background on the side of the first main surface 10A of the array substrate 10 is visible from the surface 20A.

図９に示すように、電圧が印加された画素電極ＰＥと共通電極ＣＥとの間では、微粒子５２の光軸Ａｘ２は、画素電極ＰＥと共通電極ＣＥとの間に発生する電界によって傾くことになる。バルク５１の光軸Ａｘ１は、電界によって変化しないため、バルク５１の光軸Ａｘ１と微粒子５２の光軸Ａｘ２の向きは互いに異なる。電圧が印加された画素電極ＰＥがある画素Ｐｉｘにおいて、光源光Ｌが散乱される。上述したように散乱された光源光Ｌの一部がアレイ基板１０の第１主面１０Ａ又は対向基板２０の第１主面２０Ａから外部に放射された光は、観察者に観察される。 As shown in FIG. 9, between the pixel electrode PE to which the voltage is applied and the common electrode CE, the optical axis Ax2 of the fine particle 52 is tilted by the electric field generated between the pixel electrode PE and the common electrode CE. Become. Since the optical axis Ax1 of the bulk 51 does not change due to the electric field, the directions of the optical axis Ax1 of the bulk 51 and the optical axis Ax2 of the fine particles 52 are different from each other. The light source light L is scattered in the pixel Pix having the pixel electrode PE to which the voltage is applied. A part of the scattered light source light L emitted as described above from the first main surface 10A of the array substrate 10 or the first main surface 20A of the counter substrate 20 is observed by an observer.

電圧が印加されていない画素電極ＰＥがある画素Ｐｉｘでは、アレイ基板１０の第１主面１０Ａから対向基板２０の第１主面２０Ａ側の背景が視認され、対向基板２０の第１主面２０Ａからアレイ基板１０の第１主面１０Ａ側の背景が視認される。そして、本実施形態の表示装置１は、画像出力部９１から第１入力信号ＶＳが入力されると、画像が表示される画素Ｐｉｘの画素電極ＰＥに電圧が印加され、第３入力信号ＶＣＳＡに基づく画像が背景とともに視認される。このように、高分子分散型液晶が散乱状態にあるとき、表示領域において画像が表示される。 In the pixel Pix having the pixel electrode PE to which no voltage is applied, the background on the side of the first main surface 20A of the counter substrate 20 from the first main surface 10A of the array substrate 10 is visually recognized. The background on the side of the first main surface 10A of the array substrate 10 is visible from the top. Then, in the display device 1 of the present embodiment, when the first input signal VS is input from the image output section 91, a voltage is applied to the pixel electrode PE of the pixel Pix where the image is displayed, and the third input signal VCSA is applied. The image based on is viewed with the background. Thus, when the polymer-dispersed liquid crystal is in the scattering state, an image is displayed in the display area.

電圧が印加された画素電極ＰＥがある画素Ｐｉｘにおいて光源光Ｌが散乱されて外部に放射された光によって表示された画像は、背景に重なり、表示されることになる。換言すると、本実施形態の表示装置１は、放射光６８又は放射光６８Ａと、背景との組み合わせにより、画像を背景に重ね合わせて表示する。 The light source light L is scattered in the pixel Pix where the pixel electrode PE to which the voltage is applied is scattered, and the image displayed by the light emitted to the outside overlaps the background and is displayed. In other words, the display device 1 of the present embodiment displays an image superimposed on the background by combining the emitted light 68 or the emitted light 68A with the background.

図３に示す１垂直走査期間ＧａｔｅＳｃａｎにおいて、書き込まれた各画素電極ＰＥ（図７参照）の電位が、各１垂直走査期間ＧａｔｅＳｃａｎの後にある第１色の発光期間ＲＯＮ、第２色の発光期間ＧＯＮ及び第３色の発光期間ＢＯＮの少なくとも１つに保持されている必要がある。書き込まれた各画素電極ＰＥ（図７参照）の電位が、各１垂直走査期間ＧａｔｅＳｃａｎの後にある第１色の発光期間ＲＯＮ、第２色の発光期間ＧＯＮ及び第３色の発光期間ＢＯＮの少なくとも１つで保持できないと、いわゆるフリッカーなどが生じやすい。言い換えると、走査線の選択時間である１垂直走査期間ＧａｔｅＳｃａｎを短くし、いわゆるフィールドシーケンシャル方式で駆動における視認性を高めるためには、第１色の発光期間ＲＯＮ、第２色の発光期間ＧＯＮ及び第３色の発光期間ＢＯＮのそれぞれで、書き込まれた各画素電極ＰＥ（図７参照）の電位を保持しやすくする要望がある。 In one vertical scanning period GateScan shown in FIG. 3, the written potential of each pixel electrode PE (see FIG. 7) is changed to the first color light emission period RON and the second color light emission period after each vertical scanning period GateScan. At least one of GON and the third color emission period BON must be held. The written potential of each pixel electrode PE (see FIG. 7) remains at least during the first color emission period RON, the second color emission period GON, and the third color emission period BON after each vertical scanning period GateScan. If it cannot be held by one, so-called flicker tends to occur. In other words, in order to shorten one vertical scanning period GateScan, which is the scanning line selection time, and to improve visibility in driving by a so-called field sequential method, the first color light emission period RON, the second color light emission period GON, and the There is a demand to make it easier to hold the written potential of each pixel electrode PE (see FIG. 7) in each of the light emission periods BON of the third color.

図１０は、画素において、走査線、信号線及びスイッチング素子を示す平面図である。図１１は、画素において、保持容量層を示す平面図である。図１２は、画素において、補助金属層及び開口領域を示す平面図である。図１３は、画素において、画素電極を示す平面図である。図１４は、画素において、遮光層を示す平面図である。図１５は、図１４のＸＶ－ＸＶ’の断面図である。図１６は、図１４のＸＶI－ＸＶI’の断面図である。図１７は、図１４のＸＶＩＩ－ＸＶＩＩ’の断面図である。図１８は、周辺領域の断面図である。図１、図２及び図１０に示すように、アレイ基板１０には、複数の信号線ＳＬと複数の走査線ＧＬとが平面視において格子状に設けられている。言い換えると、アレイ基板１０の一方の面には、第１方向ＰＸに間隔をおいて並ぶ複数の信号線と、第２方向ＰＹに間隔をおいて並ぶ複数の走査線と、を備える。 FIG. 10 is a plan view showing scanning lines, signal lines and switching elements in a pixel. FIG. 11 is a plan view showing a storage capacitor layer in a pixel. FIG. 12 is a plan view showing auxiliary metal layers and opening regions in a pixel. FIG. 13 is a plan view showing a pixel electrode in a pixel. FIG. 14 is a plan view showing a light shielding layer in a pixel. 15 is a cross-sectional view taken along line XV-XV' of FIG. 14. FIG. 16 is a cross-sectional view taken along line XVI-XVI' of FIG. 14. FIG. 17 is a cross-sectional view taken along line XVII-XVII' of FIG. 14. FIG. FIG. 18 is a cross-sectional view of the peripheral area. As shown in FIGS. 1, 2, and 10, the array substrate 10 is provided with a plurality of signal lines SL and a plurality of scanning lines GL in a grid pattern in plan view. In other words, one surface of the array substrate 10 is provided with a plurality of signal lines arranged at intervals in the first direction PX and a plurality of scanning lines arranged at intervals in the second direction PY.

図１０に示すように、隣り合う走査線ＧＬと隣り合う信号線ＳＬとで囲まれる領域が、画素Ｐｉｘである。画素Ｐｉｘには、画素電極ＰＥとスイッチング素子Ｔｒとが設けられている。本実施形態において、スイッチング素子Ｔｒは、ボトムゲート型の薄膜トランジスタである。スイッチング素子Ｔｒは、走査線ＧＬと電気的に接続されているゲート電極ＧＥと平面視において重畳する半導体層ＳＣを有する。 As shown in FIG. 10, a pixel Pix is an area surrounded by adjacent scanning lines GL and adjacent signal lines SL. A pixel electrode PE and a switching element Tr are provided in the pixel Pix. In this embodiment, the switching element Tr is a bottom gate type thin film transistor. The switching element Tr has a semiconductor layer SC that overlaps the gate electrode GE electrically connected to the scanning line GL in plan view.

図１０に示すように、走査線ＧＬは、モリブデン（Ｍｏ）、アルミニウム（Ａｌ）等の金属、これらの積層体又はこれらの合金の配線である。信号線ＳＬは、アルミニウム等の金属又は合金の配線である。 As shown in FIG. 10, the scanning lines GL are wirings of metals such as molybdenum (Mo) and aluminum (Al), laminates thereof, or alloys thereof. The signal line SL is a wiring made of a metal such as aluminum or an alloy.

図１０に示すように、半導体層ＳＣは、平面視において、ゲート電極ＧＥからはみ出さないように設けられている。これにより、ゲート電極ＧＥ側から半導体層ＳＣに向かう光源光Ｌが反射され、半導体層ＳＣに光リークが生じにくくなる。 As shown in FIG. 10, the semiconductor layer SC is provided so as not to protrude from the gate electrode GE in plan view. As a result, the light source light L directed toward the semiconductor layer SC from the gate electrode GE side is reflected, and light leakage is less likely to occur in the semiconductor layer SC.

図５及び図２０に示すように、光源３から照射された光源光Ｌは、第２方向ＰＹを入射方向として、入射してくる。光源光Ｌの入射方向が第２方向ＰＹである場合、半導体層ＳＣの第１方向の幅が、半導体層ＳＣの第２方向の幅よりも小さい。これにより、光源光Ｌの入射方向に交差する方向の幅が小さくなり、光リークの影響が低減する。 As shown in FIGS. 5 and 20, the light source light L emitted from the light source 3 is incident with the second direction PY as the incident direction. When the incident direction of the light source light L is the second direction PY, the width of the semiconductor layer SC in the first direction is smaller than the width of the semiconductor layer SC in the second direction. As a result, the width in the direction intersecting the incident direction of the light source light L is reduced, and the influence of light leakage is reduced.

図１０に示すように、ソース電極ＳＥは、信号線ＳＬと同じ２つの導電体が、信号線ＳＬと同層でかつ信号線と交差する方向に信号線ＳＬから伸びている。これにより、信号線ＳＬと電気的に接続するソース電極ＳＥは、平面視において、半導体層ＳＣの一端部と重畳している。 As shown in FIG. 10, in the source electrode SE, the same two conductors as the signal line SL extend from the signal line SL in the same layer as the signal line SL and in a direction intersecting the signal line. Thus, the source electrode SE electrically connected to the signal line SL overlaps with one end of the semiconductor layer SC in plan view.

図１０に示すように、平面視において、隣り合うソース電極ＳＥの導電体の間の位置には、ドレイン電極ＤＥが設けられている。ドレイン電極ＤＥは、平面視において、半導体層ＳＣと重畳している。ソース電極ＳＥ及びドレイン電極ＤＥと重畳しない部分は、スイッチング素子Ｔｒのチャネルとして機能する。図１３に示すように、ドレイン電極ＤＥと電気的に接続されるコンタクト電極ＤＥＡは、コンタクトホールＣＨで画素電極ＰＥと電気的に接続されている。 As shown in FIG. 10, the drain electrode DE is provided between the conductors of the adjacent source electrodes SE in plan view. The drain electrode DE overlaps the semiconductor layer SC in plan view. A portion not overlapping with the source electrode SE and the drain electrode DE functions as a channel of the switching element Tr. As shown in FIG. 13, the contact electrode DEA electrically connected to the drain electrode DE is electrically connected to the pixel electrode PE through the contact hole CH.

図１５に示すように、アレイ基板１０は、例えばガラスで形成された第１透光性基材１９を有している。第１透光性基材１９は、透光性を有していれば、ポリエチレンテレフタレートなどの樹脂でもよい。 As shown in FIG. 15, the array substrate 10 has a first translucent base material 19 made of glass, for example. The first translucent base material 19 may be a resin such as polyethylene terephthalate as long as it has translucency.

図１５に示すように、第１透光性基材１９上には、走査線ＧＬ（図１０参照）及びゲート電極ＧＥが設けられる。 As shown in FIG. 15, scanning lines GL (see FIG. 10) and gate electrodes GE are provided on the first translucent base material 19 .

図１５に示すように、また、走査線ＧＬ及びゲート電極ＧＥを覆って第１絶縁層１１が設けられている。第１絶縁層１１は、例えば、窒化シリコンなどの透明な無機絶縁材料によって形成されている。 As shown in FIG. 15, a first insulating layer 11 is also provided to cover the scanning lines GL and the gate electrodes GE. The first insulating layer 11 is made of, for example, a transparent inorganic insulating material such as silicon nitride.

第１絶縁層１１上には、半導体層ＳＣが積層されている。半導体層ＳＣは、例えば、アモルファスシリコンによって形成されているが、ポリシリコン又は酸化物半導体によって形成されていてもよい。同じ断面でみたときに、半導体層ＳＣの幅Ｌｓｃは、半導体層ＳＣに重畳するゲート電極ＧＥの幅Ｌｇｅよりも小さい。これにより、ゲート電極ＧＥが第１透光性基材１９の中を伝搬してくる光Ｌｄを遮光できる。その結果、実施形態１のスイッチング素子Ｔｒは、光リークが低減する。 A semiconductor layer SC is laminated on the first insulating layer 11 . The semiconductor layer SC is made of amorphous silicon, for example, but may be made of polysilicon or an oxide semiconductor. When viewed in the same cross section, the width Lsc of the semiconductor layer SC is smaller than the width Lge of the gate electrode GE overlapping the semiconductor layer SC. This allows the gate electrode GE to block the light Ld propagating through the first translucent base material 19 . As a result, the switching element Tr of the first embodiment reduces light leakage.

第１絶縁層１１上には、半導体層ＳＣの一部を覆うソース電極ＳＥ及び信号線ＳＬと、半導体層ＳＣの一部を覆うドレイン電極ＤＥとが設けられている。ドレイン電極ＤＥは、信号線ＳＬと同じ材料で形成されている。半導体層ＳＣ、信号線ＳＬ及びドレイン電極ＤＥ上には、第２絶縁層１２が設けられている。第２絶縁層１２は、例えば、第１絶縁層と同様に、窒化シリコンなどの透明な無機絶縁材料によって形成される。 A source electrode SE and a signal line SL covering part of the semiconductor layer SC, and a drain electrode DE covering part of the semiconductor layer SC are provided on the first insulating layer 11 . The drain electrode DE is made of the same material as the signal line SL. A second insulating layer 12 is provided on the semiconductor layer SC, the signal line SL and the drain electrode DE. The second insulating layer 12 is made of, for example, a transparent inorganic insulating material such as silicon nitride, like the first insulating layer.

第２絶縁層１２上には、第２絶縁層１２の一部を覆う第３絶縁層が形成されている。第３絶縁層１３は、例えばアクリル樹脂などの透光性を有する有機絶縁材料により形成されている。第３絶縁層１３は、無機系材料によって形成された他の絶縁膜と比べて厚い膜厚を有している。 A third insulating layer is formed on the second insulating layer 12 to partially cover the second insulating layer 12 . The third insulating layer 13 is made of a translucent organic insulating material such as acrylic resin. The third insulating layer 13 is thicker than other insulating films made of inorganic material.

図１５、図１６及び図１７に示すように、第３絶縁層１３がある領域と、第３絶縁層１３がない領域とがある。図１６及び図１７に示すように、第３絶縁層１３がある領域は、走査線ＧＬの上方及び信号線ＳＬの上方である。第３絶縁層１３は、走査線ＧＬ及び信号線ＳＬに沿って走査線ＧＬ及び信号線ＳＬの上方を覆う格子状になる。また、図１５に示すように、第３絶縁層１３がある領域は、半導体層ＳＣの上方、つまりスイッチング素子Ｔｒの上方である。このため、スイッチング素子Ｔｒ、走査線ＧＬ、信号線ＳＬは保持容量電極ＩＴＯから比較的距離をおいて離れることで、保持容量電極ＩＴＯからのコモン電位の影響を受けにくくなる。さらに、アレイ基板１０において、走査線ＧＬと信号線ＳＬとに囲まれた領域には第３絶縁層１３がない領域ができるので、平面視で信号線ＳＬ及び走査線ＧＬに重なる絶縁層の厚さよりも絶縁層の厚さが小さい領域ができる。走査線ＧＬと信号線ＳＬとに囲まれた領域では、走査線ＧＬの上方及び信号線ＳＬの上方よりも相対的に、光の透過率が向上し、透光性が向上する。 As shown in FIGS. 15, 16 and 17, there are regions with the third insulating layer 13 and regions without the third insulating layer 13 . As shown in FIGS. 16 and 17, the region where the third insulating layer 13 is located is above the scanning lines GL and above the signal lines SL. The third insulating layer 13 has a lattice shape along the scanning lines GL and the signal lines SL to cover the upper side of the scanning lines GL and the signal lines SL. Further, as shown in FIG. 15, the region where the third insulating layer 13 is located is above the semiconductor layer SC, that is, above the switching element Tr. Therefore, the switching element Tr, the scanning line GL, and the signal line SL are separated from the holding capacitor electrode ITO at a relatively long distance, so that they are less likely to be affected by the common potential from the holding capacitor electrode ITO. Furthermore, in the array substrate 10, a region surrounded by the scanning lines GL and the signal lines SL has a region without the third insulating layer 13. Therefore, the thickness of the insulating layer overlapping the signal lines SL and the scanning lines GL in a plan view is A region where the thickness of the insulating layer is smaller than the thickness is created. In the region surrounded by the scanning lines GL and the signal lines SL, the light transmittance and translucency are relatively improved compared to the regions above the scanning lines GL and above the signal lines SL.

図１５に示すように、第３絶縁層１３上には、保持容量電極ＩＯが設けられている。保持容量電極ＩＯは、ＩＴＯ（Ｉｎｄｉｕｍ Ｔｉｎ Ｏｘｉｄｅ）などの透光性導電材料によって形成されている。保持容量電極ＩＯは、第３透光性電極ともいう。図１１に示すように、保持容量電極ＩＯは、走査線ＧＬと信号線ＳＬとに囲まれた領域に透光性導電材料がない領域ＩＯＸを有する。保持容量電極ＩＯは、隣り合う画素Ｐｉｘに跨がって、複数の画素Ｐｉｘに渡って設けられている。保持容量電極ＩＯは、透光性導電材料がある領域が走査線ＧＬ又は信号線ＳＬに重なり、隣の画素Ｐｉｘに延びている。 As shown in FIG. 15, a storage capacitor electrode IO is provided on the third insulating layer 13 . The storage capacitor electrode IO is made of a translucent conductive material such as ITO (Indium Tin Oxide). The storage capacitor electrode IO is also called a third translucent electrode. As shown in FIG. 11, the storage capacitor electrode IO has an area IOX where there is no translucent conductive material in the area surrounded by the scanning lines GL and the signal lines SL. The storage capacitor electrode IO is provided across a plurality of pixels Pix, straddling adjacent pixels Pix. In the storage capacitor electrode IO, a region with a translucent conductive material overlaps the scanning line GL or the signal line SL and extends to the adjacent pixel Pix.

保持容量電極ＩＯは、走査線ＧＬ及び信号線ＳＬに沿って走査線ＧＬ及び信号線ＳＬの上方を覆う格子状である。これにより、透光性導電材料がない領域ＩＯＸと、画素電極ＰＥとの間の保持容量ＨＣが減少するので、透光性導電材料がない領域ＩＯＸの大きさにより保持容量ＨＣが調整される。 The storage capacitor electrode IO has a lattice shape along the scanning lines GL and the signal lines SL and covers the upper side of the scanning lines GL and the signal lines SL. As a result, the holding capacitance HC between the region IOX without the translucent conductive material and the pixel electrode PE is reduced, so that the holding capacitance HC is adjusted according to the size of the region IOX without the translucent conductive material.

図１５に示すように、保持容量電極ＩＯ上の一部には、導電性の金属層ＴＭが設けられている。導電性の金属層ＴＭは、モリブデン（Ｍｏ）、アルミニウム（Ａｌ）等の金属、これらの積層体又はこれらの合金の配線である。図１２に示すように、金属層ＴＭは、平面視において、信号線ＳＬ、走査線ＧＬ及びスイッチング素子Ｔｒに重なる領域に設けられている。これにより、金属層ＴＭは、格子状となり、金属層ＴＭで囲まれた開口部ＡＰができる。 As shown in FIG. 15, a conductive metal layer TM is provided on a portion of the storage capacitor electrode IO. The conductive metal layer TM is wiring of a metal such as molybdenum (Mo) or aluminum (Al), a laminate thereof, or an alloy thereof. As shown in FIG. 12, the metal layer TM is provided in a region overlapping with the signal lines SL, the scanning lines GL, and the switching elements Tr in plan view. As a result, the metal layer TM becomes grid-like, and an opening AP surrounded by the metal layer TM is formed.

図１２に示すように、走査線ＧＬと信号線ＳＬとに接続されたスイッチング素子Ｔｒが設けられ、少なくともスイッチング素子Ｔｒは、有機絶縁層である第３絶縁層１３で覆われており、第３絶縁層１３の上方にはスイッチング素子Ｔｒよりも大きな面積の金属層ＴＭがある。これにより、スイッチング素子Ｔｒの光リークを抑制することができる。 As shown in FIG. 12, a switching element Tr connected to the scanning line GL and the signal line SL is provided, and at least the switching element Tr is covered with a third insulating layer 13 which is an organic insulating layer. Above the insulating layer 13 is a metal layer TM having an area larger than that of the switching element Tr. Thereby, the light leakage of the switching element Tr can be suppressed.

金属層ＴＭは、保持容量電極ＩＯの下にあってもよく、保持容量電極ＩＯと積層されていればよい。金属層ＴＭは、保持容量電極ＩＯよりも電気抵抗が小さい。このため、表示領域ＡＡのうち画素Ｐｉｘがある位置による保持容量電極ＩＯの電位のばらつきが抑制される。 The metal layer TM may be under the storage capacitor electrode IO, and may be laminated with the storage capacitor electrode IO. The metal layer TM has an electrical resistance smaller than that of the storage capacitor electrode IO. Therefore, variation in the potential of the storage capacitor electrode IO depending on the position of the pixel Pix in the display area AA is suppressed.

図１２に示すように、平面視で、信号線ＳＬに重なる金属層ＴＭの幅は、信号線ＳＬの幅よりも大きい。これにより、信号線ＳＬのエッジで反射する反射光を表示パネル２より放出することを抑制する。ここで、金属層ＴＭの幅及び信号線ＳＬの幅は、信号線ＳＬの延在する方向に交差する方向の長さである。また、走査線ＧＬに重なる金属層ＴＭの幅は、走査線ＧＬの幅よりも大きい。ここで、金属層ＴＭの幅及び走査線ＧＬの幅は、走査線ＧＬの延在する方向に交差する方向の長さである。 As shown in FIG. 12, in plan view, the width of the metal layer TM overlapping the signal line SL is larger than the width of the signal line SL. This suppresses emission from the display panel 2 of the reflected light reflected by the edge of the signal line SL. Here, the width of the metal layer TM and the width of the signal line SL are the lengths in the direction crossing the extending direction of the signal line SL. Also, the width of the metal layer TM overlapping the scanning line GL is larger than the width of the scanning line GL. Here, the width of the metal layer TM and the width of the scanning line GL are the lengths in the direction crossing the direction in which the scanning line GL extends.

図１５に示すように、保持容量電極ＩＯ及び金属層ＴＭの上には、第４絶縁層１４が設けられている。第４絶縁層１４は、例えば、窒化シリコンなどの透明な無機絶縁材料によって形成されている無機絶縁層である。 As shown in FIG. 15, a fourth insulating layer 14 is provided on the storage capacitor electrode IO and the metal layer TM. The fourth insulating layer 14 is an inorganic insulating layer made of, for example, a transparent inorganic insulating material such as silicon nitride.

図１５に示すように、第４絶縁層１４上には、画素電極ＰＥが設けられている。画素電極ＰＥは、ＩＴＯなどの透光性導電材料によって形成されている。画素電極ＰＥは、第４絶縁層１４及び第３絶縁層１３及び第２絶縁層１２に設けられたコンタクトホールＣＨを介してコンタクト電極ＤＥＡと電気的に接続されている。図１３に示すように、画素電極ＰＥは、画素Ｐｉｘ毎に区画されている。画素電極ＰＥの上には、第１配向膜ＡＬ１が設けられている。 As shown in FIG. 15, pixel electrodes PE are provided on the fourth insulating layer 14 . The pixel electrode PE is made of a translucent conductive material such as ITO. The pixel electrode PE is electrically connected to the contact electrode DEA through the contact hole CH provided in the fourth insulating layer 14, the third insulating layer 13 and the second insulating layer 12. FIG. As shown in FIG. 13, the pixel electrode PE is divided for each pixel Pix. A first alignment film AL1 is provided on the pixel electrode PE.

図１５に示すように、対向基板２０は、例えばガラスで形成された第２透光性基材２９を有している。第２透光性基材２９は、透光性を有していれば、ポリエチレンテレフタレートなどの樹脂でもよい。第２透光性基材２９には、共通電極ＣＥが設けられている。共通電極ＣＥは、ＩＴＯなどの透光性導電材料によって形成されている。共通電極ＣＥの表面には、第２配向膜ＡＬ２が設けられている。また、対向基板２０は、第２透光性基材２９と共通電極ＣＥとの間に遮光層ＬＳを有する。遮光層ＬＳは黒色の樹脂又は金属材料で形成されている。また、アレイ基板１０と対向基板２０との間にスペーサＰＳが形成され、スペーサＰＳは共通電極ＣＥと第２配向膜ＡＬ２との間にある。 As shown in FIG. 15, the opposing substrate 20 has a second translucent base material 29 made of glass, for example. The second translucent base material 29 may be a resin such as polyethylene terephthalate as long as it has translucency. A common electrode CE is provided on the second translucent base material 29 . The common electrode CE is made of a translucent conductive material such as ITO. A second alignment film AL2 is provided on the surface of the common electrode CE. In addition, the counter substrate 20 has a light shielding layer LS between the second translucent base material 29 and the common electrode CE. The light shielding layer LS is made of black resin or metal material. A spacer PS is formed between the array substrate 10 and the counter substrate 20, and the spacer PS is between the common electrode CE and the second alignment film AL2.

図１２及び図１６に示すように、実施形態１の表示装置では、走査線ＧＬと同層の遮光層ＧＳが、信号線ＳＬに沿って延在し、かつ信号線ＳＬの一部と重なる位置に設けられている。遮光層ＧＳは、走査線ＧＬと同じ材料で形成されている。遮光層ＧＳは、走査線ＧＬと信号線ＳＬとが平面視において交差する部分には設けられていない。 As shown in FIGS. 12 and 16, in the display device of Embodiment 1, the light shielding layer GS, which is the same layer as the scanning line GL, extends along the signal line SL and overlaps a part of the signal line SL. is provided in The light shielding layer GS is made of the same material as the scanning lines GL. The light shielding layer GS is not provided in the portion where the scanning line GL and the signal line SL intersect in plan view.

図１２に示すように、遮光層ＧＳと、信号線ＳＬとは、コンタクトホールＣＨＧで電気的に接続されている。これにより、信号線ＳＬのみの配線抵抗に比べて、遮光層ＧＳ及び信号線ＳＬで構成する配線抵抗が下がる。その結果、信号線ＳＬに供給された階調信号の遅延が抑制される。なお、コンタクトホールＣＨＧがなく、遮光層ＧＳと、信号線ＳＬとが接続されていなくてもよい。 As shown in FIG. 12, the light shielding layer GS and the signal line SL are electrically connected through a contact hole CHG. As a result, the wiring resistance formed by the light shielding layer GS and the signal line SL is lower than the wiring resistance of the signal line SL alone. As a result, the delay of the gradation signal supplied to the signal line SL is suppressed. It should be noted that the contact hole CHG may not exist and the light shielding layer GS and the signal line SL may not be connected.

図１６に示すように、遮光層ＧＳは、信号線ＳＬに対して金属層ＴＭとは反対側に設けられている。遮光層ＧＳの幅は、信号線ＳＬの幅よりも大きく、金属層ＴＭの幅より小さい。遮光層ＧＳの幅、金属層ＴＭの幅及び信号線ＳＬの幅は、信号線ＳＬの延在する方向に交差する方向の長さである。このように、遮光層ＧＳは、信号線ＳＬよりも幅が広くなっているので、信号線ＳＬのエッジで反射する反射光を表示パネル２より放出することを抑制する。その結果、表示装置１において、画像の視認性が向上する。 As shown in FIG. 16, the light shielding layer GS is provided on the side opposite to the metal layer TM with respect to the signal line SL. The width of the light shielding layer GS is larger than the width of the signal line SL and smaller than the width of the metal layer TM. The width of the light shielding layer GS, the width of the metal layer TM, and the width of the signal line SL are the lengths in the direction crossing the extending direction of the signal line SL. As described above, the light shielding layer GS is wider than the signal line SL, and thus suppresses the emission of the reflected light reflected by the edge of the signal line SL from the display panel 2 . As a result, the visibility of the image is improved in the display device 1 .

図１４及び図１５に示すように、対向基板２０には、遮光層ＬＳが設けられている。遮光層ＬＳは、平面視において、信号線ＳＬ、走査線ＧＬ及びスイッチング素子Ｔｒに重なる領域に設けられている。 As shown in FIGS. 14 and 15, the counter substrate 20 is provided with a light shielding layer LS. The light shielding layer LS is provided in a region overlapping with the signal line SL, the scanning line GL, and the switching element Tr in plan view.

図１４、図１５、図１６及び図１７に示すように、遮光層ＬＳは、金属層ＴＭよりも大きい幅を有している。これにより、信号線ＳＬ、走査線ＧＬ及び金属層ＴＭのエッジで反射する反射光を表示パネル２より放出することを抑制する。その結果、表示装置１において、画像の視認性が向上する。 As shown in FIGS. 14, 15, 16 and 17, the light shielding layer LS has a width greater than that of the metal layer TM. This suppresses emission from the display panel 2 of reflected light reflected by the edges of the signal lines SL, the scanning lines GL, and the metal layer TM. As a result, the visibility of the image is improved in the display device 1 .

コンタクトホールＣＨ及びコンタクトホールＣＨＧは、光源光Ｌが当たると乱反射しやすい。このため、遮光層ＬＳは、平面視において、コンタクトホールＣＨ及びコンタクトホールＣＨＧに重なる領域に設けられている。 The contact hole CH and the contact hole CHG are likely to be diffusely reflected when the light source light L hits them. Therefore, the light shielding layer LS is provided in a region overlapping with the contact hole CH and the contact hole CHG in plan view.

図１５に示すように、アレイ基板１０と対向基板２０との間には、スペーサＳＰが配置され、アレイ基板１０と対向基板２０との間の距離の均一性を向上する。 As shown in FIG. 15, spacers SP are arranged between the array substrate 10 and the counter substrate 20 to improve the uniformity of the distance between the array substrate 10 and the counter substrate 20 .

図１８に示すように、周辺領域ＦＲでは、コモン電位配線ＣＯＭＬが引き回されている。コモン電位配線ＣＯＭＬは、例えば第１コモン電位配線ＣＯＭＬ１と、第２コモン電位配線ＣＯＭＬ２とを備える。第１コモン電位配線ＣＯＭＬ１は、導電性の導電部材ＣＰを介して、対向基板２０の共通電極ＣＥに電気的に接続している。導電部材ＣＰは導電注（ピラー）でもよく、またＡｕ粒子などの導電粒子が含有されたシール材であってもよい。 As shown in FIG. 18, in the peripheral region FR, common potential lines COML are routed. The common potential wiring COML includes, for example, a first common potential wiring COML1 and a second common potential wiring COML2. The first common potential wiring COML1 is electrically connected to the common electrode CE of the counter substrate 20 via the conductive member CP. The conductive member CP may be a conductive filler (pillar), or may be a sealing material containing conductive particles such as Au particles.

図１８に示すように、周辺領域ＦＲでは、保持容量電極ＩＯが第２コモン電位配線ＣＯＭＬ２と電気的に接続している。金属層ＴＭは、表示領域ＡＡに配置されている。 As shown in FIG. 18, in the peripheral region FR, the holding capacitor electrode IO is electrically connected to the second common potential wiring COML2. The metal layer TM is arranged in the display area AA.

以上説明したように、表示装置１は、アレイ基板１０と、対向基板２０と、液晶層５０と、光源３を備える。アレイ基板１０は、画素Ｐｉｘ毎に配置された第１透光性電極である複数の画素電極ＰＥを有する。アレイ基板１０には、第１方向ＰＸに間隔をおいて並ぶ複数の信号線ＳＬと、第２方向ＰＹに間隔をおいて並ぶ複数の走査線ＧＬと、が設けられている。対向基板２０は、平面視で、画素電極ＰＥと重畳する位置に第２透光性電極である共通電極ＣＥを有する。液晶層５０は、アレイ基板１０と対向基板２０との間に封入される高分子分散型液晶ＬＣを有する。光源３の発光部３１は、対向基板２０の側面に対し、第２方向ＰＹに光を発光する。アレイ基板１０及び対向基板２０を伝播する光の入射方向は、第２方向である。なお、発光部３１は、アレイ基板１０の側面に向かって、アレイ基板１０及び対向基板２０を伝播する光を発光するようにしてもよい。 As described above, the display device 1 includes the array substrate 10 , the opposing substrate 20 , the liquid crystal layer 50 and the light source 3 . The array substrate 10 has a plurality of pixel electrodes PE, which are first translucent electrodes, arranged for each pixel Pix. The array substrate 10 is provided with a plurality of signal lines SL arranged at intervals in the first direction PX and a plurality of scanning lines GL arranged at intervals in the second direction PY. The counter substrate 20 has a common electrode CE, which is a second translucent electrode, at a position overlapping with the pixel electrode PE in plan view. The liquid crystal layer 50 has polymer dispersed liquid crystal LC sealed between the array substrate 10 and the counter substrate 20 . The light emitting part 31 of the light source 3 emits light in the second direction PY to the side surface of the counter substrate 20 . The incident direction of light propagating through the array substrate 10 and the counter substrate 20 is the second direction. The light emitting section 31 may emit light propagating through the array substrate 10 and the counter substrate 20 toward the side surface of the array substrate 10 .

アレイ基板１０には、少なくともスイッチング素子Ｔｒを覆う有機絶縁層である第３絶縁層１３と、第３絶縁層１３の上方に重畳して設けられ、スイッチング素子Ｔｒよりも大きな面積の金属層ＴＭとがある。走査線ＧＬと信号線ＳＬとに囲まれた領域には、平面視で走査線ＧＬ及び信号線ＳＬに重なる第３絶縁層１３の厚さよりも厚さが小さい領域がある。このため、平面視でスイッチング素子Ｔｒよりも光源３に近い側にある第３絶縁層１３の厚みが変化する斜面であって、図１５に示すようにスイッチング素子Ｔｒに重畳する第３絶縁層１３の第１斜面１３ｔ１が金属層ＴＭｔで覆われている。ここで、金属層ＴＭｔは、金属層ＴＭと同じ材料で形成され、金属層ＴＭが延在して形成されたテーパー状の部分である。 The array substrate 10 includes a third insulating layer 13 which is an organic insulating layer covering at least the switching elements Tr, and a metal layer TM which is provided over the third insulating layer 13 and has a larger area than the switching elements Tr. There is A region surrounded by the scanning lines GL and the signal lines SL has a region whose thickness is smaller than the thickness of the third insulating layer 13 overlapping the scanning lines GL and the signal lines SL in plan view. For this reason, the slope where the thickness of the third insulating layer 13 on the side closer to the light source 3 than the switching element Tr in plan view changes, and the third insulating layer 13 overlapping the switching element Tr as shown in FIG. is covered with a metal layer TMt. Here, the metal layer TMt is formed of the same material as the metal layer TM, and is a tapered portion formed by extending the metal layer TM.

図５及び図２０に示すように、光源３から照射された光源光Ｌは、第２方向ＰＹを入射方向として、入射してくる。図１５に示すように、光Ｌｕが到達する。光Ｌｕは、スイッチング素子Ｔｒよりも光源３に近い側から到達する光源光Ｌの一部の光である。ここで、金属層ＴＭｔは、光Ｌｕを遮光するので、光リークが低減される。 As shown in FIGS. 5 and 20, the light source light L emitted from the light source 3 is incident with the second direction PY as the incident direction. As shown in FIG. 15, the light Lu arrives. The light Lu is part of the light source light L arriving from the side closer to the light source 3 than the switching element Tr. Here, since the metal layer TMt shields the light Lu, light leakage is reduced.

なお、第３絶縁層１３の厚みが変化する斜面であって、スイッチング素子Ｔｒに重畳する第３絶縁層１３の第１斜面以外の斜面については、金属層ＴＭがなくてもよい。 The slopes other than the first slope of the third insulating layer 13 overlapping the switching element Tr may not have the metal layer TM.

（実施形態２）
図１９は、実施形態２の画素を示す平面図である。上述した本実施形態で説明したものと同じ構成要素には同一の符号を付して重複する説明は省略する。 (Embodiment 2)
FIG. 19 is a plan view showing a pixel of Embodiment 2. FIG. The same reference numerals are assigned to the same components as those described in the above-described embodiment, and duplicate descriptions are omitted.

図１９に示すように、実施形態２の画素Ｐｉｘの構成は、実施形態１の画素Ｐｉｘの構成と異なり、隣り合う画素Ｐｉｘの間に２つの信号線ＳＬがある。一方の信号線ＳＬは、１つ置きの画素Ｐｉｘの走査線ＧＬとの交差部分にあるスイッチング素子Ｔｒ１と電気的に接続される。他方の信号線ＳＬは、スイッチング素子Ｔｒ１がある画素Ｐｉｘを除いて１つ置きの画素Ｐｉｘの走査線ＧＬとの交差部分にあるスイッチング素子Ｔｒ２と電気的に接続される。 As shown in FIG. 19, the configuration of the pixel Pix of the second embodiment differs from the configuration of the pixel Pix of the first embodiment, and there are two signal lines SL between adjacent pixels Pix. One signal line SL is electrically connected to the switching element Tr1 at the intersection of every other pixel Pix with the scanning line GL. The other signal line SL is electrically connected to the switching element Tr2 at the intersection of every other pixel Pix with the scanning line GL except for the pixel Pix where the switching element Tr1 is located.

これにより、ゲート駆動回路４３が隣り合う２つの走査線ＧＬを同時に選択することができる。その結果、図３に示す１垂直走査時間ＧａｔｅＳｃａｎが短くなる。各１垂直走査期間ＧａｔｅＳｃａｎが短くなると、各１垂直走査期間ＧａｔｅＳｃａｎの後にある第１色の発光期間ＲＯＮ、第２色の発光期間ＧＯＮ及び第３色の発光期間ＢＯＮが相対的に長くすることができる。 This allows the gate drive circuit 43 to simultaneously select two adjacent scanning lines GL. As a result, one vertical scanning time GateScan shown in FIG. 3 is shortened. When each vertical scanning period GateScan is shortened, the first color light emission period RON, the second color light emission period GON, and the third color light emission period BON after each vertical scanning period GateScan can be relatively lengthened. can.

（実施形態３）
図２０は、実施形態３の表示装置の平面を示す平面図である。図２１は、実施形態３の画素において、走査線、信号線及びスイッチング素子を示す平面図である。図２２は、図２１のＸＸＩＩ－ＸＸＩＩ’の断面図である。上述した本実施形態で説明したものと同じ構成要素には同一の符号を付して重複する説明は省略する。 (Embodiment 3)
20 is a plan view showing the plane of the display device of Embodiment 3. FIG. 21 is a plan view showing scanning lines, signal lines, and switching elements in the pixel of Embodiment 3. FIG. 22 is a cross-sectional view taken along line XXII-XXII' of FIG. 21. FIG. The same reference numerals are assigned to the same components as those described in the above-described embodiment, and duplicate descriptions are omitted.

図２０に示すように、光源３は、アレイ基板１０の第３側面１０Ｅ又は対向基板２０の第３側面２０Ｅに対向する。例えば、図２０に示すように、光源３は、対向基板２０の第３側面１０Ｅへ光源光Ｌを照射する。光源３と対向する対向基板２０の第３側面１０Ｅは、光入射面となる。光源３から照射された光源光Ｌは、アレイ基板１０の第１主面１０Ａ及び対向基板２０の第１主面２０Ａで反射しながら、アレイ基板１０の第３側面１０Ｅ又は対向基板２０の第３側面２０Ｅから遠ざかる方向（第１方向ＰＸ）に伝播する。 As shown in FIG. 20 , the light source 3 faces the third side surface 10E of the array substrate 10 or the third side surface 20E of the counter substrate 20 . For example, as shown in FIG. 20, the light source 3 irradiates the third side surface 10E of the counter substrate 20 with the light source light L. As shown in FIG. A third side surface 10E of the counter substrate 20 facing the light source 3 serves as a light incident surface. The light source light L emitted from the light source 3 is reflected by the first main surface 10A of the array substrate 10 and the first main surface 20A of the counter substrate 20, and is reflected by the third side surface 10E of the array substrate 10 or the third surface of the counter substrate 20. It propagates in a direction (first direction PX) away from the side surface 20E.

図２１に示すように、実施形態３の画素Ｐｉｘの構成は、実施形態１の画素Ｐｉｘの構成と異なり、隣り合う画素Ｐｉｘの間に２つの信号線ＳＬがある。一方の信号線ＳＬは、１つ置きの画素Ｐｉｘの走査線ＧＬとの交差部分にあるスイッチング素子Ｔｒ１と電気的に接続される。他方の信号線ＳＬは、スイッチング素子Ｔｒ１がある画素Ｐｉｘを除いて１つ置きの画素Ｐｉｘの走査線ＧＬとの交差部分にあるスイッチング素子Ｔｒ２と電気的に接続される。 As shown in FIG. 21, the configuration of the pixel Pix of the third embodiment differs from the configuration of the pixel Pix of the first embodiment, and there are two signal lines SL between adjacent pixels Pix. One signal line SL is electrically connected to the switching element Tr1 at the intersection of every other pixel Pix with the scanning line GL. The other signal line SL is electrically connected to the switching element Tr2 at the intersection of every other pixel Pix with the scanning line GL except for the pixel Pix where the switching element Tr1 is located.

これにより、ゲート駆動回路４３が隣り合う２つの走査線ＧＬを同時に選択することができる。その結果、図３に示す１垂直走査時間ＧａｔｅＳｃａｎが短くなる。図３に示す１垂直走査期間ＧａｔｅＳｃａｎが短くなると、各１垂直走査期間ＧａｔｅＳｃａｎの後にある第１色の発光期間ＲＯＮ、第２色の発光期間ＧＯＮ及び第３色の発光期間ＢＯＮが相対的に長くすることができる。 This allows the gate drive circuit 43 to simultaneously select two adjacent scanning lines GL. As a result, one vertical scanning time GateScan shown in FIG. 3 is shortened. When one vertical scanning period GateScan shown in FIG. 3 is shortened, the light emission period RON of the first color, the light emission period GON of the second color, and the light emission period BON of the third color after each vertical scanning period GateScan become relatively long. can do.

図２１及び図２２に示すように、光源光Ｌは、第１方向ＰＸに沿って伝搬する。光の入光方向が第１方向ＰＸに沿う方向であることから、図２０に示すように、スイッチング素子Ｔｒ１から光源３の発光部３１がある側の入光方向には、遮光構造体ＳＧＳがある。入光方向に交差する第２方向ＰＹにおいて、遮光構造体ＳＧＳの長さは、半導体層ＳＣの長さよりも大きい。これにより、遮光構造体ＳＧＳは、スイッチング素子Ｔｒへ伝播する光路を遮り、スイッチング素子Ｔｒ１の光リークを抑制することができる。 As shown in FIGS. 21 and 22, the light source light L propagates along the first direction PX. Since the light incident direction is the direction along the first direction PX, as shown in FIG. be. In a second direction PY that intersects the direction of incidence of light, the length of the shading structure SGS is greater than the length of the semiconductor layer SC. Thereby, the light shielding structure SGS can block the optical path propagating to the switching element Tr and suppress the light leakage of the switching element Tr1.

遮光構造体ＳＧＳは、走査線ＧＬと同層の遮光層ＧＳが延長され、遮光層ＧＳの導電材料の上に、信号線ＳＬと同層の導電材料で形成された第１遮光層ＳＭが積層されている。このように、遮光構造体ＳＧＳは、信号線ＳＬの延長線上にある。 In the light-shielding structure SGS, a light-shielding layer GS in the same layer as the scanning lines GL is extended, and a first light-shielding layer SM made of a conductive material in the same layer as the signal lines SL is laminated on the conductive material of the light-shielding layer GS. It is Thus, the light shielding structure SGS is on the extension line of the signal line SL.

図２１及び図２２に示すように、スイッチング素子Ｔｒは、有機絶縁層である第３絶縁層１３で覆われており、入射方向の第３絶縁層１３の第１斜面１３ｔ１は、金属層ＴＭｔで覆われている。これにより、金属層ＴＭｔは、スイッチング素子Ｔｒ１へ伝播する光路を遮り、スイッチング素子Ｔｒ１の光リークを抑制することができる。 As shown in FIGS. 21 and 22, the switching element Tr is covered with the third insulating layer 13, which is an organic insulating layer. covered. Thereby, the metal layer TMt blocks the optical path propagating to the switching element Tr1, and can suppress the light leakage of the switching element Tr1.

図２２に示すように、アレイ基板１０には、少なくともスイッチング素子Ｔｒ１を覆う有機絶縁層である第３絶縁層１３と、第３絶縁層１３の上方に重畳して設けられ、スイッチング素子Ｔｒ１よりも大きな面積の金属層ＴＭとがある。走査線ＧＬと信号線ＳＬとに囲まれた領域には、平面視で走査線ＧＬ及び信号線ＳＬに重なる第３絶縁層１３の厚さよりも厚さが小さい領域がある。このため、平面視でスイッチング素子Ｔｒ１よりも光源３に近い側にある第３絶縁層１３の厚みが変化する斜面であって、スイッチング素子Ｔｒ１に重畳する第３絶縁層１３の第１斜面１３ｔ１が金属層ＴＭｔで覆われている。ここで、金属層ＴＭｔは、金属層ＴＭと同じ材料で形成され、金属層ＴＭが延在して形成されたテーパー状の部分である。 As shown in FIG. 22, the array substrate 10 includes a third insulating layer 13, which is an organic insulating layer covering at least the switching element Tr1, and a third insulating layer 13 overlapping the third insulating layer 13 above the switching element Tr1. There is a large area metal layer TM. A region surrounded by the scanning lines GL and the signal lines SL has a region whose thickness is smaller than the thickness of the third insulating layer 13 overlapping the scanning lines GL and the signal lines SL in plan view. Therefore, the first slope 13t1 of the third insulating layer 13 overlapping with the switching element Tr1 is the slope where the thickness of the third insulating layer 13 changes on the side closer to the light source 3 than the switching element Tr1 in plan view. It is covered with a metal layer TMt. Here, the metal layer TMt is formed of the same material as the metal layer TM, and is a tapered portion formed by extending the metal layer TM.

図２１に示すように、平面視でスイッチング素子Ｔｒ１よりも光源３から遠い側にある第３絶縁層１３の厚みが変化する斜面であって、スイッチング素子Ｔｒ１に重畳する第３絶縁層１３の第２斜面１３ｔ２が金属層ＴＭｔで覆われている。これにより、光リークが低減される。 As shown in FIG. 21, the slope of the thickness of the third insulating layer 13 on the side farther from the light source 3 than the switching element Tr1 in plan view changes. 2 slope 13t2 is covered with metal layer TMt. This reduces light leakage.

遮光構造体ＳＧＳは、第３絶縁層１３、金属層ＴＭ及び金属層ＴＭｔで覆われている。これにより、金属層ＴＭｔを通過した光Ｌｕを遮光構造体ＳＧＳが遮光する。 The light shielding structure SGS is covered with a third insulating layer 13, a metal layer TM and a metal layer TMt. As a result, the light shielding structure SGS shields the light Lu that has passed through the metal layer TMt.

このように、第１斜面１３ｔ１と、スイッチング素子Ｔｒ１との間には、遮光構造体ＳＧＳがある。これにより、金属層ＴＭｔと、遮光構造体ＳＧＳとにより、光Ｌｕがよりスイッチング素子Ｔｒ１に到達しにくくなる。 Thus, there is a light blocking structure SGS between the first slope 13t1 and the switching element Tr1. As a result, the metal layer TMt and the light shielding structure SGS make it more difficult for the light Lu to reach the switching element Tr1.

（変形例）
実施形態１から４について、スイッチング素子Ｔｒがボトムゲート型であるとして説明を行ったが、上述しているようにスイッチング素子Ｔｒは、ボトムゲート構造に限らずトップゲート型であってもよい。スイッチング素子Ｔｒがトップゲート型であれば、図１５の絶縁膜積層構造を参考に説明すると、半導体層ＳＣは第１透光性基材１９と第１絶縁層その間に配置され、ゲート電極ＧＥは第１絶縁層１１と第２絶縁層１２との間に配置され、ソース電極ＳＥ及びコンタクト電極ＤＥＡは第２絶縁層１２と第３絶縁層１３との間に形成される構造となる。 (Modification)
Embodiments 1 to 4 have been described assuming that the switching element Tr is of the bottom gate type. If the switching element Tr is of the top-gate type, the semiconductor layer SC is arranged between the first translucent substrate 19 and the first insulating layer, and the gate electrode GE is located between the first transparent substrate 19 and the first insulating layer. The structure is arranged between the first insulating layer 11 and the second insulating layer 12 , and the source electrode SE and the contact electrode DEA are formed between the second insulating layer 12 and the third insulating layer 13 .

さらに、コモン電位については、直流電圧が供給される、つまり一定のコモン電位であってもよく、また交流電圧が共有される、つまり上限値と下限値の２つを有するコモン電位であってもよい。コモン電位が直流であっても交流であっても保持容量電極ＩＯ及び共通電極ＣＥには共通の電位が供給される。 Furthermore, the common potential may be supplied with a DC voltage, that is, a constant common potential, or may be shared with an AC voltage, that is, a common potential having two upper and lower limits. good. A common potential is supplied to the storage capacitor electrode IO and the common electrode CE regardless of whether the common potential is a direct current or an alternating current.

また、格子状の有機絶縁膜である第３絶縁層１３については、格子状の内側の第３絶縁層１３が完全に除去され下層の第２絶縁層１２や保持容量電極ＩＯを露出する構造を開示しているが、これに限られない。例えば、複数の信号線ＳＬと複数の走査線ＧＬとで囲まれる格子状領域の内側については、ハーフトーン露光で第３絶縁層１３の膜厚の一部を薄く残す構造であってもよい。これにより、第３絶縁層１３は、複数の信号線ＳＬと複数の走査線ＧＬとで囲まれる格子状領域よりも、格子状領域の内側の膜厚が薄くなる。 Further, regarding the third insulating layer 13, which is a grid-like organic insulating film, the third insulating layer 13 inside the grid-like structure is completely removed to expose the underlying second insulating layer 12 and the storage capacitor electrode IO. Disclosed, but not limited to. For example, halftone exposure may be applied to leave part of the thickness of the third insulating layer 13 thin inside the grid-like region surrounded by the plurality of signal lines SL and the plurality of scanning lines GL. As a result, the thickness of the third insulating layer 13 becomes thinner inside the grid-like region than in the grid-like region surrounded by the plurality of signal lines SL and the plurality of scanning lines GL.

以上、好適な実施の形態を説明したが、本開示はこのような実施の形態に限定されるものではない。実施の形態で開示された内容はあくまで一例にすぎず、本開示の趣旨を逸脱しない範囲で種々の変更が可能である。本開示の趣旨を逸脱しない範囲で行われた適宜の変更についても、当然に本開示の技術的範囲に属する。 Although preferred embodiments have been described above, the present disclosure is not limited to such embodiments. The content disclosed in the embodiment is merely an example, and various modifications are possible without departing from the gist of the present disclosure. Appropriate changes that do not deviate from the spirit of the present disclosure also naturally belong to the technical scope of the present disclosure.

１ 表示装置
２ 表示パネル
３ 光源
４ 駆動回路
９ 上位制御部
１０ アレイ基板
１１ 第１絶縁層
１２ 第２絶縁層
１３ 第３絶縁層
１４ 第４絶縁層
２０ 対向基板
３１ 発光部
４１ 信号処理回路
４２ 画素制御回路
４３ ゲート駆動回路
４４ ソース駆動回路
４５ 共通電位駆動回路
５０ 液晶層
ＡＰ 開口部
ＣＥ 共通電極
ＣＨ コンタクトホール
ＣＯＭＬ コモン電位配線
ＣＰ 導電部材
ＤＥ ドレイン電極
ＤＥＡ コンタクト電極
ＦＲ 周辺領域
ＧＥ ゲート電極
ＧＬ 走査線
ＧＯＮ 発光期間
ＧＳ 遮光層
ＨＣ 保持容量
ＨＤＳ 水平駆動信号
ＩＯ 保持容量電極
ＩＯＸ 透光性導電材料がない領域
ＬＣ 高分子分散型液晶
ＬＳ 遮光層
ＰＥ 画素電極
ＳＣ 半導体層
ＳＥ ソース電極
ＳＧＳ 遮光構造体
ＴＭ、ＴＭｔ 金属層
Ｔｒ、Ｔｒ１，Ｔｒ２ スイッチング素子 1 Display Device 2 Display Panel 3 Light Source 4 Drive Circuit 9 Upper Control Unit 10 Array Substrate 11 First Insulating Layer 12 Second Insulating Layer 13 Third Insulating Layer 14 Fourth Insulating Layer 20 Counter Substrate 31 Light Emitting Unit 41 Signal Processing Circuit 42 Pixel Control circuit 43 Gate drive circuit 44 Source drive circuit 45 Common potential drive circuit 50 Liquid crystal layer AP Opening CE Common electrode CH Contact hole COML Common potential wiring CP Conductive member DE Drain electrode DEA Contact electrode FR Peripheral region GE Gate electrode GL Scanning line GON Light-emitting period GS Light-shielding layer HC Storage capacitor HDS Horizontal drive signal IO Storage capacitor electrode IOX Region without translucent conductive material LC Polymer-dispersed liquid crystal LS Light-shielding layer PE Pixel electrode SC Semiconductor layer SE Source electrode SGS Light-shielding structures TM, TMt Metal layers Tr, Tr1, Tr2 Switching elements

Claims (10)

アレイ基板と、
対向基板と、
前記アレイ基板と前記対向基板との間の液晶層と、
前記アレイ基板と前記対向基板との間を前記対向基板の一方の側面から他方の側面に向かって光が伝播するように発光する光源と、を備え、
前記アレイ基板は、
第１方向に間隔をおいて並ぶ複数の信号線と、
第２方向に間隔をおいて並ぶ複数の走査線と、
前記走査線と前記信号線とに接続されたスイッチング素子と、
少なくとも前記スイッチング素子を覆う有機絶縁層と、
前記有機絶縁層の上方に重畳して設けられた金属層と、を有し、
前記走査線と前記信号線とに囲まれた領域には、平面視で前記走査線及び前記信号線に重なる前記有機絶縁層の厚さよりも前記有機絶縁層の厚さが小さい領域があり、
前記スイッチング素子よりも前記光源に近い側にある前記有機絶縁層の第１斜面が前記金属層で覆われ、
前記スイッチング素子よりも前記光源から遠い側にある前記有機絶縁層の第２斜面が前記金属層で覆われており、
前記第１斜面と、前記スイッチング素子との間には、遮光構造体がある、
表示装置。 an array substrate;
a counter substrate;
a liquid crystal layer between the array substrate and the counter substrate;
a light source that emits light so that light propagates between the array substrate and the counter substrate from one side surface of the counter substrate to the other side surface;
The array substrate is
a plurality of signal lines arranged at intervals in the first direction;
a plurality of scanning lines spaced apart in a second direction;
a switching element connected to the scanning line and the signal line;
an organic insulating layer covering at least the switching element;
a metal layer provided over the organic insulating layer,
In a region surrounded by the scanning lines and the signal lines, there is a region in which the thickness of the organic insulating layer is smaller than the thickness of the organic insulating layer overlapping the scanning lines and the signal lines in plan view,
a first slope of the organic insulating layer closer to the light source than the switching element is covered with the metal layer;
a second slope of the organic insulating layer on a side farther from the light source than the switching element is covered with the metal layer;
A light shielding structure is between the first slope and the switching element.
display device. 前記金属層は、平面視で、複数の前記信号線及び複数の前記走査線と重なっており、かつ前記有機絶縁層の上で格子状に配置されている請求項１に記載の表示装置。 2. The display device according to claim 1, wherein the metal layer overlaps the plurality of signal lines and the plurality of scanning lines in plan view, and is arranged in a grid pattern on the organic insulating layer. 平面視で、前記信号線に重なる金属層の幅は、当該信号線の幅よりも大きく、前記走査線に重なる金属層の幅は、当該走査線の幅よりも大きい、請求項２に記載の表示装置。 3. The method according to claim 2, wherein, in plan view, the width of the metal layer overlapping with the signal line is larger than the width of the signal line, and the width of the metal layer overlapping with the scanning line is larger than the width of the scanning line. display device. 前記アレイ基板は、画素毎に配置された複数の第１透光性電極を有し、
前記対向基板は、前記第１透光性電極と重畳する位置に第２透光性電極を有し、
前記アレイ基板は、前記画素において、平面視で前記第１透光性電極に、無機絶縁層を介して少なくとも一部が重なる第３透光性電極をさらに備え、前記金属層が前記第３透光性電極に積層されている請求項１から３のいずれか１項に記載の表示装置。 The array substrate has a plurality of first translucent electrodes arranged for each pixel,
The counter substrate has a second translucent electrode at a position overlapping with the first translucent electrode,
In the pixel, the array substrate further includes a third translucent electrode at least partially overlapping the first translucent electrode with an inorganic insulating layer interposed therebetween in a plan view, and the metal layer is the third translucent electrode. 4. A display device according to any one of claims 1 to 3, laminated on the photosensitive electrode. 前記遮光構造体は、前記走査線と同じ導電材料、又は前記信号線と同じ導電材料を含む、請求項１に記載の表示装置。 2. The display device of claim 1, wherein the light shielding structure comprises the same conductive material as the scanning lines or the same conductive material as the signal lines . 前記遮光構造体は、前記走査線と同じ導電材料、及び前記信号線と同じ導電材料が積層されている請求項１に記載の表示装置。 2. The display device according to claim 1 , wherein the light shielding structure is laminated with the same conductive material as the scanning lines and the same conductive material as the signal lines. 前記第１方向に隣り合う２つの画素の間には、２つの前記信号線が配置され、前記遮光構造体が前記信号線の延長線上に設けられている請求項５又は６に記載の表示装置。 7. The display device according to claim 5, wherein the two signal lines are arranged between two pixels adjacent to each other in the first direction, and the light blocking structure is provided on an extension line of the signal lines. . 前記遮光構造体は、前記有機絶縁層及び前記金属層で覆われている、請求項５から７のいずれか１項に記載の表示装置。 8. The display device according to any one of claims 5 to 7, wherein said light shielding structure is covered with said organic insulating layer and said metal layer. 前記光源が入射する光の入射方向と交差する方向における前記スイッチング素子の半導体層の長さが、前記入射方向における前記スイッチング素子の半導体層の長さよりも小さい、請求項１から８のいずれか１項に記載の表示装置。 9. Any one of claims 1 to 8, wherein a length of the semiconductor layer of the switching element in a direction intersecting with an incident direction of light incident from the light source is smaller than a length of the semiconductor layer of the switching element in the incident direction. The display device according to the item. 前記液晶層は、高分子分散型液晶であり、
前記アレイ基板から前記対向基板の背景が視認され、前記対向基板から前記アレイ基板の背景が視認される、請求項１から９のいずれか１項に記載の表示装置。 The liquid crystal layer is a polymer dispersed liquid crystal,
10. The display device according to claim 1, wherein the background of said counter substrate is visible from said array substrate, and the background of said array substrate is visible from said counter substrate.
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