JP7236464B2 - 積層シート及びその使用方法 - Google Patents
積層シート及びその使用方法 Download PDFInfo
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- JP7236464B2 JP7236464B2 JP2020561146A JP2020561146A JP7236464B2 JP 7236464 B2 JP7236464 B2 JP 7236464B2 JP 2020561146 A JP2020561146 A JP 2020561146A JP 2020561146 A JP2020561146 A JP 2020561146A JP 7236464 B2 JP7236464 B2 JP 7236464B2
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Images
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
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- H05K1/00—Printed circuits
- H05K1/16—Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor
- H05K1/162—Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor incorporating printed capacitors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L22/10—Measuring as part of the manufacturing process
- H01L22/14—Measuring as part of the manufacturing process for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B32—LAYERED PRODUCTS
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- B32B15/04—Layered products comprising a layer of metal comprising metal as the main or only constituent of a layer, which is next to another layer of the same or of a different material
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- B32B7/00—Layered products characterised by the relation between layers; Layered products characterised by the relative orientation of features between layers, or by the relative values of a measurable parameter between layers, i.e. products comprising layers having different physical, chemical or physicochemical properties; Layered products characterised by the interconnection of layers
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- G01R31/12—Testing dielectric strength or breakdown voltage ; Testing or monitoring effectiveness or level of insulation, e.g. of a cable or of an apparatus, for example using partial discharge measurements; Electrostatic testing
- G01R31/1227—Testing dielectric strength or breakdown voltage ; Testing or monitoring effectiveness or level of insulation, e.g. of a cable or of an apparatus, for example using partial discharge measurements; Electrostatic testing of components, parts or materials
- G01R31/1263—Testing dielectric strength or breakdown voltage ; Testing or monitoring effectiveness or level of insulation, e.g. of a cable or of an apparatus, for example using partial discharge measurements; Electrostatic testing of components, parts or materials of solid or fluid materials, e.g. insulation films, bulk material; of semiconductors or LV electronic components or parts; of cable, line or wire insulation
- G01R31/129—Testing dielectric strength or breakdown voltage ; Testing or monitoring effectiveness or level of insulation, e.g. of a cable or of an apparatus, for example using partial discharge measurements; Electrostatic testing of components, parts or materials of solid or fluid materials, e.g. insulation films, bulk material; of semiconductors or LV electronic components or parts; of cable, line or wire insulation of components or parts made of semiconducting materials; of LV components or parts
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
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- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
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- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
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- H01—ELECTRIC ELEMENTS
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- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68359—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during manufacture of interconnect decals or build up layers
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Description
剥離機能付キャリアと、
前記剥離機能付キャリア上に設けられる第1導電膜と、
前記第1導電膜上に設けられる絶縁膜と、
前記絶縁膜上に設けられる第2導電膜と、
を備えた積層シートであって、
前記第2導電膜が再配線層の形成に用いられ、かつ、前記第1導電膜、前記絶縁膜及び前記第2導電膜が前記再配線層の電気検査を行うためのキャパシタとして機能する、積層シートが提供される。
前記積層シートの前記第2導電膜を加工して再配線層を形成する、又は前記第2導電膜上に再配線層を形成する工程と、
前記再配線層に対して電気検査を行う工程と、
を含み、前記電気検査が、前記再配線層と前記第1導電膜との間に電圧を加えて、前記第1導電膜、前記絶縁膜及び前記第2導電膜をキャパシタとして機能させ、電気特性(主としてインピーダンス又は静電容量)を測定することにより行われる、積層シートの使用方法が提供される。
本発明の積層シートが図1に模式的に示される。図1に示されるように、本発明の積層シート10は、剥離機能付キャリア12と、第1導電膜14と、絶縁膜16と、第2導電膜18とをこの順に備えたものである。第1導電膜14は、剥離機能付キャリア12上に設けられる。絶縁膜16は、第1導電膜14上に設けられる。第2導電膜18は絶縁膜16上に設けられ、再配線層20の形成に用いられる。そして、第1導電膜14、絶縁膜16及び第2導電膜18が再配線層20の電気検査を行うためのキャパシタとして機能する。所望により、積層シート10は、剥離機能付キャリア12と第1導電膜14との間に機能層13を有していてもよい。上述の各種層はそれぞれ単層であってもよいし、複数の層からなるものであってもよい。また、剥離機能付キャリア12の両面に上下対称となるように上述の各種層を順に備えてなる構成としてもよい。このように、剥離機能付キャリア12上に第1導電膜14及び第2導電膜18間に絶縁膜16が介在する層構成を設けることで、再配線層20の形成に有用な積層シートの形態でありながら、第1導電膜14、絶縁膜16及び第2導電膜18がキャパシタとして機能し、それにより、第2導電膜18を用いて形成された再配線層20の電気検査を効率良く行うことが可能となる。
本発明による積層シート10は、上述したキャリア12aを用意し、キャリア12a上に、所望により中間層(例えば第1中間層及び第2中間層)、所望により剥離機能膜12b、所望により機能層13、第1導電膜14、絶縁膜16、及び第2導電膜18を形成することにより製造することができる。中間層(存在する場合)、剥離機能膜12b(存在する場合)、機能層13(存在する場合)、第1導電膜14及び第2導電膜18の各層の形成は、極薄化によるファインピッチ化に対応しやすい観点から、物理気相堆積(PVD)法により行われるのが好ましい。物理気相堆積(PVD)法の例としては、スパッタリング法、真空蒸着法、及びイオンプレーティング法が挙げられるが、0.05nmから5000nmまでといった幅広い範囲で膜厚制御できる点、広い幅ないし面積にわたって膜厚均一性を確保できる点等から、最も好ましくはスパッタリング法である。物理気相堆積(PVD)法による成膜は公知の気相成膜装置を用いて公知の条件に従って行えばよく特に限定されない。例えば、スパッタリング法を採用する場合、スパッタリング方式は、マグネトロンスパッタリング、2極スパッタリング法、対向ターゲットスパッタリング法等、公知の種々の方法であってよいが、マグネトロンスパッタリングが、成膜速度が速く生産性が高い点で好ましい。スパッタリングはDC(直流)及びRF(高周波)のいずれの電源で行ってもよい。また、ターゲット形状も広く知られているプレート型ターゲットを使用することができるが、ターゲット使用効率の観点から円筒形ターゲットを用いることが望ましい。一方、絶縁膜16の形成は、化学気相堆積(CVD)法、スパッタリング法、蒸着法、スリットコーター法、スピンコーター法、スプレー法、又はそれらの組合せにより行うのが好ましい。この点、中間層(存在する場合)、剥離機能膜12b(存在する場合)、機能層13(存在する場合)、第1導電膜14、絶縁膜16及び第2導電膜18の全ての層をスパッタリング法により形成することで、製造効率が格段に高くなる。以下、中間層(存在する場合)、剥離機能膜12b(存在する場合)、機能層13(存在する場合)、第1導電膜14、及び第2導電膜18の各層の気相法(好ましくはスパッタリング法)による成膜、並びに絶縁膜16の上記方法による成膜について説明する。
本発明の積層シート10を用いて再配線層20を製造することができる。そして、第1導電膜14、絶縁膜16及び第2導電膜18がキャパシタとして機能することで、製造した再配線層20の電気検査を効率良く行うことができる。以下、本発明の積層シート10の好ましい使用方法について説明する。この積層シート10の使用方法は、(1)再配線層の形成工程と、(2)再配線層の電気検査工程とを含む。
本発明の積層シート10を用いて再配線層20を形成する。再配線層20の形成は、第2導電膜18を加工することにより行うことができる。この場合、第2導電膜18は再配線層20の一部に含まれる。あるいは、第2導電膜18自体には加工を施さず、第2導電膜18上に再配線層20’を形成してもよい。この点、例えば第2導電膜18上にさらなる金属層(例えば銅層)を積層して、当該金属層を加工することにより再配線層20’を形成することができる。この場合、第2導電膜18自体は再配線層20’を構成しないため、剥離機能付キャリア12を剥離した後に、フラッシュエッチング等により第2導電膜18を除去するのが好ましい。
第2導電膜18を用いて形成した再配線層20に対して、電気検査を行う。この電気検査は、図2に示されるように、再配線層20と第1導電膜14との間に電圧を加えて、第1導電膜14、絶縁膜16及び第2導電膜18をキャパシタとして機能させ、電気特性(主としてインピーダンス又は静電容量)を測定することにより行えばよい。より具体的には、例えば特許文献5に示されるような公知の手法に基づいて、二つ以上の異なる周波数の電力を用いて配線間のインピーダンスを測定し、算出された二つ以上のインピーダンスの周波数に応じた変位量によって当該配線間の絶縁状態の良否を判定することができる。また、第1導電膜14に電気検査用プローブを当接する等して電気特性(主としてインピーダンス又は静電容量)を測定する場合には、第1導電膜14を露出させるために、必要に応じて再配線層20から剥離機能付キャリア12を予め剥離除去してもよい。
Claims (17)
- 剥離機能付キャリアと、
前記剥離機能付キャリア上に設けられる第1導電膜と、
前記第1導電膜上に設けられる絶縁膜と、
前記絶縁膜上に設けられる第2導電膜と、
を備えた積層シートであって、
前記第2導電膜が再配線層の形成に用いられ、かつ、前記第1導電膜、前記絶縁膜及び前記第2導電膜が前記再配線層の電気検査を行うためのキャパシタとして機能する、積層シート。 - 前記剥離機能付キャリアが、キャリアと、前記キャリアの前記第1導電膜側に設けられ、前記第1導電膜から前記キャリアを剥離可能とする剥離機能膜とを備えた、請求項1に記載の積層シート。
- 前記第1導電膜が金属膜又は導電性ポリマー膜である、請求項1又は2に記載の積層シート。
- 前記第1導電膜が、Al、Ag、Cu、Ni、Ti、Ta、Fe、Co、Mo、Mg、Mn、Zn、Cr、In及びSnからなる群から選択される少なくとも1種の金属を含む金属膜である、請求項3に記載の積層シート。
- 前記第1導電膜が、ポリチオフェン系ポリマー、ポリアセチレン系ポリマー、ポリアニリン系ポリマー及びポリピロール系ポリマーからなる群から選択される少なくとも1種を含む導電性ポリマー膜である、請求項3に記載の積層シート。
- 前記第1導電膜の厚さが5nm以上1000nm以下である、請求項1~5のいずれか一項に記載の積層シート。
- 前記第2導電膜が前記再配線層を形成するためのシード層である、請求項1~6のいずれか一項に記載の積層シート。
- 前記第2導電膜が金属膜である、請求項1~7のいずれか一項に記載の積層シート。
- 前記第2導電膜が、Al、Ag、Cu、Ni、Ti、Ta、Fe、Co、Mo、Mg、Mn、Zn、Cr、In及びSnからなる群から選択される少なくとも1種の金属を含む金属膜である、請求項1~8のいずれか一項に記載の積層シート。
- 前記第2導電膜の厚さが10nm以上1000nm以下である、請求項1~9のいずれか一項に記載の積層シート。
- 前記絶縁膜の誘電率が周波数1MHzにおいて2以上である、請求項1~10のいずれか一項に記載の積層シート。
- 前記絶縁膜の厚さが0.1μm以上10μm以下である、請求項1~11のいずれか一項に記載の積層シート。
- 前記絶縁膜の耐電圧強度が1.0×104V/cm以上である、請求項1~12のいずれか一項に記載の積層シート。
- 前記絶縁膜が、酸化膜、窒化膜、炭化膜、フッ化膜、エポキシ樹脂膜、ポリイミド樹脂膜、エチレン樹脂膜、フェノール樹脂膜、PPT樹脂膜、ABS樹脂膜、ナイロン樹脂膜及びPBT樹脂膜からなる群から選択される少なくとも1種である、請求項1~13のいずれか一項に記載の積層シート。
- 前記第1導電膜及び前記第2導電膜の各々が、Al、Ag、Cu、Ni、Ti、Ta、Fe、Co、Mo、Mg、Mn、Zn、Cr、In及びSnからなる群から選択される少なくとも1種の金属であり、かつ、前記絶縁膜が酸化膜、窒化膜、エポキシ樹脂膜及びポリイミド樹脂膜からなる群から選択される少なくとも1種である、請求項1~14のいずれか一項に記載の積層シート。
- 請求項1~15のいずれか一項に記載の積層シートの前記第2導電膜を加工して再配線層を形成する、又は前記第2導電膜上に再配線層を形成する工程と、
前記再配線層に対して電気検査を行う工程と、
を含み、前記電気検査が、前記再配線層と前記第1導電膜との間に電圧を加えて、前記第1導電膜、前記絶縁膜及び前記第2導電膜をキャパシタとして機能させ、電気特性を測定することにより行われる、積層シートの使用方法。 - 請求項16に記載の工程を含む、半導体パッケージの製造方法。
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