JP7210179B2 - 半導体装置および半導体装置の製造方法 - Google Patents
半導体装置および半導体装置の製造方法 Download PDFInfo
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Description
酸化物半導体を有する薄膜トランジスタを備え、前記酸化物半導体は、チャネル領域と、ドレイン領域と、ソース領域と、を有し、前記チャネル領域の上に設けられたゲート絶縁膜と、前記ゲート絶縁膜の上に設けられたアルミニウム酸化膜と、前記アルミニウム酸化膜の上に設けられたゲート電極と、を有し、前記アルミニウム酸化膜は、平面視において、前記ドレイン領域および前記ソース領域のいずれに対しても覆わない領域を有する半導体装置が提供される。
基板と、前記基板の上に設けられ、多結晶シリコンで構成された第1薄膜トランジスタと、前記基板の上に設けられ、酸化物半導体で構成された第2薄膜トランジスタと、を含み、前記酸化物半導体は、チャネル領域と、ドレイン領域と、ソース領域と、を有し、前記チャネル領域の上に設けられたゲート絶縁膜と、前記ゲート絶縁膜の上に設けられたアルミニウム酸化膜と、前記アルミニウム酸化膜の上に設けられたゲート電極と、を含む、半導体装置が提供される。
チャネル領域とドレイン領域とソース領域とを有する酸化物半導体の半導体層で構成された薄膜トランジスタを含む半導体装置の製造方法であって、基板の上に、前記半導体層を形成する工程と、前記半導体層を覆う様に、ゲート絶縁膜を形成する工程と、前記ゲート絶縁膜の上に、前記半導体層の前記チャネル領域の上方に開口部を有するブロック層を形成する工程と、前記ブロック層の上、および、前記開口部から露出する前記ゲート絶縁膜の上に、アルミニウム酸化膜を形成するとともに、前記開口部から前記半導体層の前記チャネル領域へ酸素を供給する工程と、を含む、半導体装置の製造方法が提供される。
図1は、本発明が適用される表示装置の平面図である。図2は、図1のA-A線に沿う断面図である。
図3は、画素PXの基本構成及び表示装置DSPの等価回路を示す図である。複数の画素PX第1方向X及び第2方向Yにマトリクス状に配置されている。複数本の走査線G(G1、G2・・・)は、走査線駆動回路GDに接続されている。複数本の信号線S(S1、S2・・・)は、信号線駆動回路SDに接続されている。複数本の共通電極CE(CE1、CE2・・・)は、コモン電圧(Vcom)の電圧供給部CDに接続され、複数の画素PXに亘って配置されている。1つの画素PXは、1本の走査線と、1本の信号線と、1本の共通電極CEと、に接続されている。なお、走査線G及び信号線Sは、必ずしも直線的に延出していなくてもよく、それらの一部が屈曲していてもよい。例えば、信号線Sは、その一部が屈曲していたとしても、第2方向Yに延出しているものとする。走査線駆動回路GD、信号線駆動回路SD、および、電圧供給部CDは、薄膜トランジスタ(TFT)によって構成される。
図4は、実施形態に係る半導体装置の構成を示す断面図である。図4に示す半導体装置10は、複数の薄膜トランジスタTFT1、TFT2を備えた第1基板である。図4において、左側の薄膜トランジスタ(第1薄膜トランジスタ)TFT1はLTPSを用いた薄膜トランジスタ(LTPSTFTともいう)であり、右側の薄膜トランジスタ(第2薄膜トランジスタ)TFT2は酸化物半導体(OS)を用いた薄膜トランジスタ(OSTFTともいう)である。半導体装置10は、表示パネルに内蔵される半導体装置である。
図5から図16を用いて、図4で説明された半導体装置10を実現する各製造工程を説明する。
上記実施態様では、LTPSTFTとOSTFTとを有する表示装置等の半導体装置10について説明した。以下の変形例では、OSTFTのみを有する表示装置等の半導体装置10aについて説明する。この場合、図4に示されるOSTFTの構成において、ドレイン領域1092およびソース領域1093に接続された保護用の金属層111が削除可能である。したがって、金属層111の成膜およびパターニング工程、および、コンタクトホールの洗浄工程が削除できるので、製造工程を短縮化することができる。
Claims (12)
- 酸化物半導体を有する薄膜トランジスタを備え、
前記酸化物半導体は、チャネル領域と、ドレイン領域と、ソース領域と、を有し、
前記チャネル領域の上に設けられたゲート絶縁膜と、
前記ゲート絶縁膜の上に設けられたアルミニウム酸化膜と、
前記アルミニウム酸化膜の上に設けられたゲート電極と、を有し、
前記アルミニウム酸化膜は、平面視において、前記ドレイン領域および前記ソース領域のいずれに対しても覆わない領域を有し、
前記チャネル領域は、前記ドレイン領域または前記ソース領域と比較して、酸素を多く含み、
前記チャネル領域の前記酸素は、前記アルミニウム酸化膜の成膜時に、前記チャネル領域に導入され、
前記アルミニウム酸化膜の両端に設けられたブロック層を有し、
前記ブロック層は、前記チャネル領域の上に位置する、半導体装置。 - 請求項1において、
前記酸化物半導体は、IGZOである、半導体装置。 - 請求項1において、
前記半導体装置は、画素を含む表示領域を有する表示パネルに内蔵される半導体装置であり、
前記薄膜トランジスタは、前記画素に設けられたスイッチング素子を構成する、半導体装置。 - 基板と、
前記基板の上に設けられ、多結晶シリコンを有する第1薄膜トランジスタと、
前記基板の上に設けられ、酸化物半導体を有する第2薄膜トランジスタと、を含み、
前記酸化物半導体は、チャネル領域と、ドレイン領域と、ソース領域と、を有し、
前記チャネル領域の上に設けられたゲート絶縁膜と、
前記ゲート絶縁膜の上に設けられたアルミニウム酸化膜と、
前記アルミニウム酸化膜の上に設けられたゲート電極と、を含み、
前記アルミニウム酸化膜の両端に設けられたブロック層を有し、
前記ブロック層は、前記チャネル領域の上に位置する、半導体装置。 - 請求項4において、
前記チャネル領域は、前記ドレイン領域または前記ソース領域と比較して、酸素を多く含み、
前記チャネル領域の前記酸素は、前記アルミニウム酸化膜の成膜時に、前記チャネル領域に導入される、半導体装置。 - 請求項4において、
前記酸化物半導体は、IGZOである、半導体装置。 - 請求項4において、
前記第2薄膜トランジスタは、前記第1薄膜トランジスタよりも、上方に位置する、半導体装置。 - 請求項7において、
前記チャネル領域は、前記ドレイン領域と前記ソース領域との間に位置し、
前記チャネル領域に接していない前記ドレイン領域の端部、および、前記チャネル領域に接し前記ソース領域の端部に接続された金属層を有する、半導体装置。 - 請求項8において、
前記半導体装置は、画素を含む表示領域と前記表示領域の外周に位置する非表示領域とを有する表示パネルに内蔵される半導体装置であり、
前記第1薄膜トランジスタは、前記非表示領域に設けられ、前記画素を制御する駆動回路を構成し、
前記第2薄膜トランジスタは、前記画素に設けられたスイッチング素子を構成する、半導体装置。 - チャネル領域とドレイン領域とソース領域とを有する酸化物半導体の半導体層を有する薄膜トランジスタを含む半導体装置の製造方法であって、
基板の上に、前記半導体層を形成する工程と、
前記半導体層を覆う様に、ゲート絶縁膜を形成する工程と、
前記ゲート絶縁膜の上に、前記半導体層の前記チャネル領域の上方に開口部を有するブロック層を形成する工程と、
前記ブロック層の上、および、前記開口部から露出する前記ゲート絶縁膜の上に、アルミニウム酸化膜を形成するとともに、前記開口部から前記半導体層の前記チャネル領域へ酸素を供給する工程と、を含む、半導体装置の製造方法。 - 請求項10において、さらに、
前記アルミニウム酸化膜の上に、ゲート電極を形成する工程と、
前記半導体層の前記チャネル領域の上側を覆う様に、前記ゲート電極、前記アルミニウム酸化膜および前記ブロック層を選択的にパターニングする工程と、含み、
前記パターニングする工程は、前記アルミニウム酸化膜の両側に、前記ブロック層が残るようにパターニングする、半導体装置の製造方法。 - 請求項11において、さらに、
選択的にパターニングされた前記ゲート電極をマスクとしてイオンインプランテーションを行い、前記半導体層の前記ドレイン領域および前記ソース領域に導電性を付与する工程と、
選択的にパターニングされた前記ゲート電極、前記アルミニウム酸化膜および前記ブロック層を覆う様に、絶縁膜を形成する工程と、
前記ドレイン領域と前記ソース領域が露出するように、前記絶縁膜および前記ゲート絶縁膜にコンタクトホールを形成する工程と、
前記コンタクトホールに配線を形成する工程と、を含む、半導体装置の製造方法。
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