JP7208421B2 - 改善された降伏電圧能力を有する集積チップ及びその製造方法 - Google Patents
改善された降伏電圧能力を有する集積チップ及びその製造方法 Download PDFInfo
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- JP7208421B2 JP7208421B2 JP2022002280A JP2022002280A JP7208421B2 JP 7208421 B2 JP7208421 B2 JP 7208421B2 JP 2022002280 A JP2022002280 A JP 2022002280A JP 2022002280 A JP2022002280 A JP 2022002280A JP 7208421 B2 JP7208421 B2 JP 7208421B2
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Description
102:半導体基板
104:ハンドル基板
106:絶縁体層
108:素子基板
110:第1の隔離構造
110a:第1の隔離セグメント
110b:第2の隔離セグメント
112:第2の隔離構造
113:第1の接触面
114:導電ビア
115:第2の接触面
116:第1のウェル領域
118:第2のウェル領域
120:第3のウェル領域
121:導電終端構造
122:高電圧トランジスタ
124:本体コンタクト領域
126:ソース領域
128:ゲート誘電層
130:ゲート電極
130s1:側壁
132:ドレイン領域
133:周辺ゲート誘電層
134:導電ゲート電極
134s1:第1の側壁
134s2:第2の側壁
136:コンタクト領域
140:誘電構造
142:導電コンタクト
144:導電配線
202:低濃度ドープ領域
400a、400b:グラフ
402:第1の電圧値
404:第2の電圧値
406:第3の電圧値
408:第4の電圧値
410、412:電圧曲線
500a、600a、700a、800a、900a、1000a、1100a:断面図
500b、600b、700b、800b、900b、1000b、1100b:上面図
902:ゲート構造
904:終端ゲート構造
1200:方法
1202、1204、1206、1208、1210、1212:工程
L1、L2、L3:横方向距離
V1:第1の電圧
V2:第2の電圧
w1:第1の幅
w2:第2の幅
Claims (10)
- 集積チップであって、
ハンドル基板上に設けられた素子基板と、前記素子基板及び前記ハンドル基板の間に配置された絶縁体層と、を備えた半導体基板と、
ドレイン領域及びソース領域の間で、前記素子基板上に設けられたゲート電極と、
前記素子基板及び前記絶縁体層を通じて延設され、前記ハンドル基板に接触する導電ビアと、
前記素子基板内に配置され、横方向で前記ゲート電極及び前記導電ビアの間に配置された第1の隔離セグメントを備える第1の隔離構造と、
前記素子基板内で、前記第1の隔離セグメント及び前記導電ビアの間に配置されたコンタクト領域と、
前記第1の隔離セグメントの直上に設けられ、前記コンタクト領域に電気的に連結する導電ゲート電極と、を備える集積チップ。 - 前記素子基板内に配置された第1のウェル領域と、
前記素子基板内に配置され、第1の接触面にて、前記第1のウェル領域と隣接する第2のウェル領域であって、前記第2のウェル領域は、第1の導電型を有し、前記第1のウェル領域は、前記第1の導電型とは反対の第2の導電型を有し、前記ゲート電極は、前記第1の接触面の直上に設けられる前記第2のウェル領域と、
前記素子基板内に配置され、第2の接触面にて、前記第2のウェル領域と隣接する第3のウェル領域であって、前記第3のウェル領域は、前記第2の導電型を有し、前記導電ゲート電極は、前記第2の接触面の直上に設けられる前記第3のウェル領域と、をさらに備える請求項1に記載の集積チップ。 - 前記ドレイン領域は、前記第2のウェル領域内に配置され、前記ソース領域は、前記第1のウェル領域内に配置され、前記コンタクト領域は、前記第3のウェル領域内に配置されることで、前記導電ゲート電極が、前記コンタクト領域により、前記第3のウェル領域に電気的に連結されるようにする請求項2に記載の集積チップ。
- 前記第1の隔離セグメントは、前記コンタクト領域の側壁から前記ドレイン領域の側壁まで、連続的に延設され、前記導電ゲート電極は、横方向で前記第1の隔離セグメントの対向する外側壁の間に離間する請求項1に記載の集積チップ。
- 前記素子基板上に設けられる相互接続構造をさらに備え、前記相互接続構造は、誘電構造内に配置された複数の導電コンタクト及び複数の導電配線を備え、前記導電ゲート電極は、前記導電コンタクト及び前記導電配線により、前記コンタクト領域に連結される請求項1に記載の集積チップ。
- 集積チップであって、
絶縁体層の上に設けられた素子基板と、前記絶縁体層の下に設けられたハンドル基板と、
前記素子基板内に配置された第1のウェル領域、第2のウェル領域、及び第3のウェル領域であって、前記第2のウェル領域は、横方向で前記第1及び第3のウェル領域の間に離間している前記第1のウェル領域、前記第2のウェル領域、及び前記第3のウェル領域と、
前記素子基板上に配置され、ゲート電極、ソース領域、及びドレイン領域を備える高電圧トランジスタであって、前記ゲート電極は、前記ソース領域及び前記ドレイン領域の間に配置され、前記ゲート電極は、前記第1のウェル領域及び前記第2のウェル領域の間の第1の接触面の直上に配置される前記高電圧トランジスタと、
前記素子基板内に配置され、前記ハンドル基板に電気的に連結される導電ビアであって、前記導電ビアは、前記第3のウェル領域と隣接する前記導電ビアと、
前記素子基板上で、前記導電ビア及び前記高電圧トランジスタの間に配置される導電終端構造であって、前記導電終端構造は、前記第3のウェル領域内に配置されるコンタクト領域と、前記第2のウェル領域及び前記第3のウェル領域の間の第2の接触面の上に設けられる導電ゲート電極とを備え、前記導電ゲート電極は、前記コンタクト領域により、前記第3のウェル領域に電気的に連結される前記導電終端構造と、を備える集積チップ。 - 前記素子基板内に配置された第1の隔離構造をさらに備え、前記第1の隔離構造は、第2の隔離セグメントから横方向にオフセットした第1の隔離セグメントを備え、前記第1の隔離セグメントは、前記素子基板から前記導電ゲート電極を離間し、前記ゲート電極は、前記第2の隔離セグメントの少なくとも一部の直上に設けられる請求項6に記載の集積チップ。
- 前記コンタクト領域は、前記第1の隔離セグメントの外側壁に隣接し、前記導電ゲート電極の対向する外側壁は、前記高電圧トランジスタに向かう方向において、前記第1の隔離セグメントの外側壁から横方向にオフセットする請求項7に記載の集積チップ。
- 集積チップを製造する方法であって、
素子基板内に第1の隔離構造を形成する工程であって、前記素子基板は、ハンドル基板の上に設けられた絶縁体層の上に設けられる工程と、
前記素子基板を通じて、前記ハンドル基板まで延設された導電ビアを形成する工程と、
前記素子基板をドープして、前記素子基板内に第1のウェル領域、第2のウェル領域、及び第3のウェル領域を形成する工程であって、前記第2のウェル領域は、横方向で前記第1及び第3のウェル領域の間に離間する工程と、
前記素子基板上方にゲート電極を形成する工程であって、前記ゲート電極は、前記第1のウェル領域及び前記第2のウェル領域の間の第1の接触面の上に設けられる工程と、
前記第1の隔離構造上方に導電ゲート電極を形成する工程と、
前記素子基板をドープして、前記素子基板内にソース領域、ドレイン領域、及びコンタクト領域を形成する工程であって、前記ゲート電極は、前記ソース領域及び前記ドレイン領域の間に配置され、前記コンタクト領域は、前記第3のウェル領域内において、前記導電ビア及び前記導電ゲート電極の間に配置される工程、とを備える方法。 - 前記素子基板上方に相互接続構造を形成し、誘電構造内に配置された複数の導電コンタクト及び複数の導電配線を備える工程であって、前記導電ゲート電極は、前記相互接続構造により、前記コンタクト領域に電気的に接続される工程をさらに備える請求項9に記載の方法。
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