JP7186645B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP7186645B2 JP7186645B2 JP2019053441A JP2019053441A JP7186645B2 JP 7186645 B2 JP7186645 B2 JP 7186645B2 JP 2019053441 A JP2019053441 A JP 2019053441A JP 2019053441 A JP2019053441 A JP 2019053441A JP 7186645 B2 JP7186645 B2 JP 7186645B2
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/0601—Structure
- H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
- H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
- H01L2224/401—Disposition
- H01L2224/40151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/40221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/40245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
- H01L2224/41—Structure, shape, material or disposition of the strap connectors after the connecting process of a plurality of strap connectors
- H01L2224/4101—Structure
- H01L2224/4103—Connectors having different sizes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Description
図4には、半導体チップ20からソース端子30A、30Bおよび30Cに至る電流経路IA、IBおよびICを示している。
コネクタ90は、第1部分90aと、第2部分90bと、第3部分90cと、を有する。第1部分90aは、ソース電極23に電気的に接続される。第2部分90bは、複数のソース端子30のそれぞれのマウントベース10側の端、もしくは、その近傍に接続される。
Claims (5)
- マウントベースと、
前記マウントベース上に配置された半導体チップであって、半導体部と、前記半導体部の裏面上に設けられ、前記マウントベースと前記半導体部との間に位置する第1電極と、前記半導体部の表面上に設けられた第2電極と、を有する半導体チップと、
前記第2電極に電気的に接続されたコネクタと、
前記コネクタを介して前記半導体チップの前記第2電極に電気的に接続された複数の端子と、
を備え、
前記複数の端子は、前記マウントベースの前記半導体チップが配置された表面の外縁に沿った第1方向に並び、
前記複数の端子は、前記マウントベースの前記表面に沿った第2方向であって、前記第1方向と交差する第2方向に延伸し、
前記複数の端子は、前記第2方向において、前記半導体チップと並ぶ第1端子と、前記第2方向において、前記半導体チップとは並ばない第2端子と、を含み、
前記コネクタは、前記半導体チップの前記第2電極に接続された第1部分と、前記複数の端子のそれぞれの前記マウントベース側の端に接続された第2部分と、前記第1部分と前記第2部分との間に位置し、前記第1部分と前記第2部分とをつなぐ接続部と、を含み、
前記コネクタを前記マウントベースの前記表面に垂直な方向に見た時、前記接続部は、前記半導体チップと前記第1端子との間には設けられない半導体装置。 - 前記複数の端子と共に、前記第1方向に並んだ別の端子と、
前記別の端子に接続された第2のコネクタと、
をさらに備え、
前記半導体チップは、前記第2電極と共に前記表面上に設けられた制御パッドをさらに有し、
前記第2のコネクタは、前記制御パッドと前記別の端子とを電気的に接続する請求項1記載の半導体装置。
- 前記第1端子は、前記第1方向の並びの一方の端に位置し、前記別の端子に隣接し、
前記第2端子は、前記第1方向の並びの他方の端に位置し、
前記別の端子と前記第2端子との間の間隔は、前記半導体チップの前記第1方向の長さよりも広い請求項2記載の半導体装置。 - 前記第2電極における前記複数の端子側の外縁の前記第1方向の長さは、前記第1端子と前記第2端子との間の間隔よりも狭い請求項3記載の半導体装置。
- 前記コネクタを前記マウントベースの前記表面に垂直な方向に見た時、前記コネクタは、前記第2部分の前記第2端子に接続される端から前記第1部分の前記半導体チップの外縁に近接した角まで直線状に延びる辺を有する形状に設けられる請求項3または4に記載の半導体装置。
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Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2009124082A (ja) | 2007-11-19 | 2009-06-04 | Mitsubishi Electric Corp | 電力用半導体装置 |
JP2009188329A (ja) | 2008-02-08 | 2009-08-20 | Fuchigami Micro:Kk | ヒートシンク、冷却モジュールおよび冷却可能な電子基板 |
JP2012079733A (ja) | 2010-09-30 | 2012-04-19 | Sharp Corp | 電子部品回路基板 |
US20160233150A1 (en) | 2015-02-05 | 2016-08-11 | Kabushiki Kaisha Toshiba | Semiconductor device |
JP2016146457A (ja) | 2015-02-02 | 2016-08-12 | 株式会社東芝 | 半導体装置およびその製造方法 |
JP2016149516A (ja) | 2015-02-05 | 2016-08-18 | 株式会社東芝 | 半導体装置 |
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- 2019-03-20 JP JP2019053441A patent/JP7186645B2/ja active Active
Patent Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2009124082A (ja) | 2007-11-19 | 2009-06-04 | Mitsubishi Electric Corp | 電力用半導体装置 |
JP2009188329A (ja) | 2008-02-08 | 2009-08-20 | Fuchigami Micro:Kk | ヒートシンク、冷却モジュールおよび冷却可能な電子基板 |
CN102017134A (zh) | 2008-02-08 | 2011-04-13 | 株式会社渊上微 | 热沉、冷却模块和可冷却电子板 |
US20110214904A1 (en) | 2008-02-08 | 2011-09-08 | Fuchigami Micro Co., Ltd | Heat Sink, Cooling Module And Coolable Electronic Board |
JP2012079733A (ja) | 2010-09-30 | 2012-04-19 | Sharp Corp | 電子部品回路基板 |
JP2016146457A (ja) | 2015-02-02 | 2016-08-12 | 株式会社東芝 | 半導体装置およびその製造方法 |
US20160233150A1 (en) | 2015-02-05 | 2016-08-11 | Kabushiki Kaisha Toshiba | Semiconductor device |
JP2016149516A (ja) | 2015-02-05 | 2016-08-18 | 株式会社東芝 | 半導体装置 |
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