JP7112160B2 - 高性能スーパーβ(SBNPN) - Google Patents
高性能スーパーβ(SBNPN) Download PDFInfo
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- JP7112160B2 JP7112160B2 JP2019513835A JP2019513835A JP7112160B2 JP 7112160 B2 JP7112160 B2 JP 7112160B2 JP 2019513835 A JP2019513835 A JP 2019513835A JP 2019513835 A JP2019513835 A JP 2019513835A JP 7112160 B2 JP7112160 B2 JP 7112160B2
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- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 claims description 90
- 238000000034 method Methods 0.000 claims description 58
- 150000004767 nitrides Chemical class 0.000 claims description 38
- 229920002120 photoresistant polymer Polymers 0.000 claims description 35
- 238000000151 deposition Methods 0.000 claims description 30
- 239000007943 implant Substances 0.000 claims description 12
- 150000002500 ions Chemical class 0.000 claims description 9
- 238000005530 etching Methods 0.000 claims description 8
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 8
- 229920005591 polysilicon Polymers 0.000 claims description 8
- 102000004129 N-Type Calcium Channels Human genes 0.000 claims description 5
- 108090000699 N-Type Calcium Channels Proteins 0.000 claims description 5
- 230000008021 deposition Effects 0.000 claims description 4
- 229910052785 arsenic Inorganic materials 0.000 claims description 3
- 238000002955 isolation Methods 0.000 claims description 2
- 238000000059 patterning Methods 0.000 claims 4
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 claims 2
- 238000004519 manufacturing process Methods 0.000 description 5
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 3
- QAOWNCQODCNURD-UHFFFAOYSA-N Sulfuric acid Chemical compound OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 description 2
- 238000004380 ashing Methods 0.000 description 2
- 235000011149 sulphuric acid Nutrition 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- -1 arsenic ions Chemical class 0.000 description 1
- 239000010408 film Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- QPJSUIGXIBEQAC-UHFFFAOYSA-N n-(2,4-dichloro-5-propan-2-yloxyphenyl)acetamide Chemical compound CC(C)OC1=CC(NC(C)=O)=C(Cl)C=C1Cl QPJSUIGXIBEQAC-UHFFFAOYSA-N 0.000 description 1
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
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- H01L29/0642—Isolation within the component, i.e. internal isolation
- H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
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- H01L29/70—Bipolar devices
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
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Description
Claims (28)
- 1000以上の共通エミッタ電流利得を有するスーパーβNPN(SBNPN)トランジスタをつくるための方法であって、
P型エピタキシャル層上にオルトケイ酸テトラエチル(TEOS)層を堆積することと、
前記TEOS層上に窒化物層を堆積することと、
前記窒化物層と前記TEOS層との一部を選択的にエッチングして除くことによって前記SBNPNトランジスタのエミッタ領域をパターニングすることと、
前記窒化物層の頂部上と、前記窒化物層と前記TEOS層との側部に沿って、前記P型エピタキシャル層の頂部上とに、第2のTEOS層を堆積することと、
前記SBNPNトランジスタのエミッタ領域を形成するために、前記第2のTEOS層を介して前記P型エピタキシャル層にN型イオンでインプラントすることと、
を含む、方法。 - 請求項1に記載の方法であって、
前記第2のTEOS層を堆積することが、前記エッチングに起因して生じる前記窒化物層と前記TEOS層との任意のアンダーカットを充填することを含む、方法。 - 請求項1に記載の方法であって、
前記第2のTEOS層を堆積することが、低温の低堆積レートプロセスを用いて前記第2のTEOS層を堆積することを含む、方法。 - 請求項1に記載の方法であって、
前記第2のTEOS層が、前記インプラントすることのためのスクリーン酸化物として機能する、方法。 - 請求項1に記載の方法であって、
前記第2のTEOS層を堆積する前に、前記SBNPNトランジスタのエミッタ領域内の前記TEOS層を取り除くことを更に含む、方法。 - 請求項1に記載の方法であって、
前記インプラントすることの前に、前記第2のTEOS層上にフォトレジストの層を堆積することを更に含む、方法。 - 請求項1に記載の方法であって、
前記P型エピタキシャル層を介してN型イオンで前記第2のTEOS層にインプラントすることが、ヒ素で前記P型エピタキシャル層にインプラントすることを含む、方法。 - 1000以上の共通エミッタ電流利得を有するスーパーβNPN(SBNPN)トランジスタをつくるための方法であって、
P型エピタキシャル層上にスクリーン酸化物層と第1のオルトケイ酸テトラエチル(TEOS)層と窒化物層と第1のフォトレジスト層とを堆積することと、
前記SBNPNトランジスタのエミッタ領域を露出させるために前記第1のフォトレジスト層をパターニングすることと、
前記SBNPNトランジスタのエミッタ領域における前記スクリーン酸化物層と前記第1のTEOS層と前記窒化物層とをエッチングして除くことと、
前記第1のフォトレジスト層を取り除くことと、
前記SBPNトランジスタのエミッタ領域における前記窒化物層の上と前記P型エピタキシャル層の上とに第2のTEOS層を堆積することと、
前記第2のTEOS層上に第2のフォトレジスト層を堆積することと、
前記SBNPNトランジスタのエミッタインプラント領域を露出させるために前記第2のフォトレジスト層をパターニングすることと、
前記SBNPNトランジスタのエミッタ領域を形成するために前記第2のTEOS層を介して前記P型エピタキシャル層をインプラントすることと、
を含む、方法。 - 請求項8に記載の方法であって、
前記第2のフォトレジスト層を取り除くことを更に含む、方法。 - 請求項9に記載の方法であって、
前記SBNPNトランジスタのエミッタ領域における前記第2のTEOS層をエッチングして除くことを更に含む、方法。 - 請求項10に記載の方法であって、
エミッタポリシリコン層を堆積することを更に含む、方法。 - 請求項8に記載の方法であって、
前記第2のTEOS層を堆積することが、前記エッチングに起因して生じる前記窒化物層と前記第1のTEOS層との任意のアンダーカットを充填することを含む、方法。 - 請求項8に記載の方法であって、
前記第2のTEOS層を堆積することが、低温の低堆積レートプロセスで前記第2のTEOS層を堆積することを含む、方法。 - 請求項8に記載の方法であって、
前記第2のTEOS層が、前記インプラントすることのためのスクリーン酸化物として機能する、方法。 - 1000以上の共通エミッタ電流利得を有するスーパーβNPN(SBNPN)トランジスタであって、
N型エピタキシャル層上に形成されるP型エピタキシャル層を含むベースと、
前記P型エピタキシャル層に結合されるN型エミッタ領域と、前記N型エミッタ領域に結合されるポリシリコン構造とを含むエミッタと、
前記N型エピタキシャル層を含むコレクタと、
を含む、SBNPNトランジスタ。 - 請求項15に記載のSBNPNトランジスタであって、
前記N型エミッタ領域が前記P型エピタキシャル層内にある、SBNPNトランジスタ。 - 請求項16に記載のSBNPNトランジスタであって、
前記ポリシリコン構造が前記N型エミッタ領域上に形成される、SBNPNトランジスタ。 - 請求項17に記載のSBNPNトランジスタであって、
前記コレクタが、前記N型エピタキシャル層に結合される水平N型チャネルを更に含む、SBNPNトランジスタ。 - 請求項18に記載のSBNPNトランジスタであって、
その上に前記水平N型チャネルが位置する埋め込み酸化物層を更に含む、SBNPNトランジスタ。 - 請求項19に記載のSBNPNトランジスタであって、
前記埋め込み酸化物層に結合されて前記N型エピタキシャル層と前記水平N型チャネルとを電気的に隔離する隔離トレンチを更に含む、SBNPNトランジスタ。 - 少なくとも1000の共通エミッタ電流利得を有するスーパーβNPN(SBNPN)トランジスタをつくるための方法であって、
P型エピタキシャル層上にオルトケイ酸テトラエチル(TEOS)層を堆積することと、
前記TEOS層上に窒化物層を堆積することと、
前記窒化物層と前記TEOS層との一部を選択的にエッチングして除くことによって前記SBNPNトランジスタのエミッタ領域をパターニングすることと、
前記窒化物層の頂部上と、前記窒化物層と前記TEOS層との側部に沿って、前記P型エピタキシャル層の頂部上とに、第2のTEOS層を堆積することと、
前記SBNPNトランジスタのエミッタ領域を形成するために前記第2のTEOS層を介してN型イオンで前記P型エピタキシャル層をインプラントすることと、
を含む、方法。 - 請求項21に記載の方法であって、
前記SBNPNトランジスタが、予測可能な共通エミッタ電流利得を有する、方法。 - 請求項21に記載の方法であって、
前記第2のTEOS層を堆積することが、前記窒化物層と前記TEOS層とのアンダーカット領域を埋めることを含む、方法。 - 請求項21に記載の方法であって、
前記第2のTEOS層を堆積することが、低温度の低堆積レートのプロセスで前記第2のTEOS層を堆積することを含む、方法。 - 請求項21に記載の方法であって、
前記第2のTEOS層が前記インプラントすることに対するスクリーンマスクとして機能する、方法。 - 請求項21に記載の方法であって、
前記第2のTEOS層を堆積する前に前記SBNPTトランジスタのエミッタ領域内の前記TEOS層を除去することを更に含む、方法。 - 請求項21に記載の方法であって、
前記インプラントすることの前に前記第2のTEOS層上にフォトレジスト層を堆積することを更に含む、方法。 - 請求項21に記載の方法であって、
前記第2のTEOS層を介してN型イオンで前記P型エピタキシャル層をインプラントすることが、砒素で前記P型エピタキシャル層をインプラントすることを含む、方法。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US15/261,024 | 2016-09-09 | ||
US15/261,024 US10032868B2 (en) | 2016-09-09 | 2016-09-09 | High performance super-beta NPN (SBNPN) |
PCT/US2017/050984 WO2018049339A1 (en) | 2016-09-09 | 2017-09-11 | High performance super-beta npn (sbnpn) |
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JP2019530226A JP2019530226A (ja) | 2019-10-17 |
JP2019530226A5 JP2019530226A5 (ja) | 2020-10-22 |
JP7112160B2 true JP7112160B2 (ja) | 2022-08-03 |
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Application Number | Title | Priority Date | Filing Date |
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JP2019513835A Active JP7112160B2 (ja) | 2016-09-09 | 2017-09-11 | 高性能スーパーβ(SBNPN) |
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US (1) | US10032868B2 (ja) |
EP (1) | EP3510631A4 (ja) |
JP (1) | JP7112160B2 (ja) |
KR (1) | KR102626910B1 (ja) |
CN (1) | CN109643654B (ja) |
WO (1) | WO2018049339A1 (ja) |
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US11205718B1 (en) | 2018-11-26 | 2021-12-21 | Texas Instruments Incorporated | High performance super-beta NPN (SBNPN) |
DE102020004051B4 (de) | 2020-07-06 | 2022-04-07 | Azur Space Solar Power Gmbh | Vertikaler hochsperrender III-V Bipolartransistor |
US20240275157A1 (en) * | 2023-02-13 | 2024-08-15 | Tower Manufacturing Corp. | Power cord lcdi and hotspot detector circuit |
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JP2000501234A (ja) | 1995-11-20 | 2000-02-02 | テレフオンアクチーボラゲツト エル エム エリクソン(パブル) | 半導体装置の製造に関する方法 |
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Family Cites Families (27)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5437478A (en) * | 1977-08-29 | 1979-03-19 | Hitachi Ltd | Semiconductor device |
EP0347550A3 (en) | 1988-06-21 | 1991-08-28 | Texas Instruments Incorporated | Process for fabricating isolated vertical and super beta bipolar transistors |
GB2236901A (en) * | 1989-09-20 | 1991-04-17 | Philips Nv | A method of manufacturing a semiconductor device |
US5117271A (en) * | 1990-12-07 | 1992-05-26 | International Business Machines Corporation | Low capacitance bipolar junction transistor and fabrication process therfor |
US5481129A (en) | 1991-10-30 | 1996-01-02 | Harris Corporation | Analog-to-digital converter |
JP2684942B2 (ja) * | 1992-11-30 | 1997-12-03 | 日本電気株式会社 | 化学気相成長法と化学気相成長装置および多層配線の製造方法 |
US20020036326A1 (en) * | 1994-08-11 | 2002-03-28 | Harris Corporation | Analog-to-digital converter and method of fabrication |
US6248650B1 (en) * | 1997-12-23 | 2001-06-19 | Texas Instruments Incorporated | Self-aligned BJT emitter contact |
SE517434C3 (sv) | 1999-10-08 | 2002-08-07 | Ericsson Telefon Ab L M | Bipolär högfrekvenskiseltransistor och förfarande för att förbättra karakeristiken för en sådan transistor genom tillägg av indium i transistors bas |
US6509242B2 (en) * | 2001-01-12 | 2003-01-21 | Agere Systems Inc. | Heterojunction bipolar transistor |
US20020197807A1 (en) * | 2001-06-20 | 2002-12-26 | International Business Machines Corporation | Non-self-aligned SiGe heterojunction bipolar transistor |
US6518111B1 (en) * | 2001-12-20 | 2003-02-11 | Texas Instruments Incorporated | Method for manufacturing and structure of semiconductor device with dielectric diffusion source and CMOS integration |
JP2005109361A (ja) * | 2003-10-01 | 2005-04-21 | Sanyo Electric Co Ltd | 半導体装置及びその製造方法 |
JP2006049685A (ja) * | 2004-08-06 | 2006-02-16 | Sanyo Electric Co Ltd | 半導体装置の製造方法 |
US8450179B2 (en) | 2006-02-02 | 2013-05-28 | Texas Instruments Deutschland Gmbh | Semiconductor device having a first bipolar device and a second bipolar device and method for fabrication |
US7656003B2 (en) * | 2006-08-25 | 2010-02-02 | Hvvi Semiconductors, Inc | Electrical stress protection apparatus and method of manufacture |
JP2008187124A (ja) * | 2007-01-31 | 2008-08-14 | Fujitsu Ltd | 半導体装置及びその製造方法 |
US7572706B2 (en) | 2007-02-28 | 2009-08-11 | Freescale Semiconductor, Inc. | Source/drain stressor and method therefor |
US7572708B1 (en) * | 2007-03-08 | 2009-08-11 | National Semiconductor Corporation | Utilization of doped glass on the sidewall of the emitter window in a bipolar transistor structure |
JP4784595B2 (ja) | 2007-12-21 | 2011-10-05 | 株式会社デンソー | バイポーラ型の半導体装置の製造方法 |
JP5298565B2 (ja) * | 2008-02-22 | 2013-09-25 | 富士電機株式会社 | 半導体装置およびその製造方法 |
DE102009001552A1 (de) * | 2008-12-12 | 2010-06-17 | Ihp Gmbh - Innovations For High Performance Microelectronics / Leibniz-Institut Für Innovative Mikroelektronik | Bipolartransistor mit selbstjustiertem Emitterkontakt |
CN101908559B (zh) * | 2009-06-08 | 2013-03-13 | 上海华虹Nec电子有限公司 | 硅-锗异质结双极晶体管及其制造方法 |
TWI474481B (zh) | 2010-01-13 | 2015-02-21 | Macronix Int Co Ltd | 高增益常數β雙極性接面電晶體及其製造方法 |
CN202259239U (zh) * | 2011-08-29 | 2012-05-30 | 王寿良 | 高稳定性电子三极管 |
GB201207448D0 (en) * | 2012-04-26 | 2012-06-13 | Spts Technologies Ltd | Method of depositing silicon dioxide films |
CN105063576A (zh) * | 2015-08-24 | 2015-11-18 | 沈阳拓荆科技有限公司 | 一种采用teos源的低温镀膜方法 |
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Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2000501234A (ja) | 1995-11-20 | 2000-02-02 | テレフオンアクチーボラゲツト エル エム エリクソン(パブル) | 半導体装置の製造に関する方法 |
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CN109643654A (zh) | 2019-04-16 |
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