JP7083026B2 - 半導体デバイスの製造方法と集積半導体デバイス - Google Patents
半導体デバイスの製造方法と集積半導体デバイス Download PDFInfo
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- JP7083026B2 JP7083026B2 JP2020535534A JP2020535534A JP7083026B2 JP 7083026 B2 JP7083026 B2 JP 7083026B2 JP 2020535534 A JP2020535534 A JP 2020535534A JP 2020535534 A JP2020535534 A JP 2020535534A JP 7083026 B2 JP7083026 B2 JP 7083026B2
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Description
本発明は半導体製造の分野に関し、具体的には、半導体デバイスの製造方法と集積半導体デバイスに関する。
半導体基板を用意し、前記半導体基板の表面において、第一領域と、第二領域と、前記第一領域と前記第二領域との間に位置する第三領域とを有する第一ドープタイプのエピタキシャル層を形成し、前記第三領域において前記第一ドープタイプのエピタキシャル層中に位置する少なくとも一つのトレンチを形成することと、
前記第一領域と前記第二領域のそれぞれにおいて少なくとも二つの第二ドープタイプのディープウェルを形成することと、
前記トレンチを充填し、前記第一ドープタイプのエピタキシャル層上に位置する第一誘電体アイランドと第二誘電体アイランドと第三誘電体アイランドとを含む誘電体アイランドを形成し、前記第一誘電体アイランドの一部が前記第一領域における隣接する二つの前記第二ドープタイプのディープウェル間の領域を覆い、他の部分が前記第二領域における隣接する二つの前記第二ドープタイプのディープウェル間の領域を覆い、そして前記第一誘電体アイランドが前記隣接する二つの前記第二ドープタイプのディープウェルのいずれにも接触せず、前記第二誘電体アイランドの一部が前記第一領域に位置する前記第二ドープタイプのディープウェルの領域の一部を覆い、他の部分が前記第二領域に位置する前記第二ドープタイプのディープウェルの領域の一部を覆い、前記第一領域中の前記第二誘電体アイランド両側の第二ドープタイプのディープウェルと前記第二領域中の前記第二誘電体アイランド両側の第二ドープタイプのディープウェルが第一ドープタイプのソース領域を形成する予定の領域となり、前記第三誘電体アイランドが前記トレンチを覆うことと、
前記第一領域中の前記第一誘電体アイランド両側のエピタキシャル層において、前記第一領域における第一ドープタイプのソース領域を形成する予定の領域まで伸びる第一ドープタイプのチャネルをそれぞれ形成することと、
前記第一ドープタイプのエピタキシャル層上において、前記第一誘電体アイランドと前記第三誘電体アイランドのそれぞれを覆うように、前記第二誘電体アイランド及び前記第一領域と前記第二領域のそれぞれに位置する前記した第一ドープタイプのソース領域を形成する予定の領域を露出させるゲート構造を形成することと、
前記ゲート構造と前記第二誘電体アイランドをマスクとして第一ドープタイプのソース領域のためのイオン注入を行って、前記第一領域と前記第二領域のそれぞれに第一ドープタイプのソース領域を形成することと、
を少なくとも含み、
前記第一ドープタイプと前記第二ドープタイプが互いに逆となるものである、半導体デバイスの製造方法。
従来技術による問題を解決するために、本願は半導体デバイスの製造方法と集積半導体デバイスを提供する。
本願は、実施例1に記載の方法で製造された集積半導体デバイスを含む集積半導体デバイスをさらに提供する。
Claims (14)
- 半導体デバイスの製造方法であって、
半導体基板を用意し、前記半導体基板の表面において、第一領域と、第二領域と、前記第一領域と前記第二領域との間に位置する第三領域とを有する第一ドープタイプのエピタキシャル層を形成し、前記第三領域において前記第一ドープタイプのエピタキシャル層中に位置する少なくとも一つのトレンチを形成することと、
前記第一領域と前記第二領域のそれぞれにおいて少なくとも二つの第二ドープタイプのディープウェルを形成することと、
前記トレンチを充填し、前記第一ドープタイプのエピタキシャル層上に位置する第一誘電体アイランドと第二誘電体アイランドと第三誘電体アイランドとを含む誘電体アイランドを形成し、前記第一誘電体アイランドの一部が前記第一領域における隣接する二つの前記第二ドープタイプのディープウェル間の領域を覆い、他の部分が前記第二領域における隣接する二つの前記第二ドープタイプのディープウェル間の領域を覆い、そして前記第一誘電体アイランドが前記隣接する二つの前記第二ドープタイプのディープウェルのいずれにも接触せず、前記第二誘電体アイランドの一部が前記第一領域に位置する前記第二ドープタイプのディープウェルの領域の一部を覆い、他の部分が前記第二領域に位置する前記第二ドープタイプのディープウェルの領域の一部を覆い、前記第一領域中の前記第二誘電体アイランド両側の第二ドープタイプのディープウェルと前記第二領域中の前記第二誘電体アイランド両側の第二ドープタイプのディープウェルが第一ドープタイプのソース領域を形成する予定の領域となり、前記第三誘電体アイランドが前記トレンチを覆うことと、
前記第一領域中の前記第一誘電体アイランド両側のエピタキシャル層において、前記第一領域における第一ドープタイプのソース領域を形成する予定の領域まで伸びる第一ドープタイプのチャネルをそれぞれ形成することと、
前記第一ドープタイプのエピタキシャル層上において、前記第一誘電体アイランドと前記第三誘電体アイランドのそれぞれを覆うように、前記第二誘電体アイランド及び前記第一領域と前記第二領域のそれぞれに位置する前記した第一ドープタイプのソース領域を形成する予定の領域を露出させるゲート構造を形成することと、
前記ゲート構造と前記第二誘電体アイランドをマスクとして第一ドープタイプのソース領域のためのイオン注入を行って、前記第一領域と前記第二領域のそれぞれに第一ドープタイプのソース領域を形成することと、
を少なくとも含み、
前記第一ドープタイプと前記第二ドープタイプが互いに逆となるものであることを特徴とする、半導体デバイスの製造方法。 - 前記トレンチの深さは前記第一ドープタイプのエピタキシャル層の厚さと等しい又は大きいことを特徴とする、請求項1に記載の製造方法。
- 前記した前記トレンチを充填し、前記第一ドープタイプのエピタキシャル層上に位置する誘電体アイランドを形成することは、
前記第一ドープタイプのエピタキシャル層を覆いながら前記トレンチを充填した誘電材料層を形成することと、
前記誘電材料層をパターン化させて、前記誘電体アイランドを形成することと、
を含むことを特徴とする、請求項1に記載の製造方法。 - 前記した第一ドープタイプのソース領域を形成した後にソースを形成することをさらに含み、つまり、
前記第一ドープタイプのエピタキシャル層上において、前記ゲート構造と前記第一ドープタイプのソース領域を覆いながら前記第二誘電体アイランドを露出させる誘電体層を形成することと、
前記第二誘電体アイランドと一部の前記誘電体層を除去して、前記第二ドープタイプのディープウェルに位置する前記第一ドープタイプのソース領域の一部及び前記第二誘電体アイランド下に位置する領域を露出させる開口を形成することと、
前記第一ドープタイプのエピタキシャル層上に前記開口を充填する前記ソースを形成することと、
をさらに含み、
前記ソースは、前記第一領域に位置する前記第二ドープタイプのディープウェル及び前記第二ドープタイプのディープウェルに位置する前記第一ドープタイプのソース領域に接触する第一領域ソースと、前記第二領域に位置する前記第二ドープタイプのディープウェル及び前記第二ドープタイプのディープウェルに位置する前記第一ドープタイプのソース領域に接触する第二領域ソースとを含み、前記第一領域ソースと第二領域ソースは接触していないことを特徴とする、請求項1に記載の製造方法。 - 前記した第一ドープタイプのソース領域を形成した後、前記したソースを形成する前に、残りの前記誘電体層をマスクとして第二ドープタイプのソース領域のためのイオン注入を実行して、前記第一ドープタイプのソース領域同士間の領域に第二ドープタイプのソース領域を形成し、前記第一ドープタイプのソース領域のためのイオン注入よりも前記第二ドープタイプのソース領域のためのイオン注入は注入量が小さいことを特徴とする、請求項4に記載の製造方法。
- 前記した第一ドープタイプのソース領域を形成した後、前記したソースを形成する前に、前記第一ドープタイプのソース領域下に第二ドープタイプのウェル領域を形成することをさらに含むことを特徴とする、請求項5に記載の製造方法。
- 前記した第二ドープタイプのウェル領域を形成した後、前記したソースを形成する前に、前記第二ドープタイプのソース領域下に、両側の前記第二ドープタイプのウェル領域を接続する別の第二ドープタイプのウェル領域を形成することを特徴とする、請求項6に記載の製造方法。
- 前記した前記トレンチを充填する前に、
前記トレンチの側壁と底部の熱シリカ層を形成することをさらに含むことを特徴とする、請求項1に記載の製造方法。 - 前記誘電体アイランドを形成した後、かつ前記第一ドープタイプのチャネルを形成する前に、デバイスの閾値電圧を調整するために閾値電圧調整用注入を行うことをさらに含むことを特徴とする、請求項1に記載の製造方法。
- 前記ソースを形成した後、前記第一ドープタイプの半導体基板の裏面にドレインを形成することをさらに含むことを特徴とする、請求項4に記載の製造方法。
- 前記した第一ドープタイプのソース領域のためのイオン注入では、イオン注入用のエネルギ範囲は50Kev~150Kevであり、注入量範囲は5.0E15/cm2~1.0E16/cm2であることを特徴とする、請求項1に記載の製造方法。
- 前記第二ドープタイプのディープウェルを形成することは、
前記第一ドープタイプのエピタキシャル層上において、前記した第二ドープタイプのディープウェルを形成するつもりの領域を露出させるパターン化マスク層を形成することと、
第二ドープタイプのディープウェルのためのイオン注入を実行して、前記第一ドープタイプのエピタキシャル層に第二ドープタイプのディープウェルを形成することと、
前記パターン化マスク層を除去することと、
を含むことを特徴とする、請求項1に記載の製造方法。 - 前記第二ドープタイプのディープウェルのためのイオン注入の後、第二ドープタイプのディープウェルの焼きなましを実行することをさらに含み、前記第二ドープタイプのディープウェルの焼きなましは、温度範囲が1100℃~1200℃であり、時間範囲が60min~300minであることを特徴とする、請求項1に記載の製造方法。
- 前記半導体基板は第一ドープタイプのものであり、前記半導体デバイスはVDMOSデバイスを含み、第一領域にディプリーション型VDMOSデバイスを形成し、前記第二領域にエンハンスメント型VDMOSデバイスを形成し、あるいは、前記半導体基板は第二ドープタイプのものであり、前記半導体デバイスはIGBTデバイスを含み、前記第一領域にディプリーション型IGBTデバイスを形成し、前記第二領域にエンハンスメント型IGBTデバイスを形成することを特徴とする、請求項1乃至請求項13のいずれか一つに記載の製造方法。
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US11257720B2 (en) | 2022-02-22 |
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