JP7028590B2 - セルフ構成するbmc及びその動作方法 - Google Patents
セルフ構成するbmc及びその動作方法 Download PDFInfo
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- JP7028590B2 JP7028590B2 JP2017173460A JP2017173460A JP7028590B2 JP 7028590 B2 JP7028590 B2 JP 7028590B2 JP 2017173460 A JP2017173460 A JP 2017173460A JP 2017173460 A JP2017173460 A JP 2017173460A JP 7028590 B2 JP7028590 B2 JP 7028590B2
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/44—Arrangements for executing specific programs
- G06F9/4401—Bootstrapping
- G06F9/4411—Configuring for operating with peripheral devices; Loading of device drivers
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/30—Monitoring
- G06F11/3003—Monitoring arrangements specially adapted to the computing system or computing system component being monitored
- G06F11/3031—Monitoring arrangements specially adapted to the computing system or computing system component being monitored where the computing system component is a motherboard or an expansion card
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/30—Monitoring
- G06F11/3058—Monitoring arrangements for monitoring environmental properties or parameters of the computing system or of the computing system component, e.g. monitoring of power, currents, temperature, humidity, position, vibrations
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
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- General Engineering & Computer Science (AREA)
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- Mathematical Physics (AREA)
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- Debugging And Monitoring (AREA)
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Description
ホストがシャーシ内のすべてのNVM装置を識別するのに必要な時間を減らすための方法が依然として要求されている。
装置の構成の変化に対してプロキシ装置に通知する段階は、装置の構成の現在状態に対してプロキシ装置からクエリーを受信する段階と、プロキシ装置に、装置の構成の変化を含む応答を伝送する段階と、を含む。
110、705 プロセッサ
115 メモリ
120 ストレージ装置
125、710 BMC
205 メモリコントローラ
210 クロック
215 ネットワークコネクター
220 バス
225 ユーザーインターフェイス
230 入/出力エンジン
305 CPLD
310 マザーボード
315 ミッドプレーン
320、325、330 NASSD
335 I2Cバス
340 SMBus
345 EEPROM
350 不揮発性メモリ
355 VPD
415 アクセスロジック
420 ビルトインセルフ構成ロジック
425 エラーレポーティングロジック
430 装置通信ロジック
435 ログページ生成ロジック
440 レセプションロジック
445 伝送ロジック
505 VPDリーディングロジック
510 ピンリーディングロジック
605、610 ピン
805 ドライバーダウンローダ
810 ドライバーローダー
815 NVMeドライバー
820 NVMeoFドライバー
825 HAドライバー
905 ネットワーク
910、915 マシン
1005 読出しロジック
1010 ポーリングロジック
1105 クエリー
1110 応答
1115 ログページ
Claims (19)
- BMC(Baseboard Management Controller)において、
シャーシの構成を判定するアクセスロジックと、
前記シャーシの構成に応じて前記BMCを構成するビルトインセルフ構成(built-in self-configuration)ロジックと、を備え、
前記BMCは、BIOS(Basic Input Output System)、装置ドライバー、又はオペレーティングシステム(operating system)を使用することなく、セルフ構成(self-configure)し、
前記ビルトインセルフ構成ロジックは、前記BMCの構成に応じて、NVMe(Non-Volatile Memory express)ドライバー又はNVMeoF(NVM over Fabric)ドライバーを使用するように前記BMCを構成することを特徴とするBMC。 - 前記NVMeoFドライバーを使用して、前記BMCが前記BMCを含むシャーシ内の少なくとも1つの装置の構成を判定することを特徴とする請求項1に記載のBMC。
- 前記アクセスロジックは、VPD(Vital Product Data)から前記シャーシの構成を読み出すVPDリーディングロジックを含むことを特徴とする請求項1に記載のBMC。
- 前記VPDは、EEPROM(Electrically Erasable Programmable Read Only Memory)に格納されることを特徴とする請求項3に記載のBMC。
- 前記アクセスロジックは、前記BMC上の少なくとも1つのピン上の信号から前記シャーシの構成を判定するピンリーディングロジックを含むことを特徴とする請求項1に記載のBMC。
- 前記ビルトインセルフ構成ロジックは、前記シャーシの構成に応じて前記NVMeドライバー又は前記NVMeoFドライバーをロード(load)するドライバーローダーを含むことを特徴とする請求項1に記載のBMC。
- 前記アクセスロジックは、前記シャーシの構成がHA(High Availability)シャーシを含むか否かを判定することを特徴とする請求項1に記載のBMC。
- 前記ビルトインセルフ構成ロジックは、HAドライバーをロードすることを特徴とする請求項7に記載のBMC。
- 前記ビルトインセルフ構成ロジックは、前記BMCがペアリングパートナー(pairing partner)が使用可能であるか否かを判定する前に、前記HAドライバーをロードすることを特徴とする請求項8に記載のBMC。
- BMC(Baseboard Management Controller)によって、前記BMCを含むシャーシの構成を判定する段階と、
前記シャーシの構成に応じて前記BMCに対するドライバーを選択する段階と、
前記選択されたドライバーをローディングする段階と、を有し、
前記BMCは、BIOS、装置ドライバー、又はオペレーティングシステムの中のいずれも使用することなく、セルフ構成することを特徴とするBMCの動作方法。 - 前記シャーシの構成は、NVMeペアリング及びNVMeoFシャーシを含むセットから抽出され、
前記シャーシの構成に応じて前記BMCに対するドライバーを選択する段階は、前記シャーシの構成にしたがって前記BMCに対するNVMeドライバー及びNVMeoFドライバーの中の1つを選択する段階を含むことを特徴とする請求項10に記載のBMCの動作方法。 - 前記BMCによって、前記BMCを含むシャーシの構成を判定する段階は、VPD(Vital Product Data)から前記シャーシの構成を読み出す段階を含むことを特徴とする請求項11に記載のBMCの動作方法。
- 前記VPDは、EEPROMに格納されることを特徴とする請求項12に記載のBMCの動作方法。
- 前記BMCによって、前記BMCを含むシャーシの構成を判定する段階は、前記シャーシの構成を判定するために前記BMC上の少なくとも1つのピンからの信号にアクセスする段階を含むことを特徴とする請求項11に記載のBMCの動作方法。
- 前記BMCによって、前記BMCを含むシャーシの構成を判定する段階は、前記BMCによって前記シャーシがHAシャーシであることを判定する段階を含むことを特徴とする請求項11に記載のBMCの動作方法。
- 前記シャーシの構成に応じて前記BMCに対するドライバーを選択する段階は、HAドライバーを選択する段階を含むことを特徴とする請求項15に記載のBMCの動作方法。
- 前記HAドライバーが使用可能でない場合にエラーをレポーティングする段階をさらに含むことを特徴とする請求項16に記載のBMCの動作方法。
- 前記BMCに対するペアリングパートナーとの通信を試みる段階をさらに含むことを特徴とする請求項16に記載のBMCの動作方法。
- 前記BMCが前記ペアリングパートナーと通信できない場合にエラーをレポーティングする段階をさらに含むことを特徴とする請求項18に記載のBMCの動作方法。
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
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US201662394727P | 2016-09-14 | 2016-09-14 | |
US62/394,727 | 2016-09-14 | ||
US15/345,509 US11461258B2 (en) | 2016-09-14 | 2016-11-07 | Self-configuring baseboard management controller (BMC) |
US15/345,509 | 2016-11-07 |
Publications (2)
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JP2018045689A JP2018045689A (ja) | 2018-03-22 |
JP7028590B2 true JP7028590B2 (ja) | 2022-03-02 |
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US (3) | US11461258B2 (ja) |
JP (1) | JP7028590B2 (ja) |
KR (1) | KR102277412B1 (ja) |
CN (1) | CN107832087B (ja) |
TW (1) | TWI754654B (ja) |
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