JP6997690B2 - パワーモジュール - Google Patents
パワーモジュール Download PDFInfo
- Publication number
- JP6997690B2 JP6997690B2 JP2018179887A JP2018179887A JP6997690B2 JP 6997690 B2 JP6997690 B2 JP 6997690B2 JP 2018179887 A JP2018179887 A JP 2018179887A JP 2018179887 A JP2018179887 A JP 2018179887A JP 6997690 B2 JP6997690 B2 JP 6997690B2
- Authority
- JP
- Japan
- Prior art keywords
- electrode
- power semiconductor
- nickel
- sintered material
- copper electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
- H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/83385—Shape, e.g. interlocking features
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/838—Bonding techniques
- H01L2224/8384—Sintering
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/84—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
- H01L2224/848—Bonding techniques
- H01L2224/8484—Sintering
Landscapes
- Die Bonding (AREA)
Description
パワーモジュール1は、図1及び図2に示すように、ケーシング2と、冷却器3と、絶縁基板4と、電極5と、複数のパワー半導体チップ6と、銀焼結材接合層7と、ニッケルメッキ層8と、はんだ層9と、第1リードフレーム10と、第2リードフレーム11とを備えている。
第2リードフレーム11は、電極5と接続され、電極5と外部端子とを電気的に接続させるための端子として機能する導電部材である。
続いて、上記第1実施形態の変形例を第2実施形態として、図3を参照して説明する。なお、以下の説明において、第1実施形態と同一の構成については符号を同一とし、説明を省略する。
溝部5aは、電極5に対して全体をメッキ加工することによりニッケルメッキ層8を形成し、さらに、ニッケルメッキ層8及び電極5の表面を切削することにより、露出部8aと共に形成される。
5……電極
5a……溝部
6……パワー半導体チップ
7……銀焼結材接合層
8……ニッケルメッキ層
8a……露出部
9……はんだ層
11……第2リードフレーム
Claims (3)
- パワー半導体と、前記パワー半導体と接続される銅電極と、前記銅電極と接続するリードフレームと、前記銅電極と前記パワー半導体とを接合する銀焼結材と、前記銅電極の表面にメッキ処理により設けられるニッケルメッキ層とを備えるパワーモジュールであって、
前記ニッケルメッキ層は、前記銅電極の一部を露出させる露出部を有し、
前記銅電極において前記露出部により露出される部位と前記パワー半導体とは、前記銀焼結材にて接合され、
前記ニッケルメッキ層と前記リードフレームとは、はんだにて接合される
ことを特徴とするパワーモジュール。 - 前記銅電極は、前記露出部より露出される部位に凹部が形成されることを特徴とする請求項1記載のパワーモジュール。
- 前記露出部は、前記銀焼結材と前記ニッケルメッキ層とが接触しない大きさであることを特徴とする請求項1または2記載のパワーモジュール。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2018179887A JP6997690B2 (ja) | 2018-09-26 | 2018-09-26 | パワーモジュール |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2018179887A JP6997690B2 (ja) | 2018-09-26 | 2018-09-26 | パワーモジュール |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2020053503A JP2020053503A (ja) | 2020-04-02 |
JP6997690B2 true JP6997690B2 (ja) | 2022-01-18 |
Family
ID=69997805
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2018179887A Active JP6997690B2 (ja) | 2018-09-26 | 2018-09-26 | パワーモジュール |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP6997690B2 (ja) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP7410822B2 (ja) * | 2020-08-20 | 2024-01-10 | 株式会社 日立パワーデバイス | 半導体パワーモジュールおよび半導体パワーモジュールの製造方法 |
JP7472852B2 (ja) * | 2021-05-27 | 2024-04-23 | 株式会社デンソー | 半導体装置 |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2016024445A1 (ja) | 2014-08-12 | 2016-02-18 | 富士電機株式会社 | 半導体装置 |
WO2016121159A1 (ja) | 2015-01-26 | 2016-08-04 | 三菱電機株式会社 | 半導体装置および半導体装置の製造方法 |
WO2017002793A1 (ja) | 2015-07-01 | 2017-01-05 | 三菱電機株式会社 | 半導体装置および半導体装置の製造方法 |
JP2018148168A (ja) | 2017-03-09 | 2018-09-20 | 日立化成株式会社 | 半導体装置 |
-
2018
- 2018-09-26 JP JP2018179887A patent/JP6997690B2/ja active Active
Patent Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2016024445A1 (ja) | 2014-08-12 | 2016-02-18 | 富士電機株式会社 | 半導体装置 |
US20160343642A1 (en) | 2014-08-12 | 2016-11-24 | Fuji Electric Co., Ltd. | Semiconductor device |
WO2016121159A1 (ja) | 2015-01-26 | 2016-08-04 | 三菱電機株式会社 | 半導体装置および半導体装置の製造方法 |
US20170309544A1 (en) | 2015-01-26 | 2017-10-26 | Mitsubishi Electric Corporation | Semiconductor device and method for manufacturing semiconductor device |
WO2017002793A1 (ja) | 2015-07-01 | 2017-01-05 | 三菱電機株式会社 | 半導体装置および半導体装置の製造方法 |
US20180190611A1 (en) | 2015-07-01 | 2018-07-05 | Mitsubishi Electric Corporation | Semiconductor device and method of manufacturing semiconductor device |
JP2018148168A (ja) | 2017-03-09 | 2018-09-20 | 日立化成株式会社 | 半導体装置 |
Also Published As
Publication number | Publication date |
---|---|
JP2020053503A (ja) | 2020-04-02 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US9035453B2 (en) | Semiconductor device | |
CN108074888B (zh) | 具有双面冷却的电源模块 | |
US9159715B2 (en) | Miniaturized semiconductor device | |
JP6835238B2 (ja) | 半導体装置およびその製造方法 | |
JPWO2018179981A1 (ja) | 半導体装置 | |
JP6997690B2 (ja) | パワーモジュール | |
CN112106194A (zh) | 用于半导体功率模块的排热组件 | |
US20150262917A1 (en) | Semiconductor device and method of manufacturing the same | |
CN110771027B (zh) | 功率半导体装置及使用该装置的电力转换装置 | |
JP6919392B2 (ja) | 半導体モジュール | |
KR101216896B1 (ko) | 파워 모듈 | |
JP2020519027A (ja) | 半導体モジュール | |
JP2006190728A (ja) | 電力用半導体装置 | |
JP6366806B1 (ja) | 電力用半導体装置 | |
JP2004235566A (ja) | 電力用半導体装置 | |
JP5418654B2 (ja) | 半導体装置 | |
EP2840607A1 (en) | Semiconductor module | |
JP2021027146A (ja) | 半導体装置 | |
JP6991950B2 (ja) | パワーモジュール | |
JP5609473B2 (ja) | 半導体装置とその製造方法 | |
JP7095641B2 (ja) | 半導体装置 | |
WO2021220357A1 (ja) | 半導体装置 | |
JP2013051300A (ja) | 半導体モジュール | |
JP7035868B2 (ja) | 半導体装置 | |
JP5151837B2 (ja) | 半導体装置の製造方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20201208 |
|
A711 | Notification of change in applicant |
Free format text: JAPANESE INTERMEDIATE CODE: A712 Effective date: 20210226 |
|
RD04 | Notification of resignation of power of attorney |
Free format text: JAPANESE INTERMEDIATE CODE: A7424 Effective date: 20210408 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20210908 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20210914 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20211108 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20211207 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20211217 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 6997690 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 |