JP6989765B2 - 発光装置の検査方法 - Google Patents
発光装置の検査方法 Download PDFInfo
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- JP6989765B2 JP6989765B2 JP2017179984A JP2017179984A JP6989765B2 JP 6989765 B2 JP6989765 B2 JP 6989765B2 JP 2017179984 A JP2017179984 A JP 2017179984A JP 2017179984 A JP2017179984 A JP 2017179984A JP 6989765 B2 JP6989765 B2 JP 6989765B2
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- light emitting
- emitting device
- resin package
- opening
- geometric center
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48257—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a die pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
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Description
側壁と底面とを備え、上面に開口部を有する凹部を備えた樹脂パッケージと、凹部内に配置される発光素子と、を備える発光装置を準備する工程と、樹脂パッケージの幾何中心位置P1を測定する工程と、開口部の幾何中心位置P2を測定する工程と、P1と前記P2の差分を算出する工程と、差分が、側壁の上面の幅の規定値の35%より大きい場合を不合格とする判定工程と、を備える発光装置の検査方法。
実施形態に係る検査を行う発光装置100の一例を図1A、図1Bに示す。発光装置100は、樹脂パッケージ10と、発光素子20と、を備える。樹脂パッケージ10は、正負一対の電極として機能するリード11と、リード11を一体的に保持する成形樹脂12と、を備える。樹脂パッケージ10は、凹部13を備える。凹部13は、側壁14と底面18とを備え、上面に開口部19を備える。発光素子20は凹部13の底面18上に載置されており、ワイヤ30等を用いてリード11と電気的に接続される。
発光装置100の検査方法においては、例えば、図3に示すような、検査装置を用いる。検査装置は、発光装置100を載置するための支持台200と、支持台200の上方に配置した測定カメラ300と、を備える。
次いで、開口部19の幅(縦幅)L2と、幅(横幅)W2を測定する。得られた測定値から、開口部19の幾何中心位置P2=(X2、Y2)が算出される。
樹脂パッケージ10の幾何中心位置P1と開口部19の幾何中心位置P2の差分DX及びDYは、以下の式(1)(2)から得られる。
DX=|X1-X2|…式(1)
DY=|Y1-Y2|…式(2)
DX>W3×0.35…式(3)
DY>L3×0.35…式(4)
100A…発光装置の集合体
10…樹脂パッケージ
11…リード
12…成形樹脂
13…凹部
14…側壁(15…内側面、16…外側面、17…上面)
18…底面
19…開口部
20…発光素子
30…ワイヤ
40…封止部材
50…切断刃
L1…樹脂パッケージの縦幅
W1…樹脂パッケージの横幅
P1…樹脂パッケージの幾何中心位置
L2…開口部の縦幅
W2…開口部の横幅
P2…開口部の幾何中心位置
L3…側壁の上面の縦幅
W3…側壁の上面の横幅
200…支持台
300…測定カメラ
S…撮像エリア
P0…基準点
PZ…対角点
Claims (3)
- 側壁と底面とを備え、上面に開口部を有する凹部を備えた樹脂パッケージと、前記凹部内に配置される発光素子と、を備える発光装置を準備する工程と、
前記樹脂パッケージの幾何中心位置P1を測定する工程と、
前記開口部の幾何中心位置P2を測定する工程と、
前記P1と前記P2の差分を算出する工程と、
前記差分が、前記側壁の上面の幅の規定値の35%より大きい場合を不合格とする判定工程と、
を備える発光装置の検査方法。 - 前記発光装置を準備する工程は、前記発光装置の集合体を切断して得る工程を経て前記発光装置を得る工程を含む、請求項1記載の発光装置の検査方法。
- 前記樹脂パッケージは、上面視形状が四角形であり、前記開口部は、前記樹脂パッケージの上面視形状と相似形である、請求項1又は請求項2に記載の発光装置の検査方法。
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JP2019057559A JP2019057559A (ja) | 2019-04-11 |
JP6989765B2 true JP6989765B2 (ja) | 2022-01-12 |
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Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2004157338A (ja) | 2002-11-06 | 2004-06-03 | Sony Corp | 電子撮像装置 |
JP2008153553A (ja) | 2006-12-19 | 2008-07-03 | Nichia Chem Ind Ltd | 発光装置およびその製造方法 |
JP2012028686A (ja) | 2010-07-27 | 2012-02-09 | Nitto Denko Corp | 発光装置の検査方法および発光装置の検査後の処理方法 |
US20160197044A1 (en) | 2013-09-23 | 2016-07-07 | Osram Opto Semiconductors Gmbh | Method and apparatus that processes an optoelectronic component |
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- 2017-09-20 JP JP2017179984A patent/JP6989765B2/ja active Active
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2004157338A (ja) | 2002-11-06 | 2004-06-03 | Sony Corp | 電子撮像装置 |
JP2008153553A (ja) | 2006-12-19 | 2008-07-03 | Nichia Chem Ind Ltd | 発光装置およびその製造方法 |
JP2012028686A (ja) | 2010-07-27 | 2012-02-09 | Nitto Denko Corp | 発光装置の検査方法および発光装置の検査後の処理方法 |
US20160197044A1 (en) | 2013-09-23 | 2016-07-07 | Osram Opto Semiconductors Gmbh | Method and apparatus that processes an optoelectronic component |
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