JP6971229B2 - 底部処理 - Google Patents
底部処理 Download PDFInfo
- Publication number
- JP6971229B2 JP6971229B2 JP2018523481A JP2018523481A JP6971229B2 JP 6971229 B2 JP6971229 B2 JP 6971229B2 JP 2018523481 A JP2018523481 A JP 2018523481A JP 2018523481 A JP2018523481 A JP 2018523481A JP 6971229 B2 JP6971229 B2 JP 6971229B2
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- Prior art keywords
- substrate
- strain
- back side
- annealing
- chamber
- Prior art date
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/30—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by physical imperfections; having polished or roughened surface
- H01L29/32—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by physical imperfections; having polished or roughened surface the imperfections being within the semiconductor body
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02115—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material being carbon, e.g. alpha-C, diamond or hydrogen doped carbon
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- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
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Description
Claims (16)
- 前面に形成された装置を有する基板を処理するための方法であって、
前記基板の裏側に非金属の膜を堆積し、その後
前記膜内のストレインを調節するために前記基板の前記裏側を、前記基板における応力又はストレインに基づく所望のパターンに従ってレーザアニールし、その後、
前記膜内のストレインを調節するために前記基板の前記裏側に注入を行う
ことを含む方法。 - 前記膜が、50nmと100nmとの間の深さで堆積される、請求項1に記載の方法。
- 前記膜の領域が、前記基板の前記前面のダイに対応する、請求項2に記載の方法。
- 前記膜が、前記基板内へと溶解又は拡散する、請求項1に記載の方法。
- 前記レーザアニールすることが、スポットアニールであり、前記スポットアニールが、応力のパターンを生成するために前記基板の前記裏側の選択された位置で行われる、請求項1に記載の方法。
- 前記基板の前記裏側をエッチングすることと、
パターニングのために前記基板を位置合わせすることと、
前記基板における歪みを位置特定することと、
前記基板を平らにすることにより、前記歪みを補うことと
をさらに含む、請求項1に記載の方法。 - 前記膜が、窒化物、アモルファスカーボン、又は金属シリサイドのうちの1つを含む、請求項1に記載の方法。
- 前面に形成された装置を有する基板を処理するための方法であって、
前記基板内のストレインを調節するために、前記基板の裏側を、前記基板における応力又はストレインに基づく所望のパターンに従ってレーザアニールし、その後
前記基板内のストレインを調節するために、前記基板の前記裏側に注入を行い、その後
前記基板の前記裏側をエッチングし、その後
パターニングのために前記基板を位置合わせする
ことを含む方法。 - 50nmと100nmとの間の深さで、膜を前記基板の前記裏側に堆積することをさらに含む、請求項8に記載の方法。
- 前記膜の領域が、前記基板の前記前面のダイに対応する、請求項9に記載の方法。
- 前記膜が、前記基板内へと溶解又は拡散する、請求項9に記載の方法。
- 前記レーザアニールすることが、スポットアニールであり、前記スポットアニールが、応力のパターンを生成するために前記基板の前記裏側の選択された位置で行われる、請求項8に記載の方法。
- 前記レーザアニールすることが、ナノ秒アニール処理又はミリ秒アニール処理である、請求項8に記載の方法。
- 前記基板における歪みを位置特定することと、
前記基板を平らにすることにより、前記歪みを補うことと
をさらに含む、請求項8に記載の方法。 - 基板を処理するためのツールであって、
前記基板の裏側に複数の膜層を堆積するための堆積チャンバ、
前記複数の膜層内のストレインを調節するために、前記基板の前記裏側の前記複数の膜層を、前記基板における応力又はストレインに基づく所望のパターンに従ってアニールするためのレーザアニールチャンバであって、基板端部支持体を備えている、レーザアニールチャンバ、
前記基板の前記裏側をエッチングするためのエッチングチャンバであって、基板端部支持体を備えている、エッチングチャンバ、及び
前記基板を、前記堆積チャンバと、前記レーザアニールチャンバと、前記エッチングチャンバとの間で移送するために動作可能に接続された移送チャンバ
を備えているツール。 - 前記複数の膜層内のストレインを調節するために、前記基板の前記裏側に注入を行うための注入チャンバを更に備える、請求項15に記載のツール。
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US201562252901P | 2015-11-09 | 2015-11-09 | |
US62/252,901 | 2015-11-09 | ||
US201662306150P | 2016-03-10 | 2016-03-10 | |
US62/306,150 | 2016-03-10 | ||
PCT/US2016/056220 WO2017083037A1 (en) | 2015-11-09 | 2016-10-10 | Bottom processing |
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JP (1) | JP6971229B2 (ja) |
KR (2) | KR102584138B1 (ja) |
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TW202015095A (zh) | 2020-04-16 |
DE112016005136T5 (de) | 2018-07-26 |
US10128197B2 (en) | 2018-11-13 |
KR102584138B1 (ko) | 2023-10-04 |
TWI729498B (zh) | 2021-06-01 |
KR20180069920A (ko) | 2018-06-25 |
KR20230152092A (ko) | 2023-11-02 |
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