JP6956600B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP6956600B2 JP6956600B2 JP2017217346A JP2017217346A JP6956600B2 JP 6956600 B2 JP6956600 B2 JP 6956600B2 JP 2017217346 A JP2017217346 A JP 2017217346A JP 2017217346 A JP2017217346 A JP 2017217346A JP 6956600 B2 JP6956600 B2 JP 6956600B2
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- 239000004065 semiconductor Substances 0.000 title claims description 83
- 238000009792 diffusion process Methods 0.000 claims description 109
- 239000000758 substrate Substances 0.000 claims description 32
- 238000009413 insulation Methods 0.000 claims description 23
- 239000012535 impurity Substances 0.000 claims description 13
- 239000000969 carrier Substances 0.000 description 28
- 229920002120 photoresistant polymer Polymers 0.000 description 11
- 230000000694 effects Effects 0.000 description 10
- 230000005684 electric field Effects 0.000 description 9
- 229910052581 Si3N4 Inorganic materials 0.000 description 6
- 230000015572 biosynthetic process Effects 0.000 description 6
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 5
- 229910052814 silicon oxide Inorganic materials 0.000 description 5
- 238000000034 method Methods 0.000 description 4
- 238000004088 simulation Methods 0.000 description 4
- 230000006378 damage Effects 0.000 description 3
- 238000009826 distribution Methods 0.000 description 3
- 238000005468 ion implantation Methods 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 230000008569 process Effects 0.000 description 3
- 230000001133 acceleration Effects 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 230000002040 relaxant effect Effects 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 238000004380 ashing Methods 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 230000000052 comparative effect Effects 0.000 description 1
- 230000003292 diminished effect Effects 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
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- Insulated Gate Type Field-Effect Transistor (AREA)
Description
また、上記LDMOSは、STI領域205によって、他の領域(図示せず)と分離されている。
102 n型拡散領域
103 p型拡散領域
104 トレンチ絶縁領域
105 STI領域
106 p型ソースコンタクト領域
107 p型ドレインコンタクト領域
110 n型拡散領域
108 ゲート絶縁膜
109 ゲート電極
121 シリコン窒化膜
122 イオン注入の方向
123 フォトレジスト
131、132、133 空乏層
111 n型埋め込み層
112 p型拡散領域
Claims (6)
- 半導体基板と、
前記半導体基板中に互いに隣接して形成された第1導電型の第1の拡散領域及び第2導電型の第2の拡散領域と、
前記第1の拡散領域中に形成された第1導電型のドレインコンタクト領域と、
前記第2の拡散領域中に形成された第1導電型のソースコンタクト領域と、
前記ドレインコンタクト領域と前記ソースコンタクト領域との間の前記第1の拡散領域中に形成されたトレンチ絶縁領域と、
前記ソースコンタクト領域と前記トレンチ絶縁領域との間の前記第1の拡散領域において、前記トレンチ絶縁領域の前記ソースコンタクト側の側壁に隣接して形成された第2導電型の第3の拡散領域と、
前記半導体基板上にゲート絶縁膜を介して形成され、前記ソースコンタクト領域の前記ドレインコンタクト領域側の端部から前記トレンチ絶縁領域上までを覆うゲート電極とを備えることを特徴とする半導体装置。 - 前記第3の拡散領域は、前記トレンチ絶縁領域の前記側壁全面及び底面の少なくとも一部を連続して覆っていることを特徴とする請求項1に記載の半導体装置。
- 前記第3の拡散領域は、前記トレンチ絶縁領域の前記側壁の上端部を含む少なくとも一部を覆っていることを特徴とする請求項1に記載の半導体装置。
- 前記第3の拡散領域と前記トレンチ絶縁領域の前記側壁との間に前記第1の拡散領域の一部が介在していることを特徴とする請求項1に記載の半導体装置。
- 前記半導体基板の前記第1及び第2の拡散領域の下に前記第1及び第2の拡散領域と離間して形成された第2導電型の埋め込み層をさらに備えることを特徴とする請求項1乃至4のいずれか一項に記載の半導体装置。
- 前記ドレインコンタクト領域の下部に形成され、不純物濃度が前記第1の拡散領域よりも高く前記ドレインコンタクト領域よりも低い第1導電型の第4の拡散領域をさらに備えることを特徴とする請求項1乃至5のいずれか一項に記載の半導体装置。
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JP2017217346A JP6956600B2 (ja) | 2017-11-10 | 2017-11-10 | 半導体装置 |
US16/184,015 US10825927B2 (en) | 2017-11-10 | 2018-11-08 | LDMOS device having hot carrier suppression |
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JP2017217346A JP6956600B2 (ja) | 2017-11-10 | 2017-11-10 | 半導体装置 |
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JP6956600B2 true JP6956600B2 (ja) | 2021-11-02 |
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US11195947B2 (en) * | 2019-10-24 | 2021-12-07 | Globalfoundries U.S. Inc. | Semiconductor device with doped region adjacent isolation structure in extension region |
CN112825327A (zh) * | 2019-11-21 | 2021-05-21 | 中芯国际集成电路制造(上海)有限公司 | 半导体结构及其形成方法 |
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US6900101B2 (en) * | 2003-06-13 | 2005-05-31 | Texas Instruments Incorporated | LDMOS transistors and methods for making the same |
US7791161B2 (en) * | 2005-08-25 | 2010-09-07 | Freescale Semiconductor, Inc. | Semiconductor devices employing poly-filled trenches |
JP5407398B2 (ja) * | 2009-02-12 | 2014-02-05 | 富士電機株式会社 | 半導体装置 |
US8461647B2 (en) * | 2010-03-10 | 2013-06-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device having multi-thickness gate dielectric |
US9159803B2 (en) * | 2012-08-21 | 2015-10-13 | Freescale Semiconductor, Inc. | Semiconductor device with HCI protection region |
JP5887233B2 (ja) * | 2012-09-10 | 2016-03-16 | ルネサスエレクトロニクス株式会社 | 半導体装置およびその製造方法 |
JP2014107302A (ja) | 2012-11-22 | 2014-06-09 | Renesas Electronics Corp | 半導体装置 |
CN104282563A (zh) * | 2013-07-03 | 2015-01-14 | 中芯国际集成电路制造(上海)有限公司 | Ldmos器件及其形成方法 |
KR20150028602A (ko) * | 2013-09-06 | 2015-03-16 | 에스케이하이닉스 주식회사 | 반도체 장치 및 그 제조방법 |
CN105448979B (zh) * | 2014-06-12 | 2018-07-10 | 中芯国际集成电路制造(上海)有限公司 | 横向双扩散场效应管及其形成方法 |
JP6651957B2 (ja) * | 2016-04-06 | 2020-02-19 | 株式会社デンソー | 半導体装置およびその製造方法 |
JP6707439B2 (ja) * | 2016-11-21 | 2020-06-10 | ルネサスエレクトロニクス株式会社 | 半導体装置及びその製造方法 |
US10529804B2 (en) * | 2017-08-21 | 2020-01-07 | Texas Instruments Incorporated | Integrated circuit, LDMOS with trapezoid JFET, bottom gate and ballast drift and fabrication method |
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