JP6844273B2 - Semiconductor device - Google Patents

Semiconductor device Download PDF

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JP6844273B2
JP6844273B2 JP2017007549A JP2017007549A JP6844273B2 JP 6844273 B2 JP6844273 B2 JP 6844273B2 JP 2017007549 A JP2017007549 A JP 2017007549A JP 2017007549 A JP2017007549 A JP 2017007549A JP 6844273 B2 JP6844273 B2 JP 6844273B2
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semiconductor region
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semiconductor
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JP2018117069A (en
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将晴 山路
将晴 山路
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Fuji Electric Co Ltd
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Fuji Electric Co Ltd
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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Description

この発明は、半導体装置に関する。 The present invention relates to semiconductor devices.

従来、高耐圧集積回路装置（ＨＶＩＣ：Ｈｉｇｈ Ｖｏｌｔａｇｅ Ｉｎｔｅｇｒａｔｅｄ Ｃｉｒｃｕｉｔ）では、同一の半導体チップに設けた高電位側（ハイサイド）領域と低電位側（ローサイド）領域とを、これらの領域の間に設けた高耐圧接合終端領域（ＨＶＪＴ：Ｈｉｇｈ Ｖｏｌｔａｇｅ Ｊｕｎｃｔｉｏｎ Ｔｅｒｍｉｎａｔｉｏｎ ｒｅｇｉｏｎ）で電気的に分離する高耐圧接合を利用した素子分離方式が知られている。 Conventionally, in a high voltage integrated circuit device (HVIC: High Voltage Integrated Circuit), a high potential side (high side) region and a low potential side (low side) region provided on the same semiconductor chip are provided between these regions. There is known an element separation method using a high voltage junction that electrically separates in a high voltage junction termination region (HVJT).

ＨＶＩＣは、パワーデバイスを駆動するゲートドライバＩＣとして用いられ、ＨＶＪＴには、ＨＶＩＣのレベルシフト素子として機能する高耐圧のｎチャネル型ＭＯＳＦＥＴ（Ｍｅｔａｌ Ｏｘｉｄｅ Ｓｅｍｉｃｏｎｄｕｃｔｏｒ Ｆｉｅｌｄ Ｅｆｆｅｃｔ Ｔｒａｎｓｉｓｔｏｒ：絶縁ゲート型電界効果トランジスタ（以下、ＨＶＮＭＯＳとする））が配置され、レベルシフト素子を介して高電位領域と低電位領域との間の信号伝達が行われる。 The HVIC is used as a gate driver IC for driving a power device, and the HVJT is a high-voltage n-channel MOSFET (Metal Oxide Semiconductor Field Effect Transistor) that functions as a level shift element of the HVIC (hereinafter referred to as an insulated gate type field effect transistor). , HVNMOS)), and signal transmission between the high potential region and the low potential region is performed via the level shift element.

また、ＨＶＩＣでは、インターフェイスデバイスであるレベルシフト素子を、当該レベルシフト素子のソースと共通電位ＣＯＭ（主直流電源の負極側の電位）との間に抵抗体またはバイポーラ素子などの素子を接続したソースフォロワ構成とした装置が提案されている（例えば、下記特許文献１，２参照。）。レベルシフト素子をソースフォロワ構成とすることで、レベルシフト素子の低電流化、高速化、発熱防止（すなわち損失低減）および信号伝達の安定化等を図っている。従来のＨＶＩＣの回路構成について説明する。 Further, in HVIC, a level shift element, which is an interface device, is a source in which an element such as a resistor or a bipolar element is connected between the source of the level shift element and the common potential COM (potential on the negative electrode side of the main DC power supply). A device having a follower configuration has been proposed (see, for example, Patent Documents 1 and 2 below). By configuring the level shift element as a source follower, the level shift element is designed to reduce the current, increase the speed, prevent heat generation (that is, reduce loss), and stabilize signal transmission. The circuit configuration of the conventional HVIC will be described.

図５は、従来のレベルシフト素子を内蔵したＨＶＩＣの回路構成を示す回路図である。図６は、図５のレベルシフト素子の電圧・電流特性を示す特性図である。図５，６は、下記特許文献１の図５，６である。図５に示す従来のＨＶＩＣ１００は、ブリッジ回路１２０の例えば一相分を形成するＩＧＢＴ１２１，１２２の高電位側（上アーム）のＩＧＢＴ１２１を駆動するゲートドライバＩＣである。ブリッジ回路１２０は、主直流電源の正極側の電位（電源電位）Ｖｄｃと、負極側である共通電位ＣＯＭとの間に、直列に接続されている。 FIG. 5 is a circuit diagram showing a circuit configuration of a conventional HVIC having a built-in level shift element. FIG. 6 is a characteristic diagram showing the voltage / current characteristics of the level shift element of FIG. 5 and 6 are FIGS. 5 and 6 of Patent Document 1 below. The conventional HVIC 100 shown in FIG. 5 is a gate driver IC that drives the IGBT 121 on the high potential side (upper arm) of the IGBTs 121 and 122 forming, for example, one phase of the bridge circuit 120. The bridge circuit 120 is connected in series between the potential (power supply potential) Vdc on the positive electrode side of the main DC power supply and the common potential COM on the negative electrode side.

符号ＯＵＴは、ブリッジ回路１２０の上アームのＩＧＢＴ１２１のエミッタと低電位側（下アーム）のＩＧＢＴ１２２のコレクタとの接続点であり、ブリッジ回路１２０の交流出力端子である。ＨＶＮＭＯＳ（レベルシフト素子）１０１，１０２、負荷抵抗（抵抗体）１０３，１０４、定電圧ダイオード１０５，１０６、ＮＯＴ回路１０７，１０８、ＲＳフリップフロップ（ＲＳ−ＦＦ）１０９、高電位側回路部１１０および補助直流電源Ｅ１は、ブリッジ回路１２０の上アームのＩＧＢＴ１２１を駆動するためのレベルシフト回路である。符号Ｖｃｃ１は、高電位側の補助直流電源Ｅ１の正極ラインの電位（ＨＶＩＣ１００の最高電位）である。 Reference numeral OUT is a connection point between the emitter of the IGBT 121 on the upper arm of the bridge circuit 120 and the collector of the IGBT 122 on the low potential side (lower arm), and is an AC output terminal of the bridge circuit 120. HVNMOS (level shift element) 101, 102, load resistance (resistor) 103, 104, constant voltage diode 105, 106, NOT circuit 107, 108, RS flip-flop (RS-FF) 109, high potential side circuit unit 110 and The auxiliary DC power supply E1 is a level shift circuit for driving the IGBT 121 of the upper arm of the bridge circuit 120. Reference numeral Vcc1 is the potential of the positive electrode line of the auxiliary DC power supply E1 on the high potential side (the maximum potential of the HVIC 100).

ＨＶＮＭＯＳ１０１は制御回路（不図示）により作られたパルスのオン信号１３１の入力を受けて導通し、ＨＶＮＭＯＳ１０１の導通による負荷抵抗１０３の電圧降下を信号としてＩＧＢＴ１２１がオンされる。ＨＶＮＭＯＳ１０２は制御回路で作られたパルスのオフ信号１３２が入力されて導通し、ＨＶＮＭＯＳ１０２の導通による負荷抵抗１０４の電圧降下を信号としてＩＧＢＴ１２１がオフされる。制御回路は、共通電位ＣＯＭを基準とした低電圧側の補助直流電源Ｅ２の正極ラインの電位Ｖｃｃ２から電流を供給される。 The HVNMOS 101 receives the input of the on signal 131 of the pulse created by the control circuit (not shown) and conducts, and the IGBT 121 is turned on by using the voltage drop of the load resistor 103 due to the continuity of the HVNMOS 101 as a signal. The off signal 132 of the pulse created by the control circuit is input to the HVNMOS 102 to conduct the HV NMOS 102, and the IGBT 121 is turned off by using the voltage drop of the load resistor 104 due to the continuity of the HV NMOS 102 as a signal. The control circuit is supplied with a current from the potential Vcc2 of the positive electrode line of the auxiliary DC power supply E2 on the low voltage side with reference to the common potential COM.

レベルシフト回路のうち、２つのＨＶＮＭＯＳ１０１，１０２は、共通電位ＣＯＭを基準とした信号を後段（ＮＯＴ回路１０７，１０８）に入力する回路部分となる。ＨＶＮＭＯＳ１０１とＨＶＮＭＯＳ１０２、および負荷抵抗１０３と負荷抵抗１０４とは通常、それぞれ互いに等しく構成されている。ＨＶＮＭＯＳ１０１，１０２は、ソースと共通電位ＣＯＭとの間に電流負帰還用の抵抗体（以下、電流帰還抵抗とする）１１１，１１２がそれぞれ接続され、ソースフォロア構成になっている。 Of the level shift circuits, the two HVNMOS 101 and 102 are circuit parts for inputting a signal based on the common potential COM to the subsequent stage (NOT circuits 107 and 108). The HVNMOS 101 and the HVNMOS 102, and the load resistor 103 and the load resistor 104 are usually configured to be equal to each other. The HVNMOS 101 and 102 have a source follower configuration in which resistors for current negative feedback (hereinafter referred to as current feedback resistors) 111 and 112 are connected between the source and the common potential COM, respectively.

このようにＨＶＮＭＯＳ１０１，１０２のソースと共通電位ＣＯＭとの間に電流帰還抵抗１１１，１１２を挿入して、ＨＶＮＭＯＳ１０１，１０２をソースフォロア構成にする。かつ、ＨＶＮＭＯＳ１０１，１０２のゲートと共通電位ＣＯＭとの間に印加する電圧を、ＨＶＮＭＯＳ１０１，１０２の負荷抵抗１０３，１０４側電源電圧の最低値を供給する補助直流電源Ｅ１よりも低い電圧値に設定する。これによって、ＨＶＮＭＯＳ１０１，１０２のドレイン電流の定電流性が改善されるとともに、電流帰還抵抗１１１，１１２での電圧降下を小さく抑えることができる。 In this way, the current feedback resistors 111 and 112 are inserted between the source of the HVNMOS 101 and 102 and the common potential COM to form the HVNMOS 101 and 102 into a source follower configuration. Further, the voltage applied between the gate of the HVNMOS 101, 102 and the common potential COM is set to a voltage value lower than that of the auxiliary DC power supply E1 that supplies the lowest value of the load resistance 103, 104 side power supply voltage of the HVNMOS 101, 102. .. As a result, the constant current property of the drain current of the HVNMOS 101 and 102 can be improved, and the voltage drop at the current feedback resistors 111 and 112 can be suppressed to a small value.

電流帰還抵抗１１１，１１２での電圧降下を小さく抑えることで、ＨＶＮＭＯＳ１０１，１０２のドレイン・ソース間電圧の値に依らず、ＨＶＮＭＯＳ１０１，１０２のドレイン電流が小さくなり、かつＨＶＮＭＯＳ１０１，１０２のドレイン電流の変動が小さくなる。このため、ＨＶＩＣ１００の内部電位の高電位側への変動および低電位側への変動に依らず、負荷抵抗１０３，１０４の電圧降下を適切に保って、安定した信号伝達を行うことができる。また、レベルシフト回路の消費電力を削減することができる。 By suppressing the voltage drop at the current feedback resistors 111 and 112 to a small value, the drain current of the HVNMOS 101 and 102 becomes small and the drain current of the HVNMOS 101 and 102 fluctuates regardless of the value of the drain-source voltage of the HVNMOS 101 and 102. Becomes smaller. Therefore, stable signal transmission can be performed by appropriately maintaining the voltage drop of the load resistors 103 and 104 regardless of the fluctuation of the internal potential of the HVIC 100 toward the high potential side and the fluctuation toward the low potential side. Moreover, the power consumption of the level shift circuit can be reduced.

図５に示すＨＶＩＣ１００のレベルシフト回路の動作について、図６を参照して説明する。図６の符号１４１は、ＨＶＮＭＯＳ１０１，１０２単独でのドレイン・ソース間電圧ＶDSとドレイン電流ＩDとの関係を示している。図６の符号１４２は、ＨＶＮＭＯＳ１０１，１０２のソースと共通電位ＣＯＭとの間に電流帰還抵抗１１１，１１２を挿入した場合の、ＨＶＮＭＯＳ１０１，１０２単独でのドレイン・ソース間電圧ＶDSとドレイン電流ＩDとの関係を示している。 The operation of the level shift circuit of the HVIC 100 shown in FIG. 5 will be described with reference to FIG. Code 141 of FIG. 6 shows the relationship between the drain-source voltage V DS and drain current I D in HVNMOS101,102 alone. Code 142 of FIG. 6, in the case of inserting a current feedback resistor 111 between the common potential COM and the source of HVNMOS101,102, drain-source voltage V DS in HVNMOS101,102 alone and the drain current I D Shows the relationship with.

ＨＶＩＣ１００では、ＭＯＳＦＥＴ１０１，１０２がそれぞれオン信号１３１およびオフ信号１３２の入力によって導通したとき、ドレイン電流ＩDによる電流帰還抵抗１１１，１１２での電圧降下により、ＨＶＮＭＯＳ１０１，１０２のゲート・ソース間電圧が減少する。電流帰還抵抗１１１，１１２の電圧降下はゲート電圧（定電圧ダイオード１１３，１１４のツェナー電圧）からＨＶＮＭＯＳ１０１，１０２のゲートしきい値電圧を減算した電圧値を超えないため、ＭＯＳＦＥＴ１０１，１０２のドレイン電流ＩDに負帰還がかかる。 In the HVIC 100, when the MOSFETs 101 and 102 are conducted by the inputs of the on signal 131 and the off signal 132, respectively, the voltage drop at the current feedback resistors 111 and 112 due to the drain current ID reduces the gate-source voltage of the HVNMOS 101 and 102. To do. Since the voltage drop of the current feedback resistors 111 and 112 does not exceed the voltage value obtained by subtracting the gate threshold voltage of the HVNMOS 101 and 102 from the gate voltage (Zener voltage of the constant voltage diodes 113 and 114), the drain current I of the MOSFETs 101 and 102 Negative feedback is applied to D.

ＭＯＳＦＥＴ１０１，１０２のドレイン電流ＩDに負帰還がかかることで、図６に示すように定電流領域が広い電圧・電流特性１４２となる。このため、交流出力端子ＯＵＴの電位が共通電位ＣＯＭに近い場合に負荷抵抗１０３または負荷抵抗１０４の負荷直線１４３で決定されるドレイン電流ＩLと、交流出力端子ＯＵＴの電位がブリッジ回路１２０の電源電位Ｖｄｃに近い場合に負荷抵抗１０３または負荷抵抗１０４の負荷直線１４４で決定されるドレイン電流ＩHと、の差が小さくなり、レベルシフト回路の損失の増加が防止される。 By applying negative feedback to the drain current ID of the MOSFETs 101 and 102, the voltage / current characteristic 142 has a wide constant current region as shown in FIG. Therefore, the power of the AC output terminal OUT and the drain current I L potential is determined by the load line 143 of the load resistor 103 or the load resistor 104 is close to the common potential COM of the AC output terminal OUT of the potential bridge circuit 120 When the potential is close to Vdc, the difference between the load resistance 103 or the drain current I H determined by the load line 144 of the load resistance 104 becomes small, and an increase in the loss of the level shift circuit is prevented.

図７は、従来のレベルシフト素子を内蔵したＨＶＩＣの別の一例の回路構成を示す回路図である。図７は、引用文献２の図３である。図７に示すＨＶＩＣ１５０は、ｎチャネルＭＯＳＦＥＴ１５１、カレントミラー回路１５２および高電位側回路部１５３を備える。ｎチャネルＭＯＳＦＥＴ１５１は、内部ノード１５４と共通電位ＣＯＭの間に接続されている。カレントミラー回路１５２は、電流供給部１５５，１５６から供給される電流に応じた電流を流す。 FIG. 7 is a circuit diagram showing another example circuit configuration of a conventional HVIC having a built-in level shift element. FIG. 7 is FIG. 3 of Cited Document 2. The HVIC 150 shown in FIG. 7 includes an n-channel MOSFET 151, a current mirror circuit 152, and a high potential side circuit unit 153. The n-channel MOSFET 151 is connected between the internal node 154 and the common potential COM. The current mirror circuit 152 causes a current corresponding to the current supplied from the current supply units 155 and 156 to flow.

高電位側回路部１５３は、カレントミラー回路１５２を流れる電流に応じた電圧信号を発生させて、上アームのＩＧＢＴ１２１のゲート駆動信号を生成する。カレントミラー回路１５２は、ＨＶＮＭＯＳ１５７およびバイポーラトランジスタ１５８，１５９を備える。ＨＶＮＭＯＳ１５７は、ゲートが内部ノード１５４に接続され、ドレインが交流出力端子ＯＵＴに接続されている。また、ＨＶＮＭＯＳ１５７は、ソースと共通電位ＣＯＭとの間にバイポーラトランジスタ１５８が接続され、ソースフォロワ構成になっている。 The high potential side circuit unit 153 generates a voltage signal corresponding to the current flowing through the current mirror circuit 152, and generates a gate drive signal of the IGBT 121 of the upper arm. The current mirror circuit 152 includes an HVNMOS 157 and bipolar transistors 158 and 159. In HVNMOS157, the gate is connected to the internal node 154 and the drain is connected to the AC output terminal OUT. Further, the HVNMOS 157 has a source follower configuration in which a bipolar transistor 158 is connected between the source and the common potential COM.

ＨＶＮＭＯＳ１５７は、ゲート電圧よりもドレイン電圧が高くなり、ソースフォロワモードで動作し、高電圧がバイポーラトランジスタ１５８，１５９へ供給されるのを防止する。また、ＨＶＮＭＯＳ１５７は、電流供給部１５５，１５６から供給される電流Ｉｒに等しい電流を高電位側回路部１５３から引き抜くレベルシフト素子である。符号ＨＩＮは上アームのＩＧＢＴ１２１のオン・オフを制御するパルス信号である。符号ＬＩＮは、下アームのＩＧＢＴ１２２のオン・オフを制御するパルス信号である。 The HVNMOS 157 has a drain voltage higher than the gate voltage and operates in the source follower mode to prevent the high voltage from being supplied to the bipolar transistors 158 and 159. Further, the HVNMOS 157 is a level shift element that draws a current equal to the current Ir supplied from the current supply units 155 and 156 from the high potential side circuit unit 153. The symbol HIN is a pulse signal for controlling the on / off of the IGBT 121 of the upper arm. The symbol LIN is a pulse signal that controls the on / off of the IGBT 122 of the lower arm.

これら図５，７に示すＨＶＩＣ１００，１５０のように、レベルシフト素子であるＨＶＮＭＯＳをソースフォロア構成とすることで、ＨＶＮＭＯＳのソースと共通電位ＣＯＭとの間に何も接続しない場合と比べて、ＨＶＮＭＯＳの飽和電流（ドレイン電流）を小さくし、かつ定電流化することができる。このため、プロセスばらつき（例えばゲート絶縁膜の厚さのばらつきなど）によるＨＶＮＭＯＳの飽和電流のばらつきも抑制され、安定したレベルシフト動作が可能となる。 As in the HVICs 100 and 150 shown in FIGS. 5 and 7, when the HVNMOS, which is a level shift element, has a source follower configuration, the HVNMOS is compared with the case where nothing is connected between the source of the HVNMOS and the common potential COM. The saturation current (drain current) of the above can be reduced and the current can be made constant. Therefore, variation in the saturation current of the HVNMOS due to process variation (for example, variation in the thickness of the gate insulating film) is suppressed, and stable level shift operation becomes possible.

ＨＶＩＣの別の一例として、ＨＶＩＣチップの内部寄生ダイオードのアノードと共通電位ＣＯＭとの間に当該内部寄生ダイオードに直列に抵抗体を接続した装置が提案されている（例えば、下記特許文献３参照。）。下記特許文献３では、ブリッジ回路の上アームのＩＧＢＴと下アームのＩＧＢＴとの接続点の電位が負電位になりすぎたときに、ＨＶＩＣチップの内部寄生ダイオードの順方向電流を抵抗体で抑制して、ＨＶＩＣチップを保護している。この抵抗体は、ＨＶＩＣチップ上に絶縁層を介して設けられたポリシリコン層で構成される。 As another example of HVIC, a device in which a resistor is connected in series with the internal parasitic diode between the anode of the internal parasitic diode of the HVIC chip and the common potential COM has been proposed (see, for example, Patent Document 3 below). ). In Patent Document 3 below, when the potential at the connection point between the upper arm IGBT and the lower arm IGBT of the bridge circuit becomes too negative, the forward current of the internal parasitic diode of the HVIC chip is suppressed by a resistor. It protects the HVIC chip. This resistor is composed of a polysilicon layer provided on the HVIC chip via an insulating layer.

従来のＨＶＩＣ１００の構造およびＨＶＮＭＯＳ１０１，１０２の構造について、図８，９を参照して説明する。図８は、従来の半導体装置の平面レイアウトを示す平面図である。平面レイアウトとは、半導体基板（半導体チップ）１６０のおもて面側から見た各部の平面形状および配置構成である。図９は、図８の矩形枠ＡＡにおける断面構造を示す斜視図である。図９には、図８の高電位側回路部のセット（ｓｅｔ）用のレベルシフト回路を構成するＨＶＮＭＯＳ１０１を示す。 The structure of the conventional HVIC100 and the structure of the HVNMOS 101 and 102 will be described with reference to FIGS. 8 and 9. FIG. 8 is a plan view showing a plan layout of a conventional semiconductor device. The planar layout is a planar shape and arrangement configuration of each part of the semiconductor substrate (semiconductor chip) 160 as viewed from the front surface side. FIG. 9 is a perspective view showing a cross-sectional structure of the rectangular frame AA of FIG. FIG. 9 shows the HVNMOS 101 constituting the level shift circuit for the set of the high potential side circuit unit of FIG.

図８に示す従来の半導体装置は、同一の半導体基板１６０上に高電位側領域１７１および低電位側領域１７２を備え、これらの領域をＨＶＪＴ１７３で電気的に分離したＨＶＩＣ１００である。ｐ--型の半導体基板１６０のおもて面の表面層には、ｎ-型拡散領域１６２およびｐ-型分離領域１６４がそれぞれ選択的に設けられている（図９参照）。ｐ-型分離領域１６４は、拡散領域である。以下、ｐ--型の半導体基板１６０の、ｎ-型拡散領域１６２およびｐ-型分離領域１６４以外の部分をｐ--型基板領域１６１とする。 The conventional semiconductor device shown in FIG. 8 is an HVIC 100 having a high potential side region 171 and a low potential side region 172 on the same semiconductor substrate 160, and these regions are electrically separated by an HVJT173. An n- type diffusion region 162 and a p - type separation region 164 are selectively provided on the surface layer of the front surface of the p-type semiconductor substrate 160 (see FIG. 9). The p - type separation region 164 is a diffusion region. Hereinafter, the portion of the p - type semiconductor substrate 160 other than the n- type diffusion region 162 and the p - type separation region 164 will be referred to as the p - type substrate region 161.

高電位側領域１７１は、ｎ-型拡散領域１６２の内部に略矩形状の平面レイアウトに配置されたｎ型拡散領域１６３で構成される。ｐ-型分離領域１６４は、ｎ-型拡散領域１６２およびｐ--型基板領域１６１に接し、かつｎ-型拡散領域１６２の周囲を囲む環状の平面レイアウトに配置されている。ｐ-型分離領域１６４とｎ-型拡散領域１６２とのｐｎ接合で形成される寄生ダイオードでＨＶＪＴ１７３が構成される。ｐ-型分離領域１６４の内部には、ｎ-型拡散領域１６２の周囲を囲む環状の平面レイアウトにｐ+型コンタクト領域１６５が選択的に配置されている。 The high potential side region 171 is composed of an n-type diffusion region 163 arranged in a substantially rectangular plane layout inside the n-type diffusion region 162. The p - type separation region 164 is arranged in an annular planar layout that is in contact with the n - type diffusion region 162 and the p - type substrate region 161 and surrounds the n-type diffusion region 162. The HVJT173 is composed of a parasitic diode formed by a pn junction between a p- type separation region 164 and an n -type diffusion region 162. p - Inside the type isolation region 164, n - p + -type contact region 165 in an annular planar layout surrounding the diffusion region 162 is selectively positioned.

ｐ+型コンタクト領域１６５は、共通電位ＣＯＭの電極パッド（以下、ＣＯＭ電極パッドとする）１９１に電気的に接続され、ｐ-型分離領域１６４およびｐ--型基板領域１６１を共通電位ＣＯＭに固定する。低電位側領域１７２は、ｐ--型基板領域１６１に選択的に設けられたｎ型拡散領域１６６で構成される。ｎ型拡散領域１６６は、ｐ-型分離領域１６４に対してｎ型拡散領域１６３の反対側に配置され、ｐ-型分離領域１６４によりｎ型拡散領域１６３と電気的に絶縁されている。 p + -type contact region 165, the electrode pads of the common potential COM (hereinafter referred to as COM electrode pad) 191 is electrically connected, p - -type isolation region 164 and p - -type substrate region 161 to the common potential COM Fix. The low potential side region 172 is composed of an n-type diffusion region 166 selectively provided in the p-type substrate region 161. n-type diffusion region 166, p - type is disposed on the opposite side of the n-type diffusion region 163 with respect to the isolation region 164, p - -type isolation region 164 is electrically insulated from the n-type diffusion region 163 by.

ＨＶＩＣ１００の高電位側回路部のセット用およびリセット（ｒｅｓｅｔ）用のレベルシフト回路を構成するＨＶＮＭＯＳ１０１，１０２は、ＨＶＪＴ１７３に配置されている。図９に示すように、ＨＶＮＭＯＳ１０１は、バックゲートとなるｐ型拡散領域（以下、ｐ型バックゲート領域とする）１８１、ｎ+型ソース領域１８２、ｐ+型コンタクト領域１８３、ｎ+型ドレイン領域１８４およびゲート電極１８５を備える。ｐ型バックゲート領域１８１およびｎ+型ドレイン領域１８４は、ｎ-型拡散領域１６２の内部にそれぞれ選択的に設けられている。ｐ型バックゲート領域１８１の深さは、ｎ-型拡散領域１６２の深さよりも浅い。 The HVNMOS 101 and 102 constituting the level shift circuit for setting and resetting the high potential side circuit portion of the HVIC 100 are arranged in the HVJT173. As shown in FIG. 9, the HVNMOS 101 has a p-type diffusion region (hereinafter referred to as a p-type backgate region) 181 serving as a back gate, an n + type source region 182, a p + type contact region 183, and an n + type drain region. It includes 184 and a gate electrode 185. The p-type backgate region 181 and the n + -type drain region 184 are selectively provided inside the n- type diffusion region 162, respectively. The depth of the p-type backgate region 181 is shallower than the depth of the n-type diffusion region 162.

ｐ型バックゲート領域１８１は、ｐ-型分離領域１６４と離して、ｐ-型分離領域１６４よりもｎ型拡散領域１６３側に配置される。ｎ+型ドレイン領域１８４は、ｐ型バックゲート領域１８１と離して、ｐ型バックゲート領域１８１よりもｎ型拡散領域１６３側に配置される。ｎ+型ソース領域１８２およびｐ+型コンタクト領域１８３は、ｐ型バックゲート領域１８１の内部に選択的に設けられている。ｎ+型ソース領域１８２およびｐ+型コンタクト領域１８３は、抵抗体ＲSFを介してＣＯＭ電極パッド１９１に電気的に接続されている。抵抗体ＲSFは、図５の電流帰還抵抗１１１に相当する。 The p-type backgate region 181 is arranged on the n-type diffusion region 163 side of the p- type separation region 164, apart from the p -type separation region 164. The n + type drain region 184 is arranged on the n-type diffusion region 163 side of the p-type back gate region 181 apart from the p-type back gate region 181. The n + type source region 182 and the p + type contact region 183 are selectively provided inside the p-type back gate region 181. n + -type source region 182 and the p + -type contact region 183 is electrically connected to the COM electrode pad 191 through a resistor R SF. Resistor R SF corresponds to a current feedback resistor 111 of FIG.

ＨＶＮＭＯＳ１０１のｐ型バックゲート領域１８１およびｎ+型ソース領域１８２と、共通電位ＣＯＭに固定された領域（ｐ--型基板領域１６１およびｐ-型分離領域１６４）と、はｎ-型拡散領域１６２によって電気的に分離される。これによって、ＨＶＮＭＯＳ１０１のソース電位と、共通電位ＣＯＭと、が電気的に分離される。かつ、これらｎ-型拡散領域１６２で電気的に分離された領域間に抵抗体（以下、ソースフォロワ抵抗とする）ＲSF等の抵抗素子が接続される。これによって、ＨＶＮＭＯＳ１０１がソースフォロワ構成となっている。ＨＶＮＭＯＳ１０２の構成は、ＨＶＮＭＯＳ１０１と同様である。 The p-type backgate region 181 and the n + -type source region 182 of the HVNMOS 101, the region fixed to the common potential COM (p - type substrate region 161 and the p - type separation region 164), and the n - type diffusion region 162 Is electrically separated by. As a result, the source potential of the HVNMOS 101 and the common potential COM are electrically separated. And these n - electrically isolated resistors between the regions in the diffusion region 162 (hereinafter referred to as source follower resistance) resistive elements, such as R SF are connected. As a result, the HVNMOS 101 has a source follower configuration. The configuration of the HVNMOS 102 is similar to that of the HVNMOS 101.

ｐ型バックゲート領域１８１が共通電位ＣＯＭに固定された領域と電気的に分離されることで、ｐ型バックゲート領域１８１の電位を共通電位ＣＯＭ以外の電位に固定することが可能となる。また、ブリッジ回路を構成するＩＧＢＴ１２１，１２２のスイッチングによりＨＶＮＭＯＳ１０１のドレインが数百ボルトの高電圧に持ち上がったとしても、ｎ-型拡散領域１６２の、ｐ型バックゲート領域１８１とｐ--型基板領域１６１とに挟まれた部分が空乏化し耐圧が確保される。 By electrically separating the p-type backgate region 181 from the region fixed to the common potential COM, the potential of the p-type backgate region 181 can be fixed to a potential other than the common potential COM. Further, even if the drain of the HVNMOS 101 is lifted to a high voltage of several hundred volts due to switching of the IGBTs 121 and 122 constituting the bridge circuit, the p-type backgate region 181 and the p - type substrate region of the n-type diffusion region 162 The portion sandwiched between the 161 and the 161 is depleted and the pressure resistance is secured.

特許第３９００１７８号公報Japanese Patent No. 3900178 特許第５５３０６６９号公報Japanese Patent No. 5530669 米国特許第６５９７５５０号明細書U.S. Pat. No. 6,597,550

しかしながら、ソースフォロワ構成のＨＶＮＭＯＳが自己分離構造やｐｎ接合分離構造で他の素子と分離されている場合、半導体基板（半導体チップ）内に寄生構造が形成される。このため、意図しない寄生電流によりソースフォロワによるＨＶＮＭＯＳの電流制御ができない虞がある。例えば、半導体基板１６０上のＨＶＮＭＯＳ１０１と他の素子とが自己分離構造で素子分離されている場合（図８，９参照）、次の寄生動作が生じる。 However, when the HVNMOS having a source follower configuration is separated from other elements by a self-separation structure or a pn junction separation structure, a parasitic structure is formed in the semiconductor substrate (semiconductor chip). Therefore, there is a possibility that the current of HVNMOS cannot be controlled by the source follower due to an unintended parasitic current. For example, when the HVNMOS 101 on the semiconductor substrate 160 and another element are separated by a self-separating structure (see FIGS. 8 and 9), the following parasitic operation occurs.

ＨＶＮＭＯＳ１０１がオン状態にあり、ＨＶＮＭＯＳ１０１のドレイン電流が電流帰還抵抗１１１での電圧降下で抑制されたときに、ＨＶＮＭＯＳ１０１のｎ+型ソース領域１８２およびｐ型バックゲート領域１８１の電位が、ｎ-型拡散領域１６２のｐ型バックゲート領域１８１直下の部分（ｐ型バックゲート領域１８１とｐ--型基板領域１６１とに挟まれた部分）の電位よりも０．６Ｖ以上高くなるとする。 When the HVNMOS 101 is in the ON state and the drain current of the HVNMOS 101 is suppressed by the voltage drop at the current feedback resistor 111, the potentials of the n + type source region 182 and the p type back gate region 181 of the HVNMOS 101 are n- type diffused. It is assumed that the potential is 0.6 V or more higher than the potential of the portion of the region 162 immediately below the p-type backgate region 181 (the portion sandwiched between the p-type backgate region 181 and the p-type substrate region 161).

この場合、ｐ型バックゲート領域１８１、ｎ-型拡散領域１６２、ｐ--型基板領域１６１およびｐ-型分離領域１６４からなるｐｎｐ寄生バイポーラトランジスタ１９２がｐ--型基板領域１６１に対して動作する。このため、ＨＶＮＭＯＳ１０１のｎ+型ソース領域１８２と共通電位ＣＯＭとの間のインピーダンスが極端に低くなり、ソースフォロワ構成によるＨＶＮＭＯＳ１０１のドレイン電流安定化の効果が失われる虞がある。 In this case, the pnp parasitic bipolar transistor 192 consisting of the p-type backgate region 181, the n - type diffusion region 162, the p - type substrate region 161 and the p - type separation region 164 operates with respect to the p- type substrate region 161. To do. Therefore, the impedance between the n + type source region 182 of the HVNMOS 101 and the common potential COM becomes extremely low, and the effect of stabilizing the drain current of the HVNMOS 101 by the source follower configuration may be lost.

この発明は、上述した従来技術による問題点を解消するため、安定したレベルシフト動作を行うことができる半導体装置を提供することを目的とする。 An object of the present invention is to provide a semiconductor device capable of performing stable level shift operation in order to solve the above-mentioned problems caused by the prior art.

上述した課題を解決し、本発明の目的を達成するため、この発明にかかる半導体装置は、次の特徴を有する。第１導電型の半導体基板の一方の主面側に、第２導電型の第１半導体領域が選択的に設けられている。前記半導体基板と前記第１半導体領域とのｐｎ接合で分離構造が形成されている。前記分離構造は、電位の異なる領域を分離する。前記第１半導体領域に、半導体素子が設けられている。前記半導体素子は、第２導電型の第２，３半導体領域、ゲート絶縁膜およびゲート電極を有し、前記最低電位を基準とした信号を、前記最低電位と異なる電位を基準とした信号に変換する。前記第２半導体領域は、前記半導体基板の一方の主面側に、前記第１半導体領域と離して選択的に設けられている。前記第２半導体領域は、第１抵抗体を介して最低電位の電極に電気的に接続されている。前記第３半導体領域は、前記第１半導体領域の内部が選択的に設けられている。前記第３半導体領域は、前記第１半導体領域よりも不純物濃度が高い。前記ゲート絶縁膜は、前記第１半導体領域と前記第２半導体領域との間の前記半導体基板に沿って設けられている。前記ゲート電極は、前記ゲート絶縁膜に沿って設けられている。前記半導体基板の一方の主面側に、所定距離で前記第２半導体領域と離して、第１導電型の第４半導体領域が選択的に設けられている。前記第４半導体領域は、前記最低電位の電極に電気的に接続されている。前記第４半導体領域は、前記半導体基板よりも不純物濃度が高い。前記第２半導体領域は、第２抵抗体を介して前記第４半導体領域と電気的に接続されている。前記第２抵抗体は、前記半導体基板の、前記第２半導体領域と前記第４半導体領域との間の部分で構成されている。 In order to solve the above-mentioned problems and achieve the object of the present invention, the semiconductor device according to the present invention has the following features. A second conductive type first semiconductor region is selectively provided on one main surface side of the first conductive type semiconductor substrate. A separated structure is formed by a pn junction between the semiconductor substrate and the first semiconductor region. The separation structure separates regions with different potentials. A semiconductor element is provided in the first semiconductor region. The semiconductor element has a second conductive type second and third semiconductor region, a gate insulating film, and a gate electrode, and converts a signal based on the lowest potential into a signal based on a potential different from the lowest potential. To do. The second semiconductor region is selectively provided on one main surface side of the semiconductor substrate, away from the first semiconductor region. The second semiconductor region is electrically connected to the electrode having the lowest potential via the first resistor. The inside of the first semiconductor region is selectively provided in the third semiconductor region. The third semiconductor region has a higher impurity concentration than the first semiconductor region. The gate insulating film is provided along the semiconductor substrate between the first semiconductor region and the second semiconductor region. The gate electrode is provided along the gate insulating film. A first conductive type fourth semiconductor region is selectively provided on one main surface side of the semiconductor substrate at a predetermined distance from the second semiconductor region. The fourth semiconductor region is electrically connected to the electrode having the lowest potential. The fourth semiconductor region has a higher impurity concentration than the semiconductor substrate. The second semiconductor region is electrically connected to the fourth semiconductor region via a second resistor. The second resistor is composed of a portion of the semiconductor substrate between the second semiconductor region and the fourth semiconductor region.

また、この発明にかかる半導体装置は、上述した発明において、第１導電型の第５半導体領域をさらに備える。前記第５半導体領域は、前記半導体基板の一方の主面側に選択的に設けられ、前記第１半導体領域に接する。前記第５半導体領域は、前記半導体基板よりも不純物濃度が高い。前記分離構造は、前記第５半導体領域と前記第１半導体領域とのｐｎ接合で形成されている。前記第２半導体領域および前記第４半導体領域は、前記第５半導体領域の内部に設けられている。前記ゲート絶縁膜は、前記第１半導体領域と前記第２半導体領域との間の前記第５半導体領域に沿って設けられている。前記第２抵抗体は、前記第５半導体領域の、前記第２半導体領域と前記第４半導体領域との間の部分で構成されていることを特徴とする。 Further, the semiconductor device according to the present invention further includes a first conductive type fifth semiconductor region in the above-described invention. The fifth semiconductor region is selectively provided on one main surface side of the semiconductor substrate and is in contact with the first semiconductor region. The fifth semiconductor region has a higher impurity concentration than the semiconductor substrate. The separated structure is formed by a pn junction between the fifth semiconductor region and the first semiconductor region. The second semiconductor region and the fourth semiconductor region are provided inside the fifth semiconductor region. The gate insulating film is provided along the fifth semiconductor region between the first semiconductor region and the second semiconductor region. The second resistor is characterized in that it is composed of a portion of the fifth semiconductor region between the second semiconductor region and the fourth semiconductor region.

また、この発明にかかる半導体装置は、上述した発明において、第１導電型の第６半導体領域をさらに備える。前記第６半導体領域は、前記第１半導体領域の内部に選択的に設けられ、前記半導体基板の、前記第２半導体領域と前記第４半導体領域との間の部分に接する。前記第６半導体領域は、前記半導体基板よりも不純物濃度が高い。前記第２半導体領域は、前記第６半導体領域の内部に、前記半導体基板の、前記第２半導体領域と前記第４半導体領域との間の部分に接して設けられている。前記ゲート絶縁膜は、前記第１半導体領域と前記第２半導体領域との間の前記第６半導体領域に沿って設けられていることを特徴とする。 Further, the semiconductor device according to the present invention further includes a first conductive type sixth semiconductor region in the above-described invention. The sixth semiconductor region is selectively provided inside the first semiconductor region, and is in contact with a portion of the semiconductor substrate between the second semiconductor region and the fourth semiconductor region. The sixth semiconductor region has a higher impurity concentration than the semiconductor substrate. The second semiconductor region is provided inside the sixth semiconductor region in contact with a portion of the semiconductor substrate between the second semiconductor region and the fourth semiconductor region. The gate insulating film is characterized in that it is provided along the sixth semiconductor region between the first semiconductor region and the second semiconductor region.

また、この発明にかかる半導体装置は、上述した発明において、第１導電型の第６半導体領域をさらに備える。前記第６半導体領域は、前記第１半導体領域の内部に選択的に設けられ、前記第５半導体領域の、前記第２半導体領域と前記第４半導体領域との間の部分に接する。前記第６半導体領域は、前記第５半導体領域よりも不純物濃度が高い。前記第２半導体領域は、前記第６半導体領域の内部に、前記第５半導体領域の、前記第２半導体領域と前記第４半導体領域との間の部分に接して設けられている。前記ゲート絶縁膜は、前記第１半導体領域と前記第２半導体領域との間の前記第６半導体領域に沿って設けられていることを特徴とする。 Further, the semiconductor device according to the present invention further includes a first conductive type sixth semiconductor region in the above-described invention. The sixth semiconductor region is selectively provided inside the first semiconductor region and is in contact with a portion of the fifth semiconductor region between the second semiconductor region and the fourth semiconductor region. The sixth semiconductor region has a higher impurity concentration than the fifth semiconductor region. The second semiconductor region is provided inside the sixth semiconductor region in contact with a portion of the fifth semiconductor region between the second semiconductor region and the fourth semiconductor region. The gate insulating film is characterized in that it is provided along the sixth semiconductor region between the first semiconductor region and the second semiconductor region.

また、この発明にかかる半導体装置は、上述した発明において、前記半導体基板の、前記第２半導体領域と前記第４半導体領域との間の部分に選択的に設けられた第２導電型の第７半導体領域をさらに備えることを特徴とする。 Further, in the above-described invention, the semiconductor device according to the present invention is a second conductive type seventh selectively provided in a portion of the semiconductor substrate between the second semiconductor region and the fourth semiconductor region. It is characterized by further including a semiconductor domain.

また、この発明にかかる半導体装置は、上述した発明において、前記半導体基板の、前記第２半導体領域と前記第４半導体領域との間の部分に選択的に設けられ、前記第６半導体領域に電気的に接続された第２導電型の第７半導体領域をさらに備えることを特徴とする。 Further, in the above-described invention, the semiconductor device according to the present invention is selectively provided in a portion of the semiconductor substrate between the second semiconductor region and the fourth semiconductor region, and electricity is provided in the sixth semiconductor region. It is characterized by further including a second conductive type seventh semiconductor region connected to the object.

また、この発明にかかる半導体装置は、上述した発明において、前記第５半導体領域の、前記第２半導体領域と前記第４半導体領域との間の部分に選択的に設けられた第２導電型の第７半導体領域をさらに備えることを特徴とする。 Further, the semiconductor device according to the present invention is of the second conductive type selectively provided in the portion of the fifth semiconductor region between the second semiconductor region and the fourth semiconductor region in the above-described invention. It is characterized by further including a seventh semiconductor region.

また、この発明にかかる半導体装置は、上述した発明において、前記第５半導体領域の、前記第２半導体領域と前記第４半導体領域との間の部分に選択的に設けられ、前記第６半導体領域に電気的に接続された第２導電型の第７半導体領域をさらに備えることを特徴とする。 Further, in the above-described invention, the semiconductor device according to the present invention is selectively provided in a portion of the fifth semiconductor region between the second semiconductor region and the fourth semiconductor region, and the sixth semiconductor region. It is characterized by further comprising a second conductive type seventh semiconductor region electrically connected to the semiconductor.

また、この発明にかかる半導体装置は、上述した発明において、前記第７半導体領域の電位は、浮遊電位または電源電位であることを特徴とする。 Further, the semiconductor device according to the present invention is characterized in that, in the above-described invention, the potential of the seventh semiconductor region is a floating potential or a power supply potential.

また、この発明にかかる半導体装置は、上述した発明において、前記第１抵抗体は、前記第２抵抗体に並列に接続された抵抗素子であることを特徴とする。 Further, the semiconductor device according to the present invention is characterized in that, in the above-described invention, the first resistor is a resistance element connected in parallel to the second resistor.

また、この発明にかかる半導体装置は、上述した発明において、前記第１抵抗体の抵抗値よりも前記第２抵抗体の抵抗値の方が高いことを特徴とする。 Further, the semiconductor device according to the present invention is characterized in that, in the above-described invention, the resistance value of the second resistor is higher than the resistance value of the first resistor.

また、この発明にかかる半導体装置は、上述した発明において、前記第１抵抗体として、前記第２抵抗体を用いることを特徴とする。 Further, the semiconductor device according to the present invention is characterized in that the second resistor is used as the first resistor in the above-described invention.

また、この発明にかかる半導体装置は、上述した発明において、前記半導体素子は、前記分離構造を形成するｐｎ接合に沿って配置されている。前記第４半導体領域は、前記半導体基板の一方の主面と平行な方向で、かつ前記分離構造を形成するｐｎ接合のうち、前記半導体素子が配置された部分のｐｎ接合面と直交する方向に、前記第２半導体領域と対向しないことを特徴とする。 Further, in the semiconductor device according to the present invention, in the above-described invention, the semiconductor element is arranged along the pn junction forming the separated structure. The fourth semiconductor region is in a direction parallel to one main surface of the semiconductor substrate and in a direction orthogonal to the pn junction surface of the portion of the pn junction forming the separated structure in which the semiconductor element is arranged. It is characterized in that it does not face the second semiconductor region.

上述した発明によれば、自己分離構造やｐｎ接合分離構造で素子分離した半導体基板であっても、半導体基板内に寄生構造が形成されない。このため、ソースフォロワ構成によるＨＶＮＭＯＳの電流制御効果（ドレイン電流安定化）が安定して得られる。 According to the above-described invention, a parasitic structure is not formed in the semiconductor substrate even if the semiconductor substrate is element-separated by a self-separation structure or a pn junction separation structure. Therefore, the current control effect (drain current stabilization) of the HVNMOS due to the source follower configuration can be stably obtained.

本発明にかかる半導体装置によれば、安定したレベルシフト動作を行うことができるという効果を奏する。 According to the semiconductor device according to the present invention, there is an effect that stable level shift operation can be performed.

実施の形態１にかかる半導体装置の平面レイアウトを示す平面図である。It is a top view which shows the plane layout of the semiconductor device which concerns on Embodiment 1. FIG. 図１の矩形枠Ａにおける断面構造を示す斜視図である。It is a perspective view which shows the cross-sectional structure in the rectangular frame A of FIG. 実施の形態１にかかる半導体装置の変形例の構造を示す斜視図である。It is a perspective view which shows the structure of the modification of the semiconductor device which concerns on Embodiment 1. FIG. 実施の形態１にかかる半導体装置の変形例の構造を示す斜視図である。It is a perspective view which shows the structure of the modification of the semiconductor device which concerns on Embodiment 1. FIG. 実施の形態１にかかる半導体装置の変形例の構造を示す斜視図である。It is a perspective view which shows the structure of the modification of the semiconductor device which concerns on Embodiment 1. FIG. 実施の形態１にかかる半導体装置の変形例の構造を示す斜視図である。It is a perspective view which shows the structure of the modification of the semiconductor device which concerns on Embodiment 1. FIG. 実施の形態１にかかる半導体装置の変形例の構造を示す斜視図である。It is a perspective view which shows the structure of the modification of the semiconductor device which concerns on Embodiment 1. FIG. 実施の形態２にかかる半導体装置の構造を示す斜視図である。It is a perspective view which shows the structure of the semiconductor device which concerns on Embodiment 2. FIG. 実施の形態３にかかる半導体装置の平面レイアウトを示す平面図である。It is a top view which shows the plane layout of the semiconductor device which concerns on Embodiment 3. FIG. 実施の形態４にかかる半導体装置の平面レイアウトを示す平面図である。It is a top view which shows the plane layout of the semiconductor device which concerns on Embodiment 4. FIG. 実施の形態５にかかる半導体装置の平面レイアウトを示す平面図である。It is a top view which shows the plane layout of the semiconductor device which concerns on Embodiment 5. 従来のレベルシフト素子を内蔵したＨＶＩＣの回路構成を示す回路図である。It is a circuit diagram which shows the circuit structure of the HVIC which built in the conventional level shift element. 図５のレベルシフト素子の電圧・電流特性を示す特性図である。It is a characteristic diagram which shows the voltage / current characteristic of the level shift element of FIG. 従来のレベルシフト素子を内蔵したＨＶＩＣの別の一例の回路構成を示す回路図である。It is a circuit diagram which shows the circuit structure of another example of the HVIC which built in the conventional level shift element. 従来の半導体装置の平面レイアウトを示す平面図である。It is a top view which shows the plane layout of the conventional semiconductor device. 図８の矩形枠ＡＡにおける断面構造を示す斜視図である。It is a perspective view which shows the cross-sectional structure in the rectangular frame AA of FIG.

以下に添付図面を参照して、この発明にかかる半導体装置の好適な実施の形態を詳細に説明する。本明細書および添付図面においては、ｎまたはｐを冠記した層や領域では、それぞれ電子または正孔が多数キャリアであることを意味する。また、ｎやｐに付す＋および−は、それぞれそれが付されていない層や領域よりも高不純物濃度および低不純物濃度であることを意味する。なお、以下の実施の形態の説明および添付図面において、同様の構成には同一の符号を付し、重複する説明を省略する。 Hereinafter, preferred embodiments of the semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings. In the present specification and the accompanying drawings, it means that electrons or holes are a large number of carriers in the layers and regions marked with n or p, respectively. Further, + and-attached to n and p mean that the impurity concentration is higher and the impurity concentration is lower than that of the layer or region to which it is not attached, respectively. In the following description of the embodiment and the accompanying drawings, the same reference numerals are given to the same configurations, and duplicate description will be omitted.

（実施の形態１）
実施の形態１にかかる半導体装置の構造について、図１，２Ａ，５を参照して説明する。図１は、実施の形態１にかかる半導体装置の平面レイアウトを示す平面図である。平面レイアウトとは、半導体基板（半導体チップ）１０のおもて面側から見た各部の平面形状および配置構成である。図２Ａは、図１の矩形枠Ａにおける断面構造を示す斜視図である。図２Ａには、図１の高電位側回路部のセット（ｓｅｔ）用のレベルシフト回路を構成するＨＶＮＭＯＳ２１を示す。 (Embodiment 1)
The structure of the semiconductor device according to the first embodiment will be described with reference to FIGS. 1, 2A, and 5. FIG. 1 is a plan view showing a plan layout of the semiconductor device according to the first embodiment. The planar layout is a planar shape and arrangement configuration of each part of the semiconductor substrate (semiconductor chip) 10 as viewed from the front surface side. FIG. 2A is a perspective view showing a cross-sectional structure of the rectangular frame A of FIG. FIG. 2A shows the HVNMOS 21 constituting the level shift circuit for the set of the high potential side circuit unit of FIG.

図１，２Ａに示す実施の形態１にかかる半導体装置は、同一の半導体基板１０上に高電位側領域１１および低電位側領域１２を備え、これらの領域を高耐圧接合終端領域（ＨＶＪＴ）１３で電気的に分離した高耐圧集積回路装置（ＨＶＩＣ）２０である。ＨＶＩＣ２０は、例えば、電力変換用のブリッジ回路１２０の一相分を構成するＩＧＢＴ１２１，１２２のうちの上アーム（高電位側）のＩＧＢＴ１２１を駆動するゲートドライバＩＣである。 The semiconductor device according to the first embodiment shown in FIGS. 1 and 2A includes a high potential side region 11 and a low potential side region 12 on the same semiconductor substrate 10, and these regions are provided as a high withstand voltage junction termination region (HVJT) 13. It is a high withstand voltage integrated circuit device (HVIC) 20 electrically separated by the above. The HVIC 20 is, for example, a gate driver IC that drives the IGBT 121 on the upper arm (high potential side) of the IGBTs 121 and 122 that form one phase of the bridge circuit 120 for power conversion.

実施の形態１にかかる半導体装置を適用した回路構成例は、図５に示す回路構成のＨＶＩＣ１００およびＨＶＮＭＯＳ１０１，１０２に代えて、図１，２ＡのＨＶＩＣ２０およびＨＶＮＭＯＳ２１，２２を適用したものである。すなわち、実施の形態１にかかる半導体装置を適用した例えば電力変換装置は、図５の符号１００〜１０２をそれぞれ符号２０〜２２とした回路構成を有する。ブリッジ回路１２０を構成するスイッチング素子として、ＩＧＢＴ２１，２２に代えて、直列接続された２つのＭＯＳＦＥＴを用いてもよい。 In the circuit configuration example to which the semiconductor device according to the first embodiment is applied, HVIC20 and HVNMOS21,22 of FIGS. 1 and 2A are applied instead of the HVIC100 and HVNMOS101 and 102 of the circuit configuration shown in FIG. That is, for example, the power conversion device to which the semiconductor device according to the first embodiment is applied has a circuit configuration in which reference numerals 100 to 102 in FIG. 5 are designated as reference numerals 20 to 22, respectively. As the switching element constituting the bridge circuit 120, two MOSFETs connected in series may be used instead of the IGBTs 21 and 22.

ｐ--型の半導体基板１０には、ｎ-型拡散領域（第１半導体領域）２およびｐ-型分離領域（第５半導体領域）４がそれぞれ選択的に配置され自己分離構造が形成されている。ｐ-型分離領域４は、ｐ-型拡散領域である。以下、ｐ--型の半導体基板１０の、拡散領域２，４が形成されていない部分をｐ--型基板領域１とする。図２Ａでは、ｐ--型基板領域１を「ｐ--ｓｕｂ」と図示する（図２Ｂ〜２Ｅにおいても同様）。半導体基板１０は、例えば略矩形状の平面形状を有する。ｎ-型拡散領域２は、例えば略矩形状の平面レイアウトに配置されている。 An n- type diffusion region (first semiconductor region) 2 and a p - type separation region (fifth semiconductor region) 4 are selectively arranged on the p- type semiconductor substrate 10 to form a self-separation structure. There is. The p - type separation region 4 is a p - type diffusion region. Hereinafter, the portion of the p - type semiconductor substrate 10 in which the diffusion regions 2 and 4 are not formed is referred to as the p - type substrate region 1. In FIG. 2A, the p - type substrate region 1 is illustrated as "p- sub" (the same applies to FIGS. 2B to 2E). The semiconductor substrate 10 has, for example, a substantially rectangular planar shape. The n - type diffusion region 2 is arranged in a substantially rectangular plane layout, for example.

ｎ-型拡散領域２には、例えば略矩形状の平面レイアウトにｎ型拡散領域３が配置されている。ｐ-型分離領域４は、ｎ-型拡散領域２およびｐ--型基板領域１に接し、かつｎ-型拡散領域２の周囲を囲む環状の平面レイアウトに配置されている。図１には、ｐ-型分離領域４が略矩形状の平面レイアウトでｎ-型拡散領域２の周囲を囲んだ状態を示す。ｎ-型拡散領域２、ｐ-型分離領域４およびｐ--型基板領域１は、ｎ型拡散領域３の周囲を略同心円状に囲む平面レイアウトに配置されている。 In the n - type diffusion region 2, for example, the n-type diffusion region 3 is arranged in a substantially rectangular plane layout. The p - type separation region 4 is arranged in an annular planar layout that is in contact with the n - type diffusion region 2 and the p - type substrate region 1 and surrounds the n-type diffusion region 2. FIG. 1 shows a state in which the p- type separation region 4 surrounds the n- type diffusion region 2 in a substantially rectangular planar layout. The n - type diffusion region 2, the p - type separation region 4, and the p - type substrate region 1 are arranged in a planar layout that substantially concentrically surrounds the n-type diffusion region 3.

以降、半導体基板１０のおもて面（拡散領域２〜４，６側の面）に平行な方向に、ｎ型拡散領域３側を内側（チップ内側）とし、ｎ型拡散領域３側に対して反対側を外側（チップ外側）とする。ｐ--型基板領域１には、ｐ-型分離領域４よりも外側に、例えば略矩形状の平面レイアウトにｎ型拡散領域６が配置されている。ｎ型拡散領域６は、ｐ-型分離領域４に接していてもよい。拡散領域とは、半導体基板１０にイオン注入等により不純物を導入することで形成された領域である。 Hereinafter, the n-type diffusion region 3 side is set to the inside (chip inside) in the direction parallel to the front surface (the surface on the diffusion regions 2 to 4 and 6 sides) of the semiconductor substrate 10, and the n-type diffusion region 3 side The opposite side is the outside (outside of the chip). In the p - type substrate region 1, an n-type diffusion region 6 is arranged outside the p- type separation region 4, for example, in a substantially rectangular plane layout. The n-type diffusion region 6 may be in contact with the p - type separation region 4. The diffusion region is a region formed by introducing impurities into the semiconductor substrate 10 by ion implantation or the like.

図１には、半導体基板１０のおもて面の表面層のｎ-型拡散領域２以外の部分全体にｐ-型分離領域４が配置されていてもよい（すなわち、図１のｐ--型基板領域１の部分をｐ-型分離領域４とした状態）。この場合、ｎ型拡散領域６は、ｐ-型分離領域４の、後述するｐ+型共通電位領域（第４半導体領域）５よりも外側に配置される。ｐ--型基板領域１は、半導体基板１０の裏面の表面層（後述する基板裏面側のｐ型領域１ａ：図２参照）のみとなる。 FIG 1, n of the surface layer of the front surface of the semiconductor substrate 10 - the p entire diffusion region 2 other portions - -type isolation region 4 may be disposed (i.e., in FIG. 1 p - A state in which the portion of the mold substrate region 1 is set as the p - type separation region 4). In this case, n-type diffusion region 6, p - type isolation regions 4 are positioned outside the p + -type common potential region (fourth semiconductor region) 5, which will be described later. The p - type substrate region 1 is only the front surface layer on the back surface of the semiconductor substrate 10 (p-type region 1a on the back surface side of the substrate to be described later: see FIG. 2).

ｐ-型分離領域４に代えて後述するようにｐ--型基板領域１を半導体基板１０のおもて面に露出させてもよいが（図２Ｃ参照）、ｐ-型分離領域４を設けることで正電荷に対する耐性が高くなる。その理由は、ｐ-型分離領域４を配置した部分で半導体基板１０のおもて面側のｐ型不純物濃度が高くなるため、層間絶縁膜に堆積した正電荷の悪影響を受けにくく、半導体基板１０のおもて面側がｎ型に反転しにくくなるからである。 Instead of the p - type separation region 4, the p - type substrate region 1 may be exposed on the front surface of the semiconductor substrate 10 as described later (see FIG. 2C), but the p- type separation region 4 is provided. This increases the resistance to positive charges. The reason is that the concentration of p-type impurities on the front surface side of the semiconductor substrate 10 increases in the portion where the p- type separation region 4 is arranged, so that the positive charge deposited on the interlayer insulating film is less likely to be adversely affected, and the semiconductor substrate is not affected. This is because the front surface side of 10 is less likely to be inverted into an n-type.

高電位側領域１１は、その周囲をＨＶＪＴ１３で囲まれており、高電位側の補助直流電源Ｅ１の正極ラインの電位（以下、高電位側電源電位とする：ＨＶＩＣ２０の最高電位）Ｖｃｃ１や高電位側回路部１１０の基準電位ＶＳが数百Ｖの高電位になったとしても（図５参照）、ＨＶＪＴ１３により低電位側領域１２と電気的に分離される。高電位側回路部１１０の基準電位ＶＳは、上アームのＩＧＢＴ１２１と下アームのＩＧＢＴ１２２との接続点１２３の電位である。高電位側領域１１は、ｎ型拡散領域３で構成される。 The high potential side region 11 is surrounded by HVJT13, and the potential of the positive potential line of the auxiliary DC power supply E1 on the high potential side (hereinafter referred to as the high potential side power supply potential: the highest potential of the HVIC 20) Vcc1 and the high potential. Even if the reference potential VS of the side circuit unit 110 becomes a high potential of several hundred V (see FIG. 5), it is electrically separated from the low potential side region 12 by the HVJT 13. The reference potential VS of the high potential side circuit unit 110 is the potential of the connection point 123 between the IGBT 121 of the upper arm and the IGBT 122 of the lower arm. The high potential side region 11 is composed of an n-type diffusion region 3.

ｎ型拡散領域３は、高電位側電源電位Ｖｃｃ１に電気的に接続されている。ｎ型拡散領域３には、例えば高電位側回路部１１０が配置される。高電位側回路部１１０は、高電位側電源電位Ｖｃｃ１を電源電位とし、基準電位ＶＳで動作し、低電位側回路部１１５からの信号に基づいてブリッジ回路１２０の交流出力端子ＯＵＴから出力される信号を生成する例えばＣＭＯＳ（Ｃｏｍｐｌｅｍｅｎｔａｒｙ ＭＯＳ：相補型ＭＯＳ）回路である。 The n-type diffusion region 3 is electrically connected to the high potential side power supply potential Vcc1. For example, the high potential side circuit unit 110 is arranged in the n-type diffusion region 3. The high potential side circuit unit 110 operates at the reference potential VS with the high potential side power supply potential Vcc1 as the power supply potential, and is output from the AC output terminal OUT of the bridge circuit 120 based on the signal from the low potential side circuit unit 115. For example, a CMOS (Complementary MOS) circuit that generates a signal.

ＨＶＪＴ１３は、ｐ-型分離領域４とｎ-型拡散領域２とのｐｎ接合で形成される寄生ダイオードで構成される耐圧領域である。ｎ-型拡散領域２には、ＨＶＩＣ２０の高電位側回路部のセット用およびリセット（ｒｅｓｅｔ）用のレベルシフト回路を構成するＨＶＮＭＯＳ２１，２２が配置されている。ＨＶＮＭＯＳ２１，２２は、共通電位ＣＯＭを基準とした信号をブリッジ回路１２０の電源電位Ｖｄｃを基準とした信号に変換するレベルシフト素子である。共通電位ＣＯＭは、ブリッジ回路１２０の主直流電源およびＨＶＩＣ２０の補助直流電源Ｅ１，Ｅ２の負極側の電位であり、例えば接地電位であってもよい。ＨＶＮＭＯＳ２１，２２は、例えば高電位側領域１１を中心として点対称に配置されることが好ましい。 The HVJT 13 is a withstand voltage region composed of a parasitic diode formed by a pn junction between the p- type separation region 4 and the n -type diffusion region 2. In the n - type diffusion region 2, HVNMOS21, 22 constituting a level shift circuit for setting and resetting the high potential side circuit portion of the HVIC 20 is arranged. The HVNMOS 21 and 22 are level shift elements that convert a signal based on the common potential COM into a signal based on the power supply potential Vdc of the bridge circuit 120. The common potential COM is the potential on the negative electrode side of the main DC power supply of the bridge circuit 120 and the auxiliary DC power supplies E1 and E2 of the HVIC 20, and may be, for example, a ground potential. The HVNMOS 21 and 22 are preferably arranged point-symmetrically with the high potential side region 11 as the center, for example.

ｐ-型分離領域４の内部には、ｎ-型拡散領域２と離して、ｐ+型コンタクト領域（以下、ｐ+型共通電位領域とする）５が選択的に配置されている。ｐ+型共通電位領域５は、ｐ-型分離領域４を共通電位ＣＯＭに固定する。ｐ+型共通電位領域５は、内側から外側へ向かう方向（ｐ-型分離領域４の径方向Ｄ）にＨＶＮＭＯＳ２１，２２に対向しない位置に配置される。 Inside the p - type separation region 4 , a p + type contact region (hereinafter referred to as a p + type common potential region) 5 is selectively arranged apart from the n- type diffusion region 2. The p + type common potential region 5 fixes the p- type separation region 4 to the common potential COM. The p + type common potential region 5 is arranged at a position not facing the HVNMOS 21 and 22 in the direction from the inside to the outside ( diameter direction D of the p-type separation region 4).

また、ｐ+型共通電位領域５は、ＨＶＮＭＯＳ２１，２２の後述するｐ型バックゲート領域３１およびソースコンタクト領域３６との間で所定の抵抗値の拡散抵抗（抵抗体）Ｒ’が得られる距離Ｘ１で当該ｐ型バックゲート領域３１およびソースコンタクト領域３６と離して配置されている。 Further, the p + type common potential region 5 is a distance X1 at which a diffusion resistance (resistor) R'with a predetermined resistance value can be obtained between the p-type back gate region 31 and the source contact region 36 described later of the HVNMOS 21 and 22. It is arranged apart from the p-type back gate region 31 and the source contact region 36.

例えば、ＨＶＮＭＯＳ２１，２２が、略矩形状のｐ-型分離領域４の１組の対辺４ａ，４ｂにそれぞれ対向する位置に配置されているとする。この場合、ｐ+型共通電位領域５は、ｐ-型分離領域４の他の１組の対辺４ｃ，４ｄに、ｐ-型分離領域４の周方向Ｒに沿って配置される。ｐ+型共通電位領域５は、ｐ-型分離領域４の当該１組の対辺４ｃ，４ｄからもう１組の対辺４ａ，４ｂに延在する略Ｕ字状または略Ｃ字状の平面レイアウトに配置されてもよい。 For example, it is assumed that the HVNMOS 21 and 22 are arranged at positions facing each other of a set of opposite sides 4a and 4b of a substantially rectangular p-type separation region 4. In this case, the p + type common potential region 5 is arranged along the circumferential direction R of the p- type separation region 4 on the other pair of opposite sides 4c and 4d of the p -type separation region 4. The p + type common potential region 5 has a substantially U-shaped or substantially C-shaped planar layout extending from the pair of opposite sides 4c and 4d of the p-type separation region 4 to the other pair of opposite sides 4a and 4b. It may be arranged.

低電位側領域１２は、ｎ型拡散領域６で構成される。ｎ型拡散領域６は、低電位側回路部１１５の最高電位（低電圧側の補助直流電源Ｅ２の正極ラインの電位Ｖｃｃ２：図５参照）に電気的に接続されている。低電位側領域１２には、図示省略する内部回路（低電位側回路部１１５）などが配置される。低電位側回路部１１５は、例えば、共通電位ＣＯＭを基準電位として動作し、ＨＶＮＭＯＳ２１，２２を駆動するＣＭＯＳ回路である。 The low potential side region 12 is composed of an n-type diffusion region 6. The n-type diffusion region 6 is electrically connected to the maximum potential of the low potential side circuit unit 115 (potential Vcc2 of the positive electrode line of the auxiliary DC power supply E2 on the low voltage side: see FIG. 5). An internal circuit (low potential side circuit unit 115) or the like (not shown) is arranged in the low potential side region 12. The low potential side circuit unit 115 is, for example, a CMOS circuit that operates with the common potential COM as a reference potential and drives the HVNMOS 21 and 22.

次に、セット用およびリセット用のレベルシフト回路を構成するＨＶＮＭＯＳ２１，２２の構成について、図２Ａを参照して説明する。図２Ａには、略矩形状の平面レイアウトを有するｐ-型分離領域４の４辺４ａ〜４ｄのうちの１辺４ａの一部（ＨＶＮＭＯＳ２１が配置された部分：図１の矩形枠Ａ）を示す。 Next, the configurations of the HVNMOS 21 and 22 constituting the set and reset level shift circuits will be described with reference to FIG. 2A. In FIG. 2A, a part of one side 4a of the four sides 4a to 4d of the p- type separation region 4 having a substantially rectangular plane layout (the part where the HVNMOS 21 is arranged: the rectangular frame A in FIG. 1) is shown. Shown.

ＨＶＮＭＯＳ２１のソース・ドレイン間には、ＨＶＮＭＯＳ２１のオン時に例えば１０Ｖ程度の電圧が印加される。ＨＶＮＭＯＳ２２のソース・ドレイン間には、ＨＶＮＭＯＳ２２のオン時に例えば最大６００Ｖ程度の電圧が印加される。ここでは、ＨＶＮＭＯＳ２１の構成について説明するが、ＨＶＮＭＯＳ２２の構成はＨＶＮＭＯＳ２１と同様である。 A voltage of, for example, about 10 V is applied between the source and drain of the HVNMOS 21 when the HVNMOS 21 is turned on. A voltage of, for example, about 600 V at maximum is applied between the source and drain of the HVNMOS 22 when the HVNMOS 22 is turned on. Here, the configuration of the HVNMOS 21 will be described, but the configuration of the HVNMOS 22 is the same as that of the HV NMOS 21.

ＨＶＮＭＯＳ２１は、バックゲートとなるｐ型拡散領域（ｐ型バックゲート領域：第６半導体領域）３１、ｎ+型ソース領域（第２半導体領域）３２、ｐ+型コンタクト領域３３、ｎ+型ドレイン領域（第３半導体領域）３４およびゲート電極３５を備えた高耐圧（例えば６００Ｖ以上）の横型のｎチャネル型ＭＯＳＦＥＴである。ｐ型バックゲート領域３１およびｎ+型ドレイン領域３４は、ｎ-型拡散領域２の、基板おもて面側の表面層にそれぞれ選択的に設けられている。 The HVNMOS21 has a p-type diffusion region (p-type backgate region: sixth semiconductor region) 31, an n + type source region (second semiconductor region) 32, a p + type contact region 33, and an n + type drain region that serve as a back gate. It is a horizontal n-channel MOSFET having a high withstand voltage (for example, 600 V or more) and having a (third semiconductor region) 34 and a gate electrode 35. The p-type back gate region 31 and the n + -type drain region 34 are selectively provided on the surface layer of the n- type diffusion region 2 on the front surface side of the substrate.

ｐ型バックゲート領域３１は、ｎ型拡散領域３（すなわち高電位側領域１１：図１参照）の周囲を囲む環状の平面レイアウトに配置されていてもよい。ｐ型バックゲート領域３１をｎ型拡散領域３の周囲を囲む環状の平面レイアウトに配置した場合、ｐ型バックゲート領域３１およびｐ-型分離領域４とｎ-型拡散領域２とのｐｎ接合で寄生ダイオードが形成され、当該寄生ダイオードでＨＶＪＴ１３が構成される。 The p-type backgate region 31 may be arranged in an annular planar layout surrounding the n-type diffusion region 3 (that is, the high potential side region 11: see FIG. 1). When the p-type backgate region 31 is arranged in an annular planar layout surrounding the n-type diffusion region 3, the p-type backgate region 31 and the p - type separation region 4 and the n - type diffusion region 2 are pn-junctioned. A parasitic diode is formed, and the HVJT 13 is composed of the parasitic diode.

また、ｐ型バックゲート領域３１は、基板裏面側のｐ型領域１ａに達していてもよい。基板裏面側のｐ型領域１ａとは、半導体基板１０のおもて面から拡散領域２，４，６よりも深さ方向Ｚに深い部分に、これらの領域が形成されないことでｐ--型基板領域１として残っている部分（半導体基板１０の裏面の表面層）である。深さ方向Ｚとは、半導体基板１０のおもて面から裏面に向かう方向である。 Further, the p-type back gate region 31 may reach the p-type region 1a on the back surface side of the substrate. The p-type region 1a of the substrate backside, p by a deep portion in the depth direction Z than the diffusion regions 2, 4, 6 from the front surface of the semiconductor substrate 10, these regions are not formed - -type The portion remaining as the substrate region 1 (the surface layer on the back surface of the semiconductor substrate 10). The depth direction Z is a direction from the front surface to the back surface of the semiconductor substrate 10.

基板裏面側のｐ型領域１ａの比抵抗は、ＨＶＮＭＯＳ２１のオン時に、基板裏面側のｐ型領域１ａとｎ-型拡散領域２とのｐｎ接合から伸びる空乏層を、基板裏面側のｐ型領域１ａに深く広げることができる程度に高くする。すなわち、基板裏面側のｐ型領域１ａ側に伸びる空乏層の体積を増やしてＨＶＮＭＯＳ２１の耐圧（耐電圧）を確保する。耐圧とは、素子が誤動作や破壊を起こさない限界の電圧である。基板裏面側のｐ型領域１ａの比抵抗は、例えば１００Ωｃｍ程度であってもよい。 The resistivity of the p-type region 1a on the back surface side of the substrate is the depletion layer extending from the pn junction between the p-type region 1a on the back surface side of the substrate and the n -type diffusion region 2 when the HVNMOS21 is turned on, and the p-type region on the back surface side of the substrate. Make it high enough to spread deeply into 1a. That is, the volume of the depletion layer extending toward the p-type region 1a on the back surface side of the substrate is increased to secure the withstand voltage (withstand voltage) of the HVNMOS 21. The withstand voltage is the limit voltage at which the element does not malfunction or break. The specific resistance of the p-type region 1a on the back surface side of the substrate may be, for example, about 100 Ωcm.

ｎ+型ドレイン領域３４は、ｐ型バックゲート領域３１よりも内側に、ｐ型バックゲート領域３１と離して配置されている。ｎ+型ソース領域３２およびｐ+型コンタクト領域３３は、ｐ型バックゲート領域３１の内部にそれぞれ選択的に設けられ、互いに接する。ｎ+型ソース領域３２とｐ型バックゲート領域３１とは、ｐ+型コンタクト領域３３を介して短絡されている。 The n + type drain region 34 is arranged inside the p-type back gate region 31 and away from the p-type back gate region 31. The n + type source region 32 and the p + type contact region 33 are selectively provided inside the p-type back gate region 31 and are in contact with each other. The n + type source region 32 and the p-type back gate region 31 are short-circuited via the p + type contact region 33.

ｎ+型ソース領域３２とｐ型バックゲート領域３１とが短絡されていることで、基板おもて面に平行な方向に基板おもて面に沿って形成されるｎ+型ソース領域３２、ｐ型バックゲート領域３１およびｎ-型拡散領域２からなるｎｐｎ寄生バイポーラトランジスタ（以下、横方向のｎｐｎ寄生バイポーラトランジスタとする）が動作することが抑制される。このため、当該横方向のｎｐｎ寄生バイポーラトランジスタによる素子破壊が生じることを防止することができる。 By short-circuiting the n + type source region 32 and the p-type backgate region 31, the n + type source region 32 is formed along the substrate front surface in a direction parallel to the substrate front surface. The operation of an npn parasitic bipolar transistor (hereinafter referred to as a lateral npn parasitic bipolar transistor) composed of a p-type backgate region 31 and an n -type diffusion region 2 is suppressed. Therefore, it is possible to prevent the element from being destroyed by the npn parasitic bipolar transistor in the lateral direction.

ｎ+型ソース領域３２およびｐ+型コンタクト領域３３は、例えばｐ-型分離領域４の周方向Ｒに交互に繰り返し配置されていてもよい。以下、ｐ-型分離領域４の周方向Ｒに交互に繰り返し配置された１組以上のｎ+型ソース領域３２およびｐ+型コンタクト領域３３をまとめてソースコンタクト領域３６とする。ソースコンタクト領域３６の端部３６ａ，３６ｂは、ｎ+型ソース領域３２およびｐ+型コンタクト領域３３のいずれであってもよい。 The n + type source region 32 and the p + type contact region 33 may be alternately and repeatedly arranged, for example, in the circumferential direction R of the p − type separation region 4. Hereinafter, one or more sets of n + type source regions 32 and p + type contact regions 33 alternately and repeatedly arranged in the circumferential direction R of the p- type separation region 4 are collectively referred to as a source contact region 36. The ends 36a and 36b of the source contact region 36 may be either the n + type source region 32 or the p + type contact region 33.

ソースコンタクト領域３６は、抵抗体（ソースフォロワ抵抗）ＲSFを介して共通電位ＣＯＭの電極パッド（ＣＯＭ電極パッド）４１に電気的に接続されている。すなわち、ＨＶＮＭＯＳ２１はソースフォロワ構成となっている。ソースフォロワ抵抗ＲSFは、図５の電流帰還抵抗１１１に相当する。ソースフォロワ抵抗ＲSFは、ＨＶＮＭＯＳ２１のオン時に電圧降下して、ＨＶＮＭＯＳ２１のドレイン電流を小さくする機能を有する。 Source contact region 36, resistor is electrically connected to (source follower resistance) through the R SF common potential COM of the electrode pads (COM electrode pad) 41. That is, the HVNMOS 21 has a source follower configuration. Source follower resistor R SF corresponds to a current feedback resistor 111 of FIG. Source follower resistor R SF is to drop during on of HVNMOS21, has a function to reduce the drain current of HVNMOS21.

ソースフォロワ抵抗ＲSFは、例えば、半導体基板１０のおもて面上に絶縁層（不図示）を介して設けられたポリシリコン（ｐｏｌｙ−Ｓｉ）層などの抵抗素子で構成される。ソースフォロワ抵抗ＲSFをポリシリコン層で構成する場合、例えば、ソースフォロワ抵抗ＲSFと半導体基板１０とを絶縁する絶縁層のコンタクトホールを介して、当該ポリシリコン層一方の端部がソースコンタクト領域３６に接続され、他方の端部がＣＯＭ電極パッド４１に接続される。ソースフォロワ抵抗ＲSFの抵抗値は、例えば１ｋΩ程度であってもよい。 Source follower resistor R SF is composed of, for example, a resistance element such as polysilicon (poly-Si) layer that is provided via an insulating layer on the front surface of the semiconductor substrate 10 (not shown). When configuring the source follower resistor R SF polysilicon layer, for example, via the contact hole of the insulating layer for insulating the source follower resistor R SF and the semiconductor substrate 10, the polysilicon layer one end a source contact region It is connected to 36 and the other end is connected to the COM electrode pad 41. Resistance value of the source follower resistor R SF may be, for example 1kΩ about.

ｎ-型拡散領域２の、ｐ型バックゲート領域３１とｎ+型ドレイン領域３４とに挟まれた部分がＨＶＮＭＯＳ２１のｎ-型ドリフト領域として機能する。ｐ型バックゲート領域３１の、ｎ-型ドリフト領域とｎ+型ソース領域３２とに挟まれた部分の表面上には、ゲート絶縁膜（不図示）を介してゲート電極３５が設けられている。ｎ+型ドレイン領域３４は、ドレイン電極（不図示）に電気的に接続されている。 The portion of the n - type diffusion region 2 sandwiched between the p-type backgate region 31 and the n + -type drain region 34 functions as the n- type drift region of the HVNMOS 21. A gate electrode 35 is provided on the surface of the p-type back gate region 31 between the n - type drift region and the n + -type source region 32 via a gate insulating film (not shown). .. The n + type drain region 34 is electrically connected to a drain electrode (not shown).

ｐ-型分離領域４は、ＨＶＮＭＯＳ２１のｐ型バックゲート領域３１よりも外側に配置されている。ｐ-型分離領域４は、ＨＶＮＭＯＳ２１のｐ型バックゲート領域３１、ｎ+型ソース領域３２およびｐ+型コンタクト領域３３に接し、これらの領域に電気的に接続されている。また、ｐ-型分離領域４は、ｐ--型基板領域１に接し、ｐ--型基板領域１に電気的に接続されている。ｐ-型分離領域４の内部には、ｐ+型共通電位領域５が選択的に設けられている。 The p - type separation region 4 is arranged outside the p-type back gate region 31 of the HVNMOS 21. The p - type separation region 4 is in contact with the p-type backgate region 31, the n + type source region 32, and the p + type contact region 33 of the HVNMOS 21, and is electrically connected to these regions. Further, the p - type separation region 4 is in contact with the p - type substrate region 1 and is electrically connected to the p- type substrate region 1. A p + type common potential region 5 is selectively provided inside the p- type separation region 4.

ｐ+型共通電位領域５は、ＨＶＪＴ１３に形成される寄生ダイオードのアノードコンタクト領域として機能する。ｐ+型共通電位領域５は、ｐ-型分離領域４の径方向ＤにＨＶＮＭＯＳ２１のｎ+型ソース領域３２およびｐ+型コンタクト領域３３に対向する位置には配置されていない。ｐ+型共通電位領域５は、ＣＯＭ電極パッド４１に電気的に接続され、ｐ-型分離領域４およびｐ--型基板領域１を共通電位ＣＯＭに固定する。 The p + type common potential region 5 functions as an anode contact region of the parasitic diode formed in the HVJT 13. The p + type common potential region 5 is not arranged at a position facing the n + type source region 32 and the p + type contact region 33 of the HVNMOS 21 in the radial direction D of the p − type separation region 4. The p + type common potential region 5 is electrically connected to the COM electrode pad 41, and the p − type separation region 4 and the p − type substrate region 1 are fixed to the common potential COM.

また、ｐ+型共通電位領域５は、ＨＶＮＭＯＳ２１のｐ型バックゲート領域３１およびソースコンタクト領域３６との間に挟まれた部分で所定の抵抗値の拡散抵抗Ｒ’が得られるように、所定の距離Ｘ１で当該ｐ型バックゲート領域３１およびソースコンタクト領域３６と離して配置される。すなわち、ｐ+型共通電位領域５とＨＶＮＭＯＳ２１のｐ型バックゲート領域３１およびソースコンタクト領域３６とは、ｐ+型共通電位領域５とＨＶＮＭＯＳ２１のｐ型バックゲート領域３１およびソースコンタクト領域３６との間の拡散抵抗Ｒ’（または後述する基板抵抗：図２Ｃ，２Ｄ参照）を介して電気的に接続されている。 Further, the p + type common potential region 5 is predetermined so that a diffusion resistance R'with a predetermined resistance value can be obtained at a portion sandwiched between the p-type back gate region 31 and the source contact region 36 of the HVNMOS 21. It is arranged at a distance X1 away from the p-type backgate region 31 and the source contact region 36. That is, the p + type common potential region 5 and the p-type backgate region 31 and the source contact region 36 of the HVNMOS 21 are between the p + type common potential region 5 and the p-type backgate region 31 and the source contact region 36 of the HVNMOS 21. It is electrically connected via the diffusion resistor R'(or the substrate resistor described later: see FIGS. 2C and 2D).

ｐ+型共通電位領域５とＨＶＮＭＯＳ２１のｐ型バックゲート領域３１およびソースコンタクト領域３６とを上記拡散抵抗Ｒ’ （または基板抵抗）を介して接続することで、ｐ型バックゲート領域３１とｐ--型基板領域１（基板裏面側のｐ型領域１ａ）との間に電位差が生じる。このため、ＨＶＮＭＯＳ２１のソース電位と、共通電位ＣＯＭと、を電気的に分離することができる。ｐ型バックゲート領域３１とｐ--型基板領域１との間の電位差は、ソースコンタクト領域３６の両端部３６ａ，３６ｂに形成される各拡散抵抗Ｒ’の合成抵抗で調整される。 a p + -type common potential region 5 and p-type back gate region 31 and the source contact region 36 of HVNMOS21 By connecting via the diffusion resistance R '(or substrate resistance), p-type back gate region 31 and p - - potential difference between the mold substrate region 1 (p-type region 1a of the substrate rear surface side) occurs. Therefore, the source potential of the HVNMOS 21 and the common potential COM can be electrically separated. The potential difference between the p-type backgate region 31 and the p - type substrate region 1 is adjusted by the combined resistance of each diffusion resistor R'formed at both ends 36a and 36b of the source contact region 36.

また、ｐ型バックゲート領域３１はｐ-型分離領域４を介してｐ--型基板領域１に短絡（または後述するようにｐ--型基板領域１に直接短絡：図２Ｃ，２Ｄ参照）しているため、半導体基板１０内に寄生構造が形成されない。このため、ＨＶＮＭＯＳ２１のｎ+型ソース領域３２と共通電位ＣＯＭとの間のインピーダンスが極端に低くなることを防止することができる。したがって、ソースフォロワ構成によるＨＶＮＭＯＳ２１の電流制御効果（ドレイン電流安定化）が安定して得られる。 Further, p-type back gate region 31 is p - type isolation region 4 via the p - short circuit -type substrate region 1 (or, as described below p - type substrate region 1 to direct short: Figure 2C, see 2D) Therefore, no parasitic structure is formed in the semiconductor substrate 10. Therefore, it is possible to prevent the impedance between the n + type source region 32 of the HVNMOS 21 and the common potential COM from becoming extremely low. Therefore, the current control effect (drain current stabilization) of the HVNMOS 21 due to the source follower configuration can be stably obtained.

拡散抵抗Ｒ’およびソースフォロワ抵抗ＲSFは、ＣＯＭ電極パッド４１とＨＶＮＭＯＳ２１のソースコンタクト領域３６との間に並列に接続されている。この場合、ＨＶＮＭＯＳ２１，２２のドレイン電流の安定化と（ソースフォロワ抵抗ＲSFで実現）と、寄生動作の防止（拡散抵抗Ｒ’で実現）と、をそれぞれ異なる抵抗体で実現することができる。したがって、ソースフォロワ抵抗ＲSFの抵抗値のばらつきや、ノイズ（変位電流）によるソースフォロワ抵抗ＲSFの抵抗値変動を小さくすることができる。 Diffusion resistance R 'and the source follower resistor R SF are connected in parallel between the source contact region 36 of the COM electrode pads 41 and HVNMOS21. In this case, the stabilization of the drain current of HVNMOS21,22 and (implemented in the source-follower resistor R SF), and prevention of parasitic action (achieved by diffusion resistance R '), can be realized in different resistor. Therefore, it is possible to reduce or variation in resistance of the source follower resistor R SF, noise resistance value variation of the source follower resistor R SF by (displacement current).

また、拡散抵抗Ｒ’とソースフォロワ抵抗ＲSFとを並列に接続する場合、拡散抵抗Ｒ’は、ソースフォロワ抵抗ＲSFよりも抵抗値を高くし、数十ｋΩ（例えば１ｋΩ〜１０ｋΩ）程度に高抵抗化する。具体的には、例えば、ｐ+型共通電位領域５と、ソースコンタクト領域３６のｐ-型分離領域４の周方向Ｒにおける端部３６ａ，３６ｂと、の最短距離Ｘ１は、例えば５μｍ以上１００μｍ以下程度とする。かつｐ-型分離領域４の不純物濃度は、例えば１×１０13／ｃｍ3程度とすればよい。 When the diffusion resistor R'and the source follower resistor R SF are connected in parallel, the diffusion resistor R'has a higher resistance value than the source follower resistor R SF , and is about several tens of kΩ (for example, 1 kΩ to 10 kΩ). Increase resistance. Specifically, for example , the shortest distance X1 between the p + type common potential region 5 and the ends 36a and 36b in the circumferential direction R of the p- type separation region 4 of the source contact region 36 is, for example, 5 μm or more and 100 μm or less. Degree. Moreover, the impurity concentration in the p- type separation region 4 may be, for example, about 1 × 10 13 / cm 3 .

また、ｐ型バックゲート領域３１をｎ型拡散領域３の周囲を囲む環状の平面レイアウトに配置した場合、拡散抵抗Ｒ’は、ｐ-型分離領域４およびｐ型バックゲート領域３１の合成抵抗となる。また、ソースフォロワ抵抗ＲSFを設けずに、拡散抵抗Ｒ’自体をソースフォロワ抵抗として用いてもよい。この場合、拡散抵抗Ｒ’は、ゲート・ソース間への印加電圧（例えば５Ｖ程度）からＨＶＮＭＯＳ２１のゲート閾値電圧を減算した電圧値（＝３Ｖ〜４Ｖ程度）以下の電圧降下を生じさせる抵抗値とすることが好ましい。 Further, when the p-type backgate region 31 is arranged in an annular planar layout surrounding the n-type diffusion region 3, the diffusion resistance R'is the combined resistance of the p- type separation region 4 and the p-type backgate region 31. Become. Also, without providing the source follower resistor R SF, it may be used diffusion resistance R 'itself as a source follower resistance. In this case, the diffusion resistance R'is a resistance value that causes a voltage drop equal to or less than the voltage value (= about 3V to 4V) obtained by subtracting the gate threshold voltage of the HVNMOS 21 from the voltage applied between the gate and the source (for example, about 5V). It is preferable to do so.

次に、ＨＶＮＭＯＳ２１の変形例について説明する。図２Ｂ〜２Ｆは、実施の形態１にかかる半導体装置の変形例の構造を示す斜視図である。図２Ｂ〜２Ｆには、図１の矩形枠Ａにおける断面構造を示す。図２Ｂ〜２Ｆに示すＨＶＮＭＯＳ２１が図２Ａに示すＨＶＮＭＯＳ２１と異なる点は、次の通りである。 Next, a modified example of the HVNMOS 21 will be described. 2B to 2F are perspective views showing the structure of a modified example of the semiconductor device according to the first embodiment. 2B to 2F show the cross-sectional structure of the rectangular frame A of FIG. The differences between the HVNMOS 21 shown in FIGS. 2B to 2F and the HVNMOS 21 shown in FIG. 2A are as follows.

図２Ｂに示すように、ＨＶＮＭＯＳ２１のｐ型バックゲート領域として、ｐ-型分離領域４を用いてもよい。この場合、ｐ-型分離領域４に、ＨＶＮＭＯＳ２１のｎ+型ソース領域３２およびｐ+型コンタクト領域３３が配置される。ＨＶＮＭＯＳ２１の一部をｐ-型分離領域４に配置する分だけ、図２Ａの場合よりもｐ-型分離領域４の幅を広くしてもよい。ゲート電極３５は、ｐ-型分離領域４の、ｎ-型ドリフト領域とｎ+型ソース領域３２とに挟まれた部分の表面上にゲート絶縁膜（不図示）を介して設けられる。 As shown in FIG. 2B, the p- type separation region 4 may be used as the p-type backgate region of the HVNMOS 21. In this case, the n + type source region 32 and the p + type contact region 33 of the HVNMOS 21 are arranged in the p- type separation region 4. The width of the p- type separation region 4 may be wider than that in the case of FIG. 2A by the amount that a part of the HVNMOS 21 is arranged in the p- type separation region 4. The gate electrode 35 is provided on the surface of the portion of the p- type separation region 4 sandwiched between the n- type drift region and the n + type source region 32 via a gate insulating film (not shown).

また、図２Ｃに示すように、ｎ-型拡散領域２とｎ型拡散領域６（図１参照）との間に基板裏面側のｐ型領域１ａから基板おもて面に露出するようにスリット状に残したｐ--型基板領域１で、ｐ-型分離領域を構成してもよい。この場合、ｐ--型基板領域１とｎ-型拡散領域２とのｐｎ接合で形成される寄生ダイオードでＨＶＪＴ１３が構成される。ＨＶＮＭＯＳ２１のｐ型バックゲート領域３１は、ｐ--型基板領域１とｎ-型拡散領域２との境界に跨って設けられる。ｐ+型共通電位領域５は、基板おもて面に露出するようにスリット状に残るｐ--型基板領域１に図２Ａと同様の構成で配置される。 Further, as shown in FIG. 2C, a slit is formed between the n- type diffusion region 2 and the n-type diffusion region 6 (see FIG. 1) so as to be exposed from the p-type region 1a on the back surface side of the substrate to the front surface of the substrate. The p- type substrate region 1 left in the shape may form a p- type separation region. In this case, the HVJT 13 is composed of a parasitic diode formed by a pn junction between the p- type substrate region 1 and the n -type diffusion region 2. The p-type backgate region 31 of the HVNMOS 21 is provided across the boundary between the p- type substrate region 1 and the n -type diffusion region 2. The p + type common potential region 5 is arranged in the p-- type substrate region 1 which remains in a slit shape so as to be exposed on the front surface of the substrate in the same configuration as in FIG. 2A.

また、図２Ｃに示すＨＶＮＭＯＳ２１に図２Ｂに示すＨＶＮＭＯＳ２１を適用してもよい（図２Ｄ参照）。すなわち、基板おもて面に露出するようにスリット状に残るｐ--型基板領域１で構成したｐ-型分離領域（図２Ｃ参照）を、ＨＶＮＭＯＳ２１のｐ型バックゲート領域として用いてもよい。この場合、基板おもて面に露出するようにスリット状に残るｐ--型基板領域１に、ＨＶＮＭＯＳ２１のｎ+型ソース領域３２およびｐ+型コンタクト領域３３が配置される。ゲート電極３５は、ｐ--型基板領域１の、ｎ-型ドリフト領域とｎ+型ソース領域３２とに挟まれた部分の表面上にゲート絶縁膜（不図示）を介して設けられる。 Further, the HVNMOS21 shown in FIG. 2B may be applied to the HVNMOS21 shown in FIG. 2C (see FIG. 2D). That is, the p- type separation region (see FIG. 2C) composed of the p- type substrate region 1 that remains in a slit shape so as to be exposed on the front surface of the substrate may be used as the p-type backgate region of the HVNMOS21. .. In this case, the n + -type source region 32 and the p + -type contact region 33 of the HVNMOS 21 are arranged in the p- type substrate region 1 that remains in a slit shape so as to be exposed on the front surface of the substrate. The gate electrode 35 is provided on the surface of the portion of the p- type substrate region 1 sandwiched between the n- type drift region and the n + -type source region 32 via a gate insulating film (not shown).

図２Ｃ，２Ｄのようにｐ-型分離領域をｐ--型基板領域１で構成する場合、ｐ+型共通電位領域５とＨＶＮＭＯＳ２１のソースコンタクト領域３６との間におけるｐ--型基板領域１の基板抵抗により、寄生動作を防止する効果が得られる。 When configuring a type substrate region 1, p between the source contact region 36 of the p + -type common potential region 5 and HVNMOS21 - - -type isolation region p - Figure 2C, p as 2D -type substrate region 1 The effect of preventing parasitic operation can be obtained by the substrate resistance of.

また、図２Ｅに示すように、ｎ-型拡散領域２に代えて、ｎ-型エピタキシャル層５２を設けてもよい。この場合、例えば、ｐ--型支持基板５１上にｎ-型エピタキシャル層５２をエピタキシャル成長させたエピタキシャル基板５０が用いられる。図２Ｅには、ｐ--型支持基板５１を「ｐ--ｓｕｂ」と図示し、ｎ-型エピタキシャル層５２を「ｎ-エピ」と図示する。このエピタキシャル基板５０に、ｎ-型エピタキシャル層５２を深さ方向Ｚに貫通してｐ--型支持基板５１に達するｐ-型分離領域４が略環状の平面レイアウトに配置される。ｎ-型エピタキシャル層５２の、ｐ-型分離領域４よりも内側に、高電位側領域１１を構成するｎ型拡散領域（不図示：図１の符号３）が配置される。ｎ-型エピタキシャル層５２の、ｐ-型分離領域４よりも外側の部分で低電位側領域１２が構成される。ｎ-型エピタキシャル層５２には、図２Ａと同様の構成でＨＶＮＭＯＳ２１の各部が配置される。 Further, as shown in FIG. 2E, an n- type epitaxial layer 52 may be provided instead of the n- type diffusion region 2. In this case, for example, an epitaxial substrate 50 in which an n- type epitaxial layer 52 is epitaxially grown on a p- type support substrate 51 is used. In FIG. 2E, the p - type support substrate 51 is shown as "p- sub", and the n - type epitaxial layer 52 is shown as "n- epi". This epitaxial substrate 50, n - through the type epitaxial layer 52 in the depth direction Z p - p reaches the mold supporting substrate 51 - -type isolation region 4 is arranged substantially annular planar layout. An n-type diffusion region (not shown: reference numeral 3 in FIG. 1) constituting the high potential side region 11 is arranged inside the p- type separation region 4 of the n - type epitaxial layer 52. The low potential side region 12 is formed in a portion of the n- type epitaxial layer 52 outside the p-type separation region 4. Each part of the HVNMOS 21 is arranged on the n - type epitaxial layer 52 in the same configuration as in FIG. 2A.

また、図２Ｆに示すように、ｐ-型分離領域４に代えて、ｐ-型エピタキシャル層５３を設けてもよい。図２Ｆには、ｐ-型エピタキシャル層５３を「ｐ-エピ」と図示する。この場合、例えば、ｐ--型支持基板５１上にｐ-型エピタキシャル層５３をエピタキシャル成長させたエピタキシャル基板５０が用いられる。このエピタキシャル基板５０に、ｐ-型エピタキシャル層５３を深さ方向Ｚに貫通してｐ--型支持基板５１に達するｎ-型拡散領域２が略矩形状の平面レイアウトに配置される。このｎ-型拡散領域２には、高電位側領域１１を構成するｎ型拡散領域（不図示：図１の符号３）と、図２Ａと同様の構成でＨＶＮＭＯＳ２１の各部と、が配置される。ｐ-型エピタキシャル層５３の内部には、図２Ａと同様の構成でｐ+型共通電位領域５が配置される。ｐ-型エピタキシャル層５３の、ｐ+型共通電位領域５よりも外側に、低電位側領域１２を構成するｎ型拡散領域（不図示：図１の符号６）が配置される。 Further, as shown in FIG. 2F, a p- type epitaxial layer 53 may be provided instead of the p- type separation region 4. In FIG. 2F, the p - type epitaxial layer 53 is illustrated as "p- epi". In this case, for example, p - -type supported p on the substrate 51 - epitaxial substrate 50 -type epitaxial layer 53 is epitaxially grown is used. On the epitaxial substrate 50, an n- type diffusion region 2 that penetrates the p- type epitaxial layer 53 in the depth direction Z and reaches the p- type support substrate 51 is arranged in a substantially rectangular plane layout. In the n - type diffusion region 2, an n-type diffusion region (not shown: reference numeral 3 in FIG. 1) constituting the high potential side region 11 and each part of the HVNMOS 21 having the same configuration as that in FIG. 2A are arranged. .. Inside the p - type epitaxial layer 53, the p + type common potential region 5 is arranged with the same configuration as in FIG. 2A. p - type epitaxial layer 53, outside the p + -type common potential region 5, n-type diffusion region constituting the low potential side region 12 (not shown: code 6 of FIG. 1) is disposed.

以上、説明したように、実施の形態１によれば、セット用およびリセット用のレベルシフト回路を構成する各ＨＶＮＭＯＳ（レベルシフト素子）をソースフォロワ構成とすることで、これら２つのＨＶＮＭＯＳのドレイン電流の定電流性が改善され（図６の電圧・電流特性１４２が得られ）、伝達遅延時間差を小さくすることを防止することができる。また、ＨＶＮＭＯＳ（レベルシフト素子）をソースフォロワ構成とすることで、ドレイン電流を抑制することができるため、高速スイッチングによる発熱を抑制する（熱損失を低減させる）ことができ、高周波化が可能となる。 As described above, according to the first embodiment, the drain currents of these two HVNMOSs are obtained by forming each HVNMOS (level shift element) constituting the level shift circuit for setting and resetting as a source follower configuration. The constant current property of the above is improved (the voltage / current characteristic 142 of FIG. 6 is obtained), and it is possible to prevent the transmission delay time difference from being reduced. In addition, by configuring the HVNMOS (level shift element) as a source follower, the drain current can be suppressed, so heat generation due to high-speed switching can be suppressed (heat loss can be reduced), and high frequencies can be increased. Become.

また、実施の形態１によれば、ｐ+型共通電位領域を、ＨＶＮＭＯＳのｐ型バックゲート領域およびソースコンタクト領域と所定距離で離して配置する。このため、ｐ+型共通電位領域とＨＶＮＭＯＳのｐ型バックゲート領域およびソースコンタクト領域とは、当該ｐ+型共通電位領域とＨＶＮＭＯＳのｐ型バックゲート領域およびソースコンタクト領域との間の拡散抵抗（または基板抵抗）を介して電気的に接続される。これにより、ＨＶＮＭＯＳのソース電位と共通電位とを電気的に分離することができ、ＨＶＮＭＯＳを動作させることができる。 Further, according to the first embodiment, the p + type common potential region is arranged at a predetermined distance from the p-type back gate region and the source contact region of the HVNMOS. Therefore, the p + type common potential region and the p-type backgate region and the source contact region of the HVNMOS are the diffusion resistance between the p + type common potential region and the p-type backgate region and the source contact region of the HVNMOS. Or it is electrically connected via a substrate resistor). As a result, the source potential and the common potential of the HVNMOS can be electrically separated, and the HVNMOS can be operated.

また、実施の形態１によれば、ＨＶＮＭＯＳのｐ型バックゲート領域とｐ--型基板領域とが短絡されるため、自己分離構造やｐｎ接合分離構造で素子分離した半導体基板であっても、半導体基板内に寄生構造が形成されない。このため、ソースフォロワ構成によるＨＶＮＭＯＳの電流制御効果（ドレイン電流安定化）が安定して得られる。したがって、ＨＶＮＭＯＳを備えたレベルシフト回路において、安定したレベルシフト動作を行うことができる。 Further, according to the first embodiment, since the p-type back gate region and the p - type substrate region of the HVNMOS are short-circuited, even if the semiconductor substrate is element-separated by a self-separation structure or a pn junction separation structure, the element is separated. No parasitic structure is formed in the semiconductor substrate. Therefore, the current control effect (drain current stabilization) of the HVNMOS due to the source follower configuration can be stably obtained. Therefore, stable level shift operation can be performed in the level shift circuit provided with HVNMOS.

また、実施の形態１によれば、自己分離構造やｐｎ接合分離構造で素子分離した半導体基板であっても、半導体基板内に寄生構造が形成されないため、ＦＺ（Ｆｌｏａｔｉｎｇ Ｚｏｎｅ：浮遊帯）法やＣＺ（Ｃｚｏｃｈｒａｌｓｋｉ：チョクラルスキー）法、エピタキシャル成長法等で製造された安価な半導体基板を用いることができる。これにより、シリコン基板内に厚い絶縁層を埋め込んだＳＯＩ（Ｓｉｌｉｃｏｎ ｏｎ Ｉｎｓｕｌａｔｏｒ）基板等の高価な半導体基板を用いる必要がないため、コストを低減させることができる。 Further, according to the first embodiment, even if the semiconductor substrate is element-separated by a self-separation structure or a pn junction separation structure, a parasitic structure is not formed in the semiconductor substrate. Therefore, the FZ (Floating Zone) method or An inexpensive semiconductor substrate manufactured by a CZ (Czochralski) method, an epitaxial growth method, or the like can be used. As a result, it is not necessary to use an expensive semiconductor substrate such as an SOI (Silicon on Insulator) substrate in which a thick insulating layer is embedded in the silicon substrate, so that the cost can be reduced.

（実施の形態２）
次に、実施の形態２にかかる半導体装置の構造について説明する。図３は、実施の形態２にかかる半導体装置の構造を示す斜視図である。実施の形態２にかかる半導体装置が実施の形態１にかかる半導体装置と異なる点は、ｐ-型分離領域４にｎ型拡散領域（第７半導体領域）６１を配置し、ｐ+型共通電位領域５とＨＶＮＭＯＳ２１のソースコンタクト領域３６との間の拡散抵抗Ｒ’を高抵抗化した点である。図示省略するが、実施の形態２においても、ＨＶＮＭＯＳ２２の構成はＨＶＮＭＯＳ２１と同様である。 (Embodiment 2)
Next, the structure of the semiconductor device according to the second embodiment will be described. FIG. 3 is a perspective view showing the structure of the semiconductor device according to the second embodiment. The semiconductor device differs from that according to the semiconductor device according to the first embodiment of the second embodiment, p - -type isolation region 4 is arranged an n-type diffusion region (seventh semiconductor region) 61, p + -type common potential region This is a point in which the diffusion resistance R'between 5 and the source contact region 36 of the HVNMOS 21 is increased. Although not shown, the configuration of the HVNMOS 22 is the same as that of the HVNMOS 21 in the second embodiment as well.

ｎ型拡散領域６１は、ｐ+型共通電位領域５とＨＶＮＭＯＳ２１のソースコンタクト領域３６との間において、ｐ-型分離領域４の、基板おもて面側の表面層に選択的に設けられている。ｐ-型分離領域４の、ｎ型拡散領域６１との界面付近の部分のシート抵抗で、ｐ+型共通電位領域５とＨＶＮＭＯＳ２１のソースコンタクト領域３６との間の拡散抵抗Ｒ’の抵抗値が決まる。ｐ-型分離領域４にｎ型拡散領域６１を設けることで、ｐ+型共通電位領域５とＨＶＮＭＯＳ２１のソースコンタクト領域３６との間の拡散抵抗Ｒ’が高抵抗化される。その理由は、次の通りである。 The n-type diffusion region 61 is selectively provided on the surface layer on the front surface side of the substrate of the p- type separation region 4 between the p + type common potential region 5 and the source contact region 36 of the HVNMOS 21. There is. p - type isolation region 4, a sheet resistance of the interface near the portion of the n-type diffusion region 61, the resistance value of the diffusion resistance R 'between the source contact region 36 of the p + -type common potential region 5 and HVNMOS21 is It is decided. By providing the n-type diffusion region 61 in the p - type separation region 4, the diffusion resistance R'between the p + type common potential region 5 and the source contact region 36 of the HVNMOS 21 is increased. The reason is as follows.

ｐ-型分離領域４は、例えばイオン注入等で導入したｐ型不純物を拡散させることで形成される。このため、ｐ-型分離領域４の不純物濃度分布は、ガウス分布に基づいて半導体基板１０のおもて面付近で最も高く、かつ深さ方向Ｚに向かうにしたがって低くなっている。したがって、ｐ-型分離領域４の、基板おもて面側の表面層に例えばイオン注入等でｎ型不純物を導入して拡散させてｎ型拡散領域６１を形成することで、ｐ-型分離領域４の、基板おもて面側の実効的なｐ型不純物濃度が低くなり、ｐ-型分離領域４の基板おもて面側のシート抵抗が高くなるからである。 The p - type separation region 4 is formed by diffusing p-type impurities introduced by, for example, ion implantation. Therefore, the impurity concentration distribution in the p - type separation region 4 is highest near the front surface of the semiconductor substrate 10 based on the Gaussian distribution, and decreases toward the depth direction Z. Thus, p - -type isolation region 4, by introducing the n-type impurity into the surface layer of the substrate front side for example by ion implantation or the like are diffused to form the n-type diffusion region 61, p - -type isolation This is because the effective p-type impurity concentration on the substrate front surface side of the region 4 becomes low, and the sheet resistance on the substrate front surface side of the p-type separation region 4 increases.

ｐ-型分離領域４の導電型が反転しない程度に、ｐ-型分離領域４の、基板おもて面側の表面層にｎ型不純物が導入されている場合においても、ｐ-型分離領域４の基板おもて面側のシート抵抗を高くすることができる。すなわち、ｎ型拡散領域６１に代えて、ｐ-型分離領域４にｎ型不純物を導入してなる、ｐ-型分離領域４よりも不純物濃度の低いｐ--型拡散領域が設けられていてもよい。この場合、ｐ-型分離領域４の不純物濃度は、例えば１×１０13／ｃｍ3程度であり、当該ｐ--型拡散領域の不純物濃度は例えば６×１０12／ｃｍ3程度である。 p - to the extent that the conductivity type of the type isolation region 4 is not inverted, p - type isolation region 4, even when the n-type impurity is introduced into the surface layer of the substrate front side, p - -type isolation region The sheet resistance on the front surface side of the substrate of No. 4 can be increased. That is, instead of the n-type diffusion region 61, p - formed by introducing an n-type impurity type isolation region 4, p - -type isolation region lower in impurity concentration than 4 p - and -type diffusion region provided May be good. In this case, the impurity concentration of the p- type separation region 4 is, for example, about 1 × 10 13 / cm 3 , and the impurity concentration of the p- type diffusion region is, for example, about 6 × 10 12 / cm 3 .

また、後述するようにｐ-型分離領域４がｐ-型エピタキシャル層で構成されている場合（図２Ｅ参照）においても、ｐ-型分離領域４にｎ型拡散領域６１を設けることで、ｐ+型共通電位領域５とＨＶＮＭＯＳ２１のソースコンタクト領域３６との間の拡散抵抗Ｒ’が高抵抗化される。その理由は、ｐ-型分離領域４にｎ型拡散領域６１を設けることで、ｐ-型分離領域４の体積が小さくなり、ｐ-型分離領域４およびｎ型拡散領域６１の単位体積当たりのｐ型不純物濃度が高くなるからである。 Further, as will be described later, even when the p - type separation region 4 is composed of the p- type epitaxial layer (see FIG. 2E), by providing the n-type diffusion region 61 in the p-type separation region 4, p-type separation region 4 is provided. The diffusion resistance R'between the + type common potential region 5 and the source contact region 36 of the HVNMOS 21 is increased. The reason is, p - -type isolation region 4 by providing the n-type diffusion region 61, p - -type volume of the isolation region 4 is reduced, p - per unit volume type isolation region 4 and the n-type diffusion region 61 This is because the concentration of p-type impurities increases.

このようにｐ-型分離領域４にｎ型拡散領域６１（またはｐ--型拡散領域）を配置することで、ｐ+型共通電位領域５とＨＶＮＭＯＳ２１のソースコンタクト領域３６との最短距離Ｘ１を短くしても所定の抵抗値の拡散抵抗Ｒ’が得られる。また、ｐ+型共通電位領域５とＨＶＮＭＯＳ２１のソースコンタクト領域３６との最短距離Ｘ１を短くすることで、ｐ+型共通電位領域５とＨＶＮＭＯＳ２１のソースコンタクト領域３６との間の無効領域の面積が小さくなるため、チップサイズを縮小化することができる。無効領域とは、配線や回路等が配置されない領域である。 By arranging the n-type diffusion region 61 (or p - type diffusion region) in the p - type separation region 4 in this way, the shortest distance X1 between the p + type common potential region 5 and the source contact region 36 of the HVNMOS 21 can be set. Even if it is shortened, a diffusion resistance R'with a predetermined resistance value can be obtained. Further, by shortening the shortest distance X1 between the source contact region 36 of the p + -type common potential region 5 and HVNMOS21, the area of the ineffective region between the source contact region 36 of the p + -type common potential region 5 and HVNMOS21 Since it becomes smaller, the chip size can be reduced. The invalid area is an area in which wiring, circuits, etc. are not arranged.

また、ｎ型拡散領域６１は、ｐ-型分離領域４の径方向Ｄに所定距離Ｘ２を空けてＨＶＮＭＯＳ２１のソースコンタクト領域３６に対向する。ｎ型拡散領域６１が距離Ｘ２でソースコンタクト領域３６に対向する部分の長さ（ｐ-型分離領域４の周方向Ｒの長さ）Ｘ３は、可能な限り長いことが好ましい。図３には、ｎ型拡散領域６１が距離Ｘ２でソースコンタクト領域３６に対向する部分を内側に突出させた略Ｔ字状の平面レイアウトにｎ型拡散領域６１を配置した場合を示す（太線で囲む部分）。ｐ-型分離領域４にｎ型拡散領域６１を配置することで拡散抵抗Ｒ’を高抵抗化することができればよく、ｎ型拡散領域６１の平面レイアウトは種々変更可能である。 Further, the n-type diffusion region 61 faces the source contact region 36 of the HVNMOS 21 with a predetermined distance X2 in the radial direction D of the p-type separation region 4. The length (length of the circumferential direction R of the p- type separation region 4) X3 of the portion where the n-type diffusion region 61 faces the source contact region 36 at a distance X2 is preferably as long as possible. FIG. 3 shows a case where the n-type diffusion region 61 is arranged in a substantially T-shaped plane layout in which a portion of the n-type diffusion region 61 facing the source contact region 36 at a distance X2 is projected inward (thick lines). Surrounding part). It suffices if the diffusion resistance R'can be increased by arranging the n-type diffusion region 61 in the p- type separation region 4, and the planar layout of the n-type diffusion region 61 can be variously changed.

ｎ型拡散領域６１は、フローティング（浮遊）電位、バックゲート電位および高電位側電源電位Ｖｃｃ１のいずれの電位に固定されてもよい。ｎ型拡散領域６１をバックゲート電位以外の電位に固定する場合、ｎ型拡散領域６１は、上述したようにＨＶＮＭＯＳ２１のｐ型バックゲート領域３１およびソースコンタクト領域３６と距離Ｘ２で離して配置される（すなわちＸ２＞０）。その理由は、例えばｎ型拡散領域６１を高電位側電源電位Ｖｃｃ１に固定したときに、回路全体の耐圧がＨＶＮＭＯＳ２１の横方向の耐圧に律速されてしまうからである。 The n-type diffusion region 61 may be fixed at any of the floating potential, the back gate potential, and the high potential side power supply potential Vcc1. When the n-type diffusion region 61 is fixed to a potential other than the backgate potential, the n-type diffusion region 61 is arranged at a distance X2 from the p-type backgate region 31 and the source contact region 36 of the HVNMOS 21 as described above. (That is, X2> 0). The reason is that, for example, when the n-type diffusion region 61 is fixed to the high potential side power supply potential Vcc1, the withstand voltage of the entire circuit is regulated by the withstand voltage in the lateral direction of the HVNMOS 21.

例えば、ｐ-型分離領域４とｎ型拡散領域６１との間に、高電位側電源電位Ｖｃｃ１から共通電位ＣＯＭを減算した電位差の電圧が印加されるとする（すなわち、ｎ型拡散領域６１を高電位側電源電位Ｖｃｃ１に固定）。この場合に、横方向のｎｐｎ寄生バイポーラトランジスタが動作する、また、ｐ-型分離領域４とｎ型拡散領域６１とのｐｎ接合から伸びる空乏層がＨＶＮＭＯＳ２１のソースコンタクト領域３６にパンチスルーして、２０Ｖ程度のソース・ドレイン間電圧でＨＶＮＭＯＳ２１がブレークダウンし、高電位側電源電位Ｖｃｃ１と共通電位ＣＯＭ間の漏れ電流となる、等によりＨＶＮＭＯＳ２１の横方向の耐圧が低下する。このような問題が生じない程度に、ｎ型拡散領域６１とＨＶＮＭＯＳ２１のソースコンタクト領域３６との距離Ｘ２が設定される。具体的には、ｎ型拡散領域６１とＨＶＮＭＯＳ２１のソースコンタクト領域３６との距離Ｘ２は、例えば５μｍ以上程度であってもよい。 For example, it is assumed that a voltage having a potential difference obtained by subtracting the common potential COM from the high potential side power supply potential Vcc1 is applied between the p-type separation region 4 and the n-type diffusion region 61 (that is, the n-type diffusion region 61 is applied. High potential side power supply potential Vcc1 fixed). In this case, the lateral npn parasitic bipolar transistor operates, and the depletion layer extending from the pn junction between the p- type separation region 4 and the n-type diffusion region 61 punches through the source contact region 36 of the HVNMOS 21. The HVNMOS 21 breaks down at a source-drain voltage of about 20 V, resulting in a leakage current between the high potential side power supply potential Vcc1 and the common potential COM, and the like, so that the withstand voltage of the HVNMOS 21 in the lateral direction decreases. The distance X2 between the n-type diffusion region 61 and the source contact region 36 of the HVNMOS 21 is set to such an extent that such a problem does not occur. Specifically, the distance X2 between the n-type diffusion region 61 and the source contact region 36 of the HVNMOS 21 may be, for example, about 5 μm or more.

ｎ型拡散領域６１をバックゲート電位に固定する場合には、ｎ型拡散領域６１は、ＨＶＮＭＯＳ２１のｐ型バックゲート領域３１およびソースコンタクト領域３６と接していてもよい（すなわちＸ２＝０）。 When the n-type diffusion region 61 is fixed to the back gate potential, the n-type diffusion region 61 may be in contact with the p-type back gate region 31 and the source contact region 36 of the HVNMOS 21 (that is, X2 = 0).

図２Ｂに示すＨＶＮＭＯＳ２１に実施の形態２を適用してもよい（すなわちｐ型バックゲート領域３１を設けない構成）。また、図２Ｃ，２Ｄに示すＨＶＮＭＯＳ２１に実施の形態２を適用してもよい（すなわちｐ-型分離領域をｐ--型基板領域１で構成した素子分離構造）。すなわち、ｐ-型分離領域を構成するｐ--型基板領域１の、ｐ+型共通電位領域５とＨＶＮＭＯＳ２１のソースコンタクト領域３６との間にｎ型拡散領域６１を配置してもよい。また、図２Ｅ，２Ｆに示すＨＶＮＭＯＳ２１に実施の形態２を適用してもよい（すなわちｎ-型拡散領域２およびｐ-型分離領域４のいずれかをエピタキシャル層とした構成）。 The second embodiment may be applied to the HVNMOS 21 shown in FIG. 2B (that is, the p-type back gate region 31 is not provided). Further, FIG. 2C, may be applied a second embodiment in HVNMOS21 shown in 2D (i.e. p - type isolation regions p - isolation structure constituted by -type substrate region 1). That, p - -type constituting the isolation region p - type substrate region 1 may be arranged n-type diffusion region 61 between the source contact region 36 of the p + -type common potential region 5 and HVNMOS21. Further, the second embodiment may be applied to the HVNMOS 21 shown in FIGS. 2E and 2F (that is, a configuration in which either the n- type diffusion region 2 or the p - type separation region 4 is an epitaxial layer).

以上、説明したように、実施の形態２によれば、実施の形態１と同様の効果を得ることができる。また、実施の形態２によれば、ｐ-型分離領域にｎ型拡散領域を設けることで、ｐ-型分離領域を共通電位に固定するｐ+型共通電位領域と、ＨＶＮＭＯＳのソースコンタクト領域と、の最短距離を短くしても所定の抵抗値の拡散抵抗が得られる。このため、ｐ+型共通電位領域の配置の自由度が高くなり、チップレイアウトの制御が少なくなる。 As described above, according to the second embodiment, the same effect as that of the first embodiment can be obtained. Further, according to the second embodiment, p - -type isolation region by providing the n-type diffusion region, p - and p + -type common potential region for fixing the type isolation region to a common potential, and the source contact region HVNMOS Even if the shortest distance of, is shortened, the diffusion resistance of a predetermined resistance value can be obtained. Therefore, the degree of freedom in arranging the p + type common potential region is increased, and the control of the chip layout is reduced.

（実施の形態３）
次に、実施の形態３にかかる半導体装置の構造について説明する。図４Ａは、実施の形態３にかかる半導体装置の平面レイアウトを示す平面図である。実施の形態３にかかる半導体装置が実施の形態１にかかる半導体装置と異なる点は、ｐ-型分離領域４を共通電位ＣＯＭに固定するｐ+型共通電位領域６５を、略矩形状の平面レイアウトに配置されたｐ-型分離領域４の頂点付近のみに配置した点である。 (Embodiment 3)
Next, the structure of the semiconductor device according to the third embodiment will be described. FIG. 4A is a plan view showing a plan layout of the semiconductor device according to the third embodiment. The semiconductor device differs from that according to Embodiment 1 of the semiconductor device is carried out according to the third embodiment, p - p + -type common potential region 65 for fixing the type isolation region 4 to the common potential COM, substantially rectangular planar layout It is a point arranged only near the apex of the p -type separation region 4 arranged in.

以上、説明したように、実施の形態３によれば、ｐ+型共通電位領域の配置に依らず、実施の形態１，２と同様の効果を得ることができる。 As described above, according to the third embodiment, the same effect as that of the first and second embodiments can be obtained regardless of the arrangement of the p + type common potential region.

（実施の形態４）
次に、実施の形態４にかかる半導体装置の構造について説明する。図４Ｂは、実施の形態４にかかる半導体装置の平面レイアウトを示す平面図である。実施の形態４にかかる半導体装置が実施の形態１にかかる半導体装置と異なる点は、次の２点である。１つ目の相違点は、ＨＶＮＭＯＳ２１，２２がｎ-型拡散領域２からｎ型拡散領域３にわたって設けられている点である。２つ目の相違点は、ＨＶＮＭＯＳ２１，２２の周囲をそれぞれ囲むようにｐ-型スリット領域７１，７２が設けられている点である。 (Embodiment 4)
Next, the structure of the semiconductor device according to the fourth embodiment will be described. FIG. 4B is a plan view showing a plan layout of the semiconductor device according to the fourth embodiment. The semiconductor device according to the fourth embodiment is different from the semiconductor device according to the first embodiment in the following two points. The first difference is, HVNMOS21,22 the n - in that provided over the diffusion region 2 n-type diffusion region 3 from. The second difference is that p- shaped slit regions 71 and 72 are provided so as to surround the circumferences of the HVNMOS 21 and 22, respectively.

具体的には、ｐ-型スリット領域７１，７２は、ｎ-型拡散領域２およびｎ型拡散領域３からなるｎ型領域に略Ｕ字状の平面レイアウトに設けられ、ＨＶＮＭＯＳ２１，２２の周囲をそれぞれ囲む。ｐ-型スリット領域７１，７２は、半導体基板１０のおもて面から深さ方向にｐ--型基板領域１に達する深さで設けられている。すなわち、ｐ-型スリット領域７１，７２は、ｎ-型拡散領域２およびｎ型拡散領域３を、ＨＶＮＭＯＳ２１，２２が配置された部分と、それ以外の部分と、に分離している。 Specifically, the p - type slit regions 71 and 72 are provided in an n - type region composed of the n-type diffusion region 2 and the n-type diffusion region 3 in a substantially U-shaped plane layout, and surround the HVNMOS 21 and 22. Surround each. The p - type slit regions 71 and 72 are provided at a depth reaching the p- type substrate region 1 in the depth direction from the front surface of the semiconductor substrate 10. That is, the p - type slit regions 71 and 72 separate the n- type diffusion region 2 and the n-type diffusion region 3 into a portion where the HVNMOS 21 and 22 are arranged and a portion other than that.

また、ｐ-型スリット領域７１，７２は、略Ｕ字状の両端部でｐ-型分離領域４と接している。すなわち、ＨＶＮＭＯＳ２１は、ｐ-型スリット領域７１と３辺とし、ｐ-型分離領域４を残りの１辺とする略矩形状のｐ-型領域に囲まれている。ＨＶＮＭＯＳ２２は、ｐ-型スリット領域７２と３辺とし、ｐ-型分離領域４を残りの１辺とする略矩形状のｐ-型領域に囲まれている。ＨＶＮＭＯＳ２１，２２のｎ+型ドレイン領域３４は、ｎ型拡散領域３に設けられる。 Further, the p - type slit regions 71 and 72 are in contact with the p - type separation region 4 at both ends of a substantially U-shape. That is, the HVNMOS 21 is surrounded by a substantially rectangular p- type region having a p- type slit region 71 and three sides and a p - type separation region 4 as the remaining one side. The HVNMOS 22 is surrounded by a substantially rectangular p- type region having a p- type slit region 72 and three sides and a p - type separation region 4 as the remaining one side. The n + type drain region 34 of the HVNMOS 21 and 22 is provided in the n type diffusion region 3.

ｐ-型スリット領域７１，７２は、ｐ--型基板領域１（ｐ--型の半導体基板１０の、拡散領域２，３を形成しない部分）を半導体基板１０のおもて面に露出させて構成されていてもよい。また、ｐ-型スリット領域７１，７２は、当該ｐ--型基板領域１や拡散領域２，３にイオン注入等により不純物を導入することで形成されたｐ-型拡散領域であってもよい。 In the p - type slit regions 71 and 72, the p - type substrate region 1 (the portion of the p - type semiconductor substrate 10 that does not form the diffusion regions 2 and 3) is exposed on the front surface of the semiconductor substrate 10. May be configured. Further, the p - type slit regions 71 and 72 may be p- type diffusion regions formed by introducing impurities into the p- type substrate region 1 and diffusion regions 2 and 3 by ion implantation or the like. ..

図示省略するが、ｐ-型スリット領域７１，７２は、ｎ-型拡散領域２のみに設けられていてもよい。この場合、ＨＶＮＭＯＳ２１，２２のｎ+型ドレイン領域３４は、実施の形態１と同様にｎ-型拡散領域２に設けられる。ｐ-型スリット領域７１，７２は、ｎ-型拡散領域２を、ＨＶＮＭＯＳ２１，２２が配置された部分と、それ以外の部分と、に分離する。 Although not shown, the p - type slit regions 71 and 72 may be provided only in the n-type diffusion region 2. In this case, the n + type drain region 34 of the HVNMOS 21 and 22 is provided in the n − type diffusion region 2 as in the first embodiment. The p - type slit regions 71 and 72 separate the n- type diffusion region 2 into a portion where the HVNMOS 21 and 22 are arranged and a portion other than that.

このｐ-型スリット領域７１，７２は、ＨＶＮＭＯＳ２１，２２のｎ+型ドレイン領域３４に高電圧が印加された際（例えば、図５の回路に用いた場合において、上アームのＩＧＢＴ１２１がオン状態となり交流出力端子ＯＵＴの電位がブリッジ回路１２０の略電源電位Ｖｄｃとなったとき）には空乏化される。 In the p - type slit regions 71 and 72, when a high voltage is applied to the n + type drain region 34 of the HVNMOS 21 and 22 (for example, when used in the circuit of FIG. 5, the IGBT 121 of the upper arm is turned on. When the potential of the AC output terminal OUT becomes the substantially power supply potential Vdc of the bridge circuit 120), it is depleted.

以上、説明したように、実施の形態４によれば、実施の形態１〜３と同様の効果を得ることができる。実施の形態４によれば、ＨＶＮＭＯＳのｎ+型ドレイン領域に高電圧が印加されたとしても、ＨＶＮＭＯＳの周囲を囲むｐ-型スリット領域が空乏化され、耐圧が確保される。 As described above, according to the fourth embodiment, the same effects as those of the first to third embodiments can be obtained. According to the fourth embodiment, even if a high voltage is applied to the n + type drain region of the HVNMOS, the p − type slit region surrounding the HVNMOS is depleted and the withstand voltage is ensured.

（実施の形態５）
次に、実施の形態５にかかる半導体装置の構造について説明する。図４Ｃは、実施の形態５にかかる半導体装置の平面レイアウトを示す平面図である。実施の形態５にかかる半導体装置は、ｐ-型スリット領域７３の配置が実施の形態４にかかる半導体装置と異なる。具体的には、ｐ-型スリット領域７３は、ｎ-型拡散領域２に、ｎ型拡散領域３の周囲を囲むように設けられている。 (Embodiment 5)
Next, the structure of the semiconductor device according to the fifth embodiment will be described. FIG. 4C is a plan view showing a plan layout of the semiconductor device according to the fifth embodiment. The semiconductor device according to the fifth embodiment is different from the semiconductor device according to the fourth embodiment in the arrangement of the p-type slit region 73. Specifically, the p - type slit region 73 is provided in the n - type diffusion region 2 so as to surround the n-type diffusion region 3.

ｐ-型スリット領域７３は、ｎ-型拡散領域２に略Ｃ字状（一部が開口した略矩形状）の平面レイアウトに設けられ、ｎ型拡散領域３の周囲を囲む。ｐ-型スリット領域７３は、半導体基板１０のおもて面から深さ方向にｐ--型基板領域１に達する深さで設けられている。すなわち、ｎ-型拡散領域２は、ｐ-型スリット領域７３が配置された部分で、ｎ型拡散領域３と分離されている。 The p - type slit region 73 is provided in the n - type diffusion region 2 in a substantially C-shaped (substantially rectangular shape with a part open) planar layout, and surrounds the n-type diffusion region 3. The p - type slit region 73 is provided at a depth that reaches the p- type substrate region 1 in the depth direction from the front surface of the semiconductor substrate 10. That is, the n - type diffusion region 2 is separated from the n-type diffusion region 3 at the portion where the p-type slit region 73 is arranged.

図示省略するが、ｐ-型スリット領域７３は、ｎ型拡散領域３に設けられていてもよい。この場合、ｐ-型スリット領域７３は、ｎ型拡散領域３の中央部を囲む略Ｃ字状の平面レイアウトに配置される。 Although not shown, the p - type slit region 73 may be provided in the n-type diffusion region 3. In this case, the p - shaped slit region 73 is arranged in a substantially C-shaped plane layout surrounding the central portion of the n-shaped diffusion region 3.

このｐ-型スリット領域７３は、ＨＶＮＭＯＳ２１，２２のｎ+型ドレイン領域３４に高電圧が印加された際（例えば、図５の回路に用いた場合において、上アームのＩＧＢＴ１２１がオン状態となり交流出力端子ＯＵＴの電位がブリッジ回路１２０の略電源電位Ｖｄｃとなったとき）には空乏化される。 The p - type slit region 73 has an AC output when a high voltage is applied to the n + type drain region 34 of the HVNMOS 21 and 22 (for example, when used in the circuit of FIG. 5, the IGBT 121 of the upper arm is turned on. When the potential of the terminal OUT becomes the substantially power supply potential Vdc of the bridge circuit 120), it is depleted.

以上、説明したように、実施の形態５によれば、実施の形態１〜４と同様の効果を得ることができる。実施の形態５によれば、ＨＶＮＭＯＳのｎ+型ドレイン領域に高電圧が印加されたとしても、ｎ型拡散領域の周囲を囲むｐ-型領域が空乏化され、耐圧が確保される。 As described above, according to the fifth embodiment, the same effects as those of the first to fourth embodiments can be obtained. According to the fifth embodiment, even if a high voltage is applied to the n + type drain region of the HVNMOS, the p − type region surrounding the n type diffusion region is depleted and the withstand voltage is ensured.

以上において本発明は、上述した実施の形態に限らず、本発明の趣旨を逸脱しない範囲で種々変更可能である。例えば、ｐ+型共通電位領域とＨＶＮＭＯＳのソースコンタクト領域およびｐ型バックゲート領域とが、ｐ-型分離領域の拡散抵抗（または基板抵抗）を介して接続さればよく、ｐ+型共通電位領域と、ＨＶＮＭＯＳのソースコンタクト領域およびｐ型バックゲート領域と、の位置関係（平面レイアウト）は種々変更可能である。また、上述した各実施の形態では、パワーデバイスを駆動するゲートドライバＩＣを例に説明しているが、ＭＯＳＦＥＴをソースフォロワ構成とした様々な回路に適用可能である。また、本発明は、導電型（ｎ型、ｐ型）を反転させても同様に成り立つ。 As described above, the present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the spirit of the present invention. For example, the p + type common potential region and the source contact region and p-type backgate region of the HVNMOS may be connected via the diffusion resistance (or substrate resistance) of the p- type separation region, and the p + type common potential region may be connected. The positional relationship (planar layout) between the source contact region and the p-type backgate region of the HVNMOS can be changed in various ways. Further, in each of the above-described embodiments, the gate driver IC for driving the power device is described as an example, but it can be applied to various circuits having a MOSFET as a source follower configuration. Further, the present invention holds the same even if the conductive type (n type, p type) is inverted.

以上のように、本発明にかかる半導体装置は、インバータなどの電力変換装置や種々の産業用機械などに用いる電源装置などに使用される半導体装置に有用である。 As described above, the semiconductor device according to the present invention is useful for semiconductor devices used in power conversion devices such as inverters and power supply devices used in various industrial machines.

１ ｐ--型基板領域
２ ｎ-型拡散領域
３，６，６１ ｎ型拡散領域
４ ｐ-型分離領域
５ ｐ+型共通電位領域
１０ 半導体基板
１１ 高電位側領域
１２ 低電位側領域
１３ ＨＶＪＴ
２０ ＨＶＩＣ
２１，２２ ＨＶＮＭＯＳ
３１ ｐ型バックゲート領域
３２ ｎ+型ソース領域
３３ ｐ+型コンタクト領域
３４ ｎ+型ドレイン領域
３５ ゲート電極
３６ ソースコンタクト領域
４１ ＣＯＭ電極パッド
５０ エピタキシャル基板
５１ ｐ--型支持基板
５２ ｎ-型エピタキシャル層
５３ ｐ-型エピタキシャル層
７１〜７３ ｐ-型スリット領域
１０１，１０２ ＨＶＮＭＯＳ
１０３，１０４ 負荷抵抗
１０５，１０６ 定電圧ダイオード
１０７，１０８ ＮＯＴ回路
１１０ 高電位側回路部
１１１，１１２ 電流帰還抵抗
１１３，１１４ 定電圧ダイオード
１２０ ブリッジ回路
１２１ 上アームのＩＧＢＴ
１２２ 下アームのＩＧＢＴ
１２３ 上アームのＩＧＢＴと下アームのＩＧＢＴとの接続点
１３１ オン信号
１３２ オフ信号
ＣＯＭ 共通電位
Ｅ１ 高電圧側の補助直流電源
Ｅ２ 低電圧側の補助直流電源
ＯＵＴ 交流出力端子
Ｖｃｃ１ 高電圧側の補助直流電源の正極ラインの電位（高電位側電源電位）
Ｖｃｃ２ 低電圧側の補助直流電源の正極ラインの電位（低電位側電源電位）
Ｖｄｃ ブリッジ回路の正極側の電位（電源電位） 1 p - type substrate region 2 n - type diffusion region 3, 6, 61 n-type diffusion region 4 p - type separation region 5 p + type common potential region 10 Semiconductor substrate 11 High potential side region 12 Low potential side region 13 HVJT
20 HVIC
21 and 22 HVNMOS
31 p-type back gate region 32 n + -type source region 33 p + -type contact region 34 n + -type drain region 35 a gate electrode 36 source contact region 41 COM electrode pads 50 epitaxial substrate 51 p - -type supporting substrate 52 n - -type epitaxial Layer 53 p - type epitaxial layer 71-73 p- type slit region 101,102 HVNMOS
103, 104 Load resistance 105, 106 Zener diode 107, 108 NOT circuit 110 High potential side circuit section 111, 112 Current feedback resistor 113, 114 Zener diode 120 Bridge circuit 121 Upper arm IGBT
122 Lower arm IGBT
123 Connection point between the IGBT of the upper arm and the IGBT of the lower arm 131 On signal 132 Off signal COM Common potential E1 Auxiliary DC power supply on the high voltage side E2 Auxiliary DC power supply on the low voltage side OUT AC output terminal Vcc1 Auxiliary DC on the high voltage side Potential of the positive line of the power supply (high potential side power supply potential)
Vcc2 Potential of the positive electrode line of the auxiliary DC power supply on the low voltage side (low potential side power supply potential)
Potential on the positive electrode side of the Vdc bridge circuit (power supply potential)

Claims (13)

第１導電型の半導体基板と、
前記半導体基板の一方の主面側に選択的に設けられた第２導電型の第１半導体領域と、
前記半導体基板と前記第１半導体領域とのｐｎ接合で形成され、電位の異なる領域を分離する分離構造と、
前記半導体基板の一方の主面側に、前記第１半導体領域と離して選択的に設けられ、第１抵抗体を介して最低電位の電極に電気的に接続された第２導電型の第２半導体領域と、前記第１半導体領域の内部に選択的に設けられた、前記第１半導体領域よりも不純物濃度の高い第２導電型の第３半導体領域と、前記第１半導体領域と前記第２半導体領域との間の前記半導体基板に沿って設けられたゲート絶縁膜と、前記ゲート絶縁膜に沿って設けられたゲート電極と、を有し、前記最低電位を基準とした信号を、前記最低電位と異なる電位を基準とした信号に変換する半導体素子と、
前記半導体基板の一方の主面側に、所定距離で前記第２半導体領域と離して選択的に設けられ、前記最低電位の電極に電気的に接続された、前記半導体基板よりも不純物濃度の高い第１導電型の第４半導体領域と、
を備え、
前記第２半導体領域は、第２抵抗体を介して前記第４半導体領域と電気的に接続され、
前記第２抵抗体は、前記半導体基板の、前記第２半導体領域と前記第４半導体領域との間の部分で構成されていることを特徴とする半導体装置。 The first conductive type semiconductor substrate and
A second conductive type first semiconductor region selectively provided on one main surface side of the semiconductor substrate,
A separation structure formed by a pn junction between the semiconductor substrate and the first semiconductor region and separating regions having different potentials,
A second conductive type second that is selectively provided on one main surface side of the semiconductor substrate apart from the first semiconductor region and electrically connected to the lowest potential electrode via the first resistor. A semiconductor region, a second conductive type third semiconductor region selectively provided inside the first semiconductor region, which has a higher impurity concentration than the first semiconductor region, the first semiconductor region, and the second semiconductor region. It has a gate insulating film provided along the semiconductor substrate between the semiconductor region and a gate electrode provided along the gate insulating film, and a signal with reference to the minimum potential is used as the minimum. A semiconductor element that converts a signal based on a potential different from the potential, and
The impurity concentration is higher than that of the semiconductor substrate, which is selectively provided on one main surface side of the semiconductor substrate at a predetermined distance away from the second semiconductor region and electrically connected to the electrode having the lowest potential. The first conductive type fourth semiconductor region and
With
The second semiconductor region is electrically connected to the fourth semiconductor region via a second resistor.
The semiconductor device is characterized in that the second resistor is composed of a portion of the semiconductor substrate between the second semiconductor region and the fourth semiconductor region. 前記半導体基板の一方の主面側に選択的に設けられ、前記第１半導体領域に接する、前記半導体基板よりも不純物濃度の高い第１導電型の第５半導体領域をさらに備え、
前記分離構造は、前記第５半導体領域と前記第１半導体領域とのｐｎ接合で形成され、
前記第２半導体領域および前記第４半導体領域は、前記第５半導体領域の内部に設けられ、
前記ゲート絶縁膜は、前記第１半導体領域と前記第２半導体領域との間の前記第５半導体領域に沿って設けられ、
前記第２抵抗体は、前記第５半導体領域の、前記第２半導体領域と前記第４半導体領域との間の部分で構成されていることを特徴とする請求項１に記載の半導体装置。 A first conductive type fifth semiconductor region, which is selectively provided on one main surface side of the semiconductor substrate and is in contact with the first semiconductor region and has a higher impurity concentration than the semiconductor substrate, is further provided.
The separated structure is formed by a pn junction between the fifth semiconductor region and the first semiconductor region.
The second semiconductor region and the fourth semiconductor region are provided inside the fifth semiconductor region.
The gate insulating film is provided along the fifth semiconductor region between the first semiconductor region and the second semiconductor region.
The semiconductor device according to claim 1, wherein the second resistor is composed of a portion of the fifth semiconductor region between the second semiconductor region and the fourth semiconductor region. 前記第１半導体領域の内部に選択的に設けられ、前記半導体基板の、前記第２半導体領域と前記第４半導体領域との間の部分に接する、前記半導体基板よりも不純物濃度の高い第１導電型の第６半導体領域をさらに備え、
前記第２半導体領域は、前記第６半導体領域の内部に、前記半導体基板の、前記第２半導体領域と前記第４半導体領域との間の部分に接して設けられ、
前記ゲート絶縁膜は、前記第１半導体領域と前記第２半導体領域との間の前記第６半導体領域に沿って設けられていることを特徴とする請求項１に記載の半導体装置。 A first conductor that is selectively provided inside the first semiconductor region and is in contact with a portion of the semiconductor substrate between the second semiconductor region and the fourth semiconductor region and has a higher impurity concentration than the semiconductor substrate. Further equipped with a sixth semiconductor region of the mold,
The second semiconductor region is provided inside the sixth semiconductor region in contact with a portion of the semiconductor substrate between the second semiconductor region and the fourth semiconductor region.
The semiconductor device according to claim 1, wherein the gate insulating film is provided along the sixth semiconductor region between the first semiconductor region and the second semiconductor region. 前記第１半導体領域の内部に選択的に設けられ、前記第５半導体領域の、前記第２半導体領域と前記第４半導体領域との間の部分に接する、前記第５半導体領域よりも不純物濃度の高い第１導電型の第６半導体領域をさらに備え、
前記第２半導体領域は、前記第６半導体領域の内部に、前記第５半導体領域の、前記第２半導体領域と前記第４半導体領域との間の部分に接して設けられ、
前記ゲート絶縁膜は、前記第１半導体領域と前記第２半導体領域との間の前記第６半導体領域に沿って設けられていることを特徴とする請求項２に記載の半導体装置。 The impurity concentration is higher than that of the fifth semiconductor region, which is selectively provided inside the first semiconductor region and is in contact with the portion of the fifth semiconductor region between the second semiconductor region and the fourth semiconductor region. Further equipped with a high first conductive type sixth semiconductor region,
The second semiconductor region is provided inside the sixth semiconductor region in contact with a portion of the fifth semiconductor region between the second semiconductor region and the fourth semiconductor region.
The semiconductor device according to claim 2, wherein the gate insulating film is provided along the sixth semiconductor region between the first semiconductor region and the second semiconductor region. 前記半導体基板の、前記第２半導体領域と前記第４半導体領域との間の部分に選択的に設けられた第２導電型の第７半導体領域をさらに備えることを特徴とする請求項１または３に記載の半導体装置。 1 or 3 of the semiconductor substrate, further comprising a second conductive type seventh semiconductor region selectively provided in a portion between the second semiconductor region and the fourth semiconductor region. The semiconductor device described in 1. 前記半導体基板の、前記第２半導体領域と前記第４半導体領域との間の部分に選択的に設けられ、前記第６半導体領域に電気的に接続された第２導電型の第７半導体領域をさらに備えることを特徴とする請求項３に記載の半導体装置。 A second conductive type seventh semiconductor region selectively provided in a portion of the semiconductor substrate between the second semiconductor region and the fourth semiconductor region and electrically connected to the sixth semiconductor region is provided. The semiconductor device according to claim 3, further comprising. 前記第５半導体領域の、前記第２半導体領域と前記第４半導体領域との間の部分に選択的に設けられた第２導電型の第７半導体領域をさらに備えることを特徴とする請求項２または４に記載の半導体装置。 2. A second aspect of the fifth semiconductor region, further comprising a second conductive type seventh semiconductor region selectively provided in a portion between the second semiconductor region and the fourth semiconductor region. Or the semiconductor device according to 4. 前記第５半導体領域の、前記第２半導体領域と前記第４半導体領域との間の部分に選択的に設けられ、前記第６半導体領域に電気的に接続された第２導電型の第７半導体領域をさらに備えることを特徴とする請求項４に記載の半導体装置。 A second conductive type seventh semiconductor selectively provided in a portion of the fifth semiconductor region between the second semiconductor region and the fourth semiconductor region and electrically connected to the sixth semiconductor region. The semiconductor device according to claim 4, further comprising a region. 前記第７半導体領域の電位は、浮遊電位または電源電位であることを特徴とする請求項５または７に記載の半導体装置。 The semiconductor device according to claim 5 or 7, wherein the potential of the seventh semiconductor region is a floating potential or a power supply potential. 前記第１抵抗体は、前記第２抵抗体に並列に接続された抵抗素子であることを特徴とする請求項１〜９のいずれか一つに記載の半導体装置。 The semiconductor device according to any one of claims 1 to 9, wherein the first resistor is a resistance element connected in parallel to the second resistor. 前記第１抵抗体の抵抗値よりも前記第２抵抗体の抵抗値の方が高いことを特徴とする請求項１０に記載の半導体装置。 The semiconductor device according to claim 10, wherein the resistance value of the second resistor is higher than the resistance value of the first resistor. 前記第１抵抗体として、前記第２抵抗体を用いることを特徴とする請求項１〜９のいずれか一つに記載の半導体装置。 The semiconductor device according to any one of claims 1 to 9, wherein the second resistor is used as the first resistor. 前記半導体素子は、前記分離構造を形成するｐｎ接合に沿って配置され、
前記第４半導体領域は、前記半導体基板の一方の主面と平行な方向で、かつ前記分離構造を形成するｐｎ接合のうち、前記半導体素子が配置された部分のｐｎ接合面と直交する方向に、前記第２半導体領域と対向しないことを特徴とする請求項１〜１２のいずれか一つに記載の半導体装置。 The semiconductor element is arranged along a pn junction forming the separated structure.
The fourth semiconductor region is in a direction parallel to one main surface of the semiconductor substrate and in a direction orthogonal to the pn junction surface of the portion of the pn junction forming the separated structure in which the semiconductor element is arranged. The semiconductor device according to any one of claims 1 to 12, wherein the semiconductor device does not face the second semiconductor region.
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