JP6785802B2 - Detection, quantification and control of process-induced asymmetry using patterned wafer geometry measurement - Google Patents

Detection, quantification and control of process-induced asymmetry using patterned wafer geometry measurement Download PDF

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JP6785802B2
JP6785802B2 JP2017566282A JP2017566282A JP6785802B2 JP 6785802 B2 JP6785802 B2 JP 6785802B2 JP 2017566282 A JP2017566282 A JP 2017566282A JP 2017566282 A JP2017566282 A JP 2017566282A JP 6785802 B2 JP6785802 B2 JP 6785802B2
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プラディープ ブッカダラ
プラディープ ブッカダラ
ジャイディープ ケー シンハ
ジャイディープ ケー シンハ
ジェーエイチ キム
ジェーエイチ キム
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Description

本件開示は総じて半導体製造の分野に関し、具体的にはプロセス誘起非対称性(process-induced asymmetry)の検出、定量及び制御技術に関する。 The present disclosure relates to the field of semiconductor manufacturing as a whole, and more specifically to process-induced asymmetry detection, quantification and control techniques.

（関連出願への相互参照）
本願は２０１５年６月２２日付米国暫定特許出願第６２／１８３１０５号に基づき米国特許法第１１９条（ｅ）の規定による利益を主張する出願である。この参照を以て当該米国暫定特許出願第６２／１８３１０５号の全容を本願に繰り入れる。 (Mutual reference to related applications)
This application is an application claiming benefits under Article 119 (e) of the US Patent Act based on US Provisional Patent Application No. 62/183105 dated June 22, 2015. With this reference, the entire contents of the US Provisional Patent Application No. 62/183105 are incorporated into the present application.

研磨薄板例えばシリコンウェハ等は現代技術の極重要な構成部分である。ウェハは、例えば、集積回路その他のデバイスの製造に用いられる半導体素材薄片と呼べるものである。研磨薄板の他例としては磁気ディスク基板、ゲージブロック等があろう。本願記載の技術では主にウェハを参照しているが、ご理解頂けるように、同技術は他種研磨板にも遜色なく適用することができる。本件開示では語「ウェハ」と語「研磨薄板」を可換的に用いうる。 Polished thin plates such as silicon wafers are extremely important components of modern technology. Wafers can be called, for example, semiconductor material flakes used in the manufacture of integrated circuits and other devices. Other examples of polished thin plates include magnetic disk substrates and gauge blocks. The technique described in the present application mainly refers to a wafer, but as you can see, this technique can be applied to other types of polishing plates as well. In the present disclosure, the terms "wafer" and "polished thin plate" can be used interchangeably.

半導体デバイスの製造においては、通常、多数の半導体製造プロセスを用い基板例えば半導体ウェハが処理される。例えば、リソグラフィなる半導体製造プロセスにおいては、半導体ウェハ上に配されたレジストへとレティクルからパターンが転写される。半導体製造プロセスの別例としては、これに限られるものではないが、化学機械研磨、エッチング、堆積・成長及びイオン注入がある。 In the manufacture of semiconductor devices, substrates such as semiconductor wafers are usually processed using a large number of semiconductor manufacturing processes. For example, in a semiconductor manufacturing process called lithography, a pattern is transferred from a reticle to a resist arranged on a semiconductor wafer. Other examples of semiconductor manufacturing processes include, but are not limited to, chemical mechanical polishing, etching, deposition / growth and ion implantation.

米国特許出願公開第２０１５／０１２０２１６号U.S. Patent Application Publication No. 2015/0120216

Monitoring Process-Induced Overlay Errors through High-Resolution Wafer Geometry Measurements, Kevin Turner et al., Proceedings of SPIE, Vol. 9050, p. 905013, 2014Monitoring Process-Induced Overlay Errors through High-Resolution Wafer Geometry Measurements, Kevin Turner et al., Proceedings of SPIE, Vol. 9050, p. 905013, 2014 Determining Local Residual Stresses from High Resolution Wafer Geometry Measurements, J. Gong et al., Journal of Vacuum Science & Technology B (JVST B) 31 , 051205, 2013Determining Local Residual Stresses from High Resolution Wafer Geometry Measurements, J. Gong et al., Journal of Vacuum Science & Technology B (JVST B) 31, 051205, 2013

一般に、ウェハの平坦性及び厚み不均一性については何らかの条件が定められる。しかしながら、様々な処理工程が製造中に実行される結果、ウェハ上に成長した薄膜内で応力変化が生じて弾性変形が起こり、それによって顕著な歪み例えば面内歪み（ＩＰＤ）及び／又は面外歪み（ＯＰＤ）が引き起こされることがある。そうした歪みは下流プロセスでの誤差・エラーにつながりうる。例えば、歪みがリソグラフィ的パターニング等でのオーバレイ誤差につながることがある。 In general, some conditions are set for the flatness and thickness non-uniformity of the wafer. However, as a result of various processing steps being performed during manufacturing, stress changes occur within the thin film grown on the wafer, causing elastic deformation, which results in significant strains such as in-plane strain (IPD) and / or out-of-plane. Distortion (OPD) can be caused. Such distortion can lead to errors in downstream processes. For example, distortion can lead to overlay errors in lithographic patterning and the like.

半導体製造中の非対称オーバレイ誤差シグネチャも観測されてきた。ここでいう非対称性は、その定義によれば、回転対称から逸脱したシグネチャのことである。例えば、オーバレイシグネチャが全対称又は軸対称であると言えるのは、そのオーバレイ誤差がウェハ径方向沿いに変化する一方で、所与の径方向位置ではそのウェハ上での角度位置によらずオーバレイ誤差値が同じである場合である。オーバレイ誤差シグネチャのうち軸対称から逸脱する成分のことを非対称成分／シグネチャと呼んでいる。こうした非対称シグネチャの多くが、古典的及び進歩的リソグラフィスキャナをベースにしたオーバレイ補正諸策では補正できない傾向を呈することに、注意すべきである。そうした非対称シグネチャは、膜堆積、熱アニーリング等、様々なプロセスツールにより誘起されうる。ここには、それら非対称シグネチャにより引き起こされうる潜在的問題を解決する上で助力となるシステム及び方法への需要が存在している。 Asymmetric overlay error signatures during semiconductor manufacturing have also been observed. Asymmetry here, by definition, is a signature that deviates from rotational symmetry. For example, an overlay signature can be said to be totally symmetric or axisymmetric because its overlay error varies along the radial direction of the wafer, while at a given radial position, the overlay error is independent of the angular position on the wafer. If the values are the same. The component of the overlay error signature that deviates from the axisymmetric component is called the asymmetric component / signature. It should be noted that many of these asymmetric signatures tend to be uncorrectable with overlay correction measures based on classical and progressive lithography scanners. Such asymmetric signatures can be induced by a variety of process tools such as membrane deposition and thermal annealing. There is a demand for systems and methods that can help solve the potential problems posed by these asymmetric signatures.

本件開示のある実施形態は方向を指向している。本方法は、ウェハが製造プロセスに供される前にそのウェハの第１組のウェハ幾何計測結果(wafer geometry measurements)を取得するステップと、その製造プロセスの後にそのウェハの第２組のウェハ幾何計測結果を取得するステップと、第１組のウェハ幾何計測結果及び第２組のウェハ幾何計測結果に基づき幾何変化マップ(geometry-change map)を算出するステップと、その製造プロセスによってウェハ幾何に誘起された非対称成分を検出すべく幾何変化マップを分析するステップと、その製造プロセスによって誘起された非対称オーバレイ誤差をウェハ幾何にて検出された非対称成分に基づき推定するステップと、を有するものとされうる。 Some embodiments disclosed in this case are directional. The method involves obtaining a first set of wafer geometry measurements of the wafer before it is subjected to the manufacturing process, and a second set of wafer geometry of the wafer after the manufacturing process. Induced to wafer geometry by the step of acquiring the measurement result, the step of calculating the geometry-change map based on the first set of wafer geometry measurement results and the second set of wafer geometry measurement results, and the manufacturing process. It may have a step of analyzing the geometric change map to detect the asymmetric component, and a step of estimating the asymmetric overlay error induced by the manufacturing process based on the asymmetric component detected in the wafer geometry. ..

本件開示の更なる実施形態もまた方法を指向している。本方法は、ウェハが製造プロセスに供される前にそのウェハの第１組のウェハ幾何計測結果を取得するステップと、その製造プロセスの後にそのウェハの第２組のウェハ幾何計測結果を取得するステップと、第１組のウェハ幾何計測結果及び第２組のウェハ幾何計測結果に基づき幾何変化マップを算出するステップと、幾何変化マップに少なくとも部分的に基づきそのウェハの面内歪みマップ(in-plane distortion map)及び局所形状曲率マップ(local shape curvature map)のうち少なくとも一方を生成するステップと、そのウェハの面内歪みマップ及び局所形状曲率マップのうち少なくとも一方に少なくとも部分的に基づきプロセス誘起非対称成分(process-induced asymmetric component)を検出するステップと、を有するものとされうる。 Further embodiments of the disclosure are also method oriented. In this method, the step of acquiring the wafer geometry measurement result of the first set of the wafer before the wafer is subjected to the manufacturing process and the wafer geometry measurement result of the second set of the wafer after the manufacturing process are acquired. A step, a step of calculating a geometric change map based on the first set of wafer geometric measurement results and a second set of wafer geometric measurement results, and an in-plane strain map of the wafer based at least partially on the geometric change map (in- Process-induced asymmetry based on at least one of the plane distortion map and the local shape curvature map, and at least one of the wafer's in-plane strain map and the local shape curvature map. It may have a step of detecting a process-induced asymmetric component.

本件開示のもう一つの実施形態はシステムを指向している。本システムは、ウェハが製造プロセスに供される前にそのウェハの第１組のウェハ幾何計測結果を取得するよう、且つその製造プロセスの後にそのウェハの第２組のウェハ幾何計測結果を取得するよう構成された、幾何計測ツールを備えうる。本システムは、また、その幾何計測ツールと通信するプロセッサを備えうる。そのプロセッサは、第１組のウェハ幾何計測結果及び第２組のウェハ幾何計測結果に基づき幾何変化マップを算出するよう、その製造プロセスによってウェハ幾何に誘起された非対称成分を検出すべく幾何変化マップを分析するよう、且つその製造プロセスによって誘起された非対称オーバレイ誤差をウェハ幾何にて検出された非対称成分に基づき推定するよう、構成されうる。 Another embodiment of the disclosure is system oriented. The system acquires the wafer geometry measurement results of the first set of wafers before the wafer is subjected to the manufacturing process, and acquires the wafer geometry measurement results of the second set of wafers after the manufacturing process. It may be equipped with a geometric measurement tool configured as such. The system may also be equipped with a processor that communicates with its geometric measurement tool. The processor calculates the geometric change map based on the first set of wafer geometric measurement results and the second set of wafer geometric measurement results, and the geometric change map is used to detect the asymmetric component induced in the wafer geometry by the manufacturing process. Can be configured to analyze and estimate the asymmetric overlay error induced by the manufacturing process based on the asymmetric components detected in the wafer geometry.

ご理解頂けるように、上掲の概述及び後掲の詳述は共に専ら例示的且つ説明的なものであり、本件開示を必然的に限定するものではない。添付図面は明細書に組み込まれその一部を構成するものであり、本件開示の主題を描出している。明細書及び図面には、相俟って本件開示の諸原理を説明する働きがある。 As you can see, both the above description and the details below are merely exemplary and descriptive and do not necessarily limit the disclosure of this case. The accompanying drawings are incorporated into the specification and form a part thereof, and depict the subject matter of the present disclosure. The specifications and drawings together serve to explain the principles of the Disclosure.

本件開示の多様な長所については、本件技術分野に習熟した者（いわゆる当業者）には、以下の如き添付図面を参照することでより好適に理解頂けよう。 Those who are familiar with the technical field (so-called those skilled in the art) will be able to better understand the various advantages of the Disclosure by referring to the attached drawings as shown below.

製造プロセスを示すブロック図である。It is a block diagram which shows the manufacturing process. パターン化ウェハ幾何計測を用いプロセス誘起非対称シグネチャを検出する方法の一実施形態を示すフロー図である。It is a flow diagram which shows one Embodiment of the method of detecting a process-induced asymmetric signature using the patterned wafer geometry measurement. パターン化ウェハ幾何計測を用いプロセス誘起非対称シグネチャを検出及び定量する方法の一実施形態を示すフロー図である。FIG. 5 is a flow diagram illustrating an embodiment of a method of detecting and quantifying process-induced asymmetric signatures using patterned wafer geometry measurement. 本件開示に従い構成された方法を利用し取得した非対称性検出及び定量結果の例示的ケースを示す図である。It is a figure which shows the example case of the asymmetry detection and quantification result obtained by using the method constructed in accordance with this disclosure. 本件開示に従い構成されたプロセス誘起非対称性検出、定量及び制御システムの一実施形態を示すブロック図である。FIG. 5 is a block diagram showing an embodiment of a process-induced asymmetry detection, quantification and control system configured in accordance with the present disclosure.

以下、添付図面に示した被開示主題について詳細に説明する。 Hereinafter, the subject to be disclosed shown in the attached drawings will be described in detail.

本件開示の諸実施形態は、パターン化ウェハ幾何計測を用いプロセス誘起非対称シグネチャを検出、定量及び制御するシステム及び方法を指向している。より具体的には、ウェハ幾何計測を利用しプロセス誘起オーバレイ及び応力を評価しうるものである。高分解能（例．２００μｍ平方画素以下）且つほぼ無歪みな（例．ウェハを鉛直保持することで達成される）ウェハ幾何計測を用い、検出プロセスを開発することで、懸念のある処理工程Ｐｎ＋１により下流オーバレイ誤差中に非対称シグネチャが引き起こされそうなことを、（図１に示す如き）検出ラインにて検出することが可能となる。この検出プロセスは、更に、非対称性の度合及びオーバレイに対するその影響を定量するよう構成することができる。考えるに、非対称シグネチャを検出及び定量しうる能力をこうして付すことで、（例．リソグラフィのさなかに）歴然となるよりだいぶ前に潜在的諸問題を捉えることが可能になるほか、実現形態によっては、非対称性を引き起こしている処理工程Ｐｎ＋１を再最適化すること及びウェハをリワークすることができ、それをサイクルタイム及びコストの顕著な節約につなげることができる。 The embodiments disclosed in the present disclosure are directed to systems and methods for detecting, quantifying and controlling process-induced asymmetric signatures using patterned wafer geometry measurements. More specifically, process-induced overlays and stresses can be evaluated using wafer geometry measurement. By developing a detection process using wafer geometry measurement with high resolution (eg 200 μm square pixels or less) and almost distortion-free (eg achieved by holding the wafer vertically), the processing process P n + 1 of concern This makes it possible to detect on the detection line (as shown in FIG. 1) that an asymmetric signature is likely to be caused during the downstream overlay error. This detection process can also be configured to quantify the degree of asymmetry and its effect on overlays. Thinking about it, this ability to detect and quantify asymmetric signatures makes it possible to capture potential problems long before they become apparent (eg, in the middle of lithography), and in some implementations. The processing step P n + 1 causing the asymmetry can be reoptimized and the wafer can be reworked, which can lead to significant savings in cycle time and cost.

まず、図２は、パターン化ウェハ幾何計測を用いプロセス誘起非対称シグネチャを検出する方法２００の一実施形態を示すフロー図である。本件開示によれば、ウェハ幾何ツールを利用し、所与ウェハのウェハ幾何を（図１中で工程Ｐｎ＋１として記されている）処理工程の前（ステップ２０２）及び後（ステップ２０４）に計測することができる。考えるに、このウェハ幾何ツールは、半導体ウェハの幾何を計測可能ないずれのウェハ幾何計測システムを有するものでもよい。なお、語「ウェハ幾何」は、ウェハの前面高、背面高、厚み変動、平坦性等や、それらのあらゆる帰結派生物・導関数、例えば形状、形状差、ナノトポグラフィ等を包含しうる語である。ある種の実施形態では、ＫＬＡ−Ｔｅｎｃｏｒにより提供されているＷａｆｅｒＳｉｇｈｔＰＷＧ(Patterned Wafer Geometry)システムが、ウェハ幾何ツールとして利用されることとなろう。とはいえ、ご理解頂けるように他種ウェハ幾何計測ツールを利用してもよいのであり、それにより本件開示の神髄及び技術的範囲から離隔するものではない。 First, FIG. 2 is a flow chart showing an embodiment of a method 200 for detecting a process-induced asymmetric signature using patterned wafer geometric measurement. According to the present disclosure, the wafer geometry of a given wafer is measured before (step 202) and after (step 204) the processing step ( denoted as step Pn + 1 in FIG. 1) using a wafer geometry tool. can do. Considerably, the wafer geometry tool may have any wafer geometry measurement system capable of measuring the geometry of semiconductor wafers. The term "wafer geometry" is a term that can include the front height, back height, thickness variation, flatness, etc. of the wafer, and all of these consequential derivatives / derivatives, such as shape, shape difference, nanotopography, etc. is there. In certain embodiments, the WaferSightPWG (Patterned Wafer Geometry) system provided by KLA-Tencor will be utilized as a wafer geometry tool. However, as you can see, other types of wafer geometry measurement tools may be used, which does not depart from the essence and technical scope of the present disclosure.

ステップ２０２及び２０４にてウェハの幾何計測結果を得た暁には、ステップ２０６にてそれら二組の計測結果間の差異を算出することができる。その結果得られるのは幾何変化（又は形状変化）マップと呼びうるものであり、次いでそれを子細に分析することで更なる情報を取得することができる。例えば、その形状変化マップの一次導関数を（ステップ２０８に示す如く）求めることで、（例．ｘ方向及びｙ方向に沿った）表面勾配の変化に関する情報を得ることができる。その後は、ステップ２１０にて、その表面勾配変化に基づき面内歪み（ＩＰＤ）を算出することができる；これには、「ウェハ幾何指標を用いたオーバレイ及び半導体プロセス制御」(Overlay and Semiconductor Process Control Using a Wafer Geometry Metric)と題しこの参照を以てその全容が本願に繰り入れられるところの２０１２年５月２１日付米国特許出願第１３／４７６３２８号に記載のそれの如き技術を利用する。ご理解頂けるように、他の高次形状ベースモデルを利用しＩＰＤを算出してもよいのであり、それにより本件開示の神髄及び技術的範囲から離隔するものではない。 When the geometric measurement results of the wafer are obtained in steps 202 and 204, the difference between the two sets of measurement results can be calculated in step 206. The result is what can be called a geometric change (or shape change) map, which can then be analyzed in detail to obtain more information. For example, by finding the first derivative of the shape change map (as shown in step 208), information about changes in surface gradient (eg, along the x and y directions) can be obtained. After that, in step 210, the in-plane strain (IPD) can be calculated based on the change in the surface gradient; for this, "Overlay and Semiconductor Process Control using the wafer geometric index" (Overlay and Semiconductor Process Control). Using a Wafer Geometry Metric), a technique such as that described in US Patent Application No. 13/476328 dated May 21, 2012, of which the whole picture is incorporated herein by reference. As you can see, the IPD may be calculated using other higher-order shape-based models, which does not depart from the essence and technical scope of the present disclosure.

ＩＰＤが算出された暁には、ステップ２１２にて、そのＩＰＤマップ内での対称性を分析することにより非対称性を推定することができる。考えるに、この対称性分析は、多項式例えばゼルニケ多項式等をそのＩＰＤマップに当てはめ、軸対称成分をゼロに設定する（即ち後に詳述するプロセスにより軸対称成分をヌル化する）ことによって、実行することができる。これに代え及び／又は加え、多項式をＩＰＤマップに当てはめることで高次留数を取得し、より低次な項のうち幾つかをゼロに設定することによっても、対称性分析を実行することができる。いずれの手法でも、対称性分析の最終結果となるのは濾過ＩＰＤマップ(filtered IPD map)であり、これはＩＰＤマップに関する非対称性情報を指し示すものとなりうる。そして、その濾過ＩＰＤマップ（ＩＰＤベース非対称性マップとも称しうる）に基づき非対称性の影響を評価し、報告／可視表現することができる。 When the IPD is calculated, the asymmetry can be estimated by analyzing the symmetry in the IPD map in step 212. Considerably, this symmetry analysis is performed by fitting a polynomial, such as a Zernike polynomial, to its IPD map and setting the axisymmetric component to zero (ie, nullifying the axisymmetric component by a process detailed below). be able to. Alternatively and / or in addition, symmetry analysis can also be performed by applying polynomials to the IPD map to obtain higher-order residues and setting some of the lower-order terms to zero. it can. In either method, the final result of the symmetry analysis is a filtered IPD map, which can point to asymmetry information about the IPD map. Then, the influence of asymmetry can be evaluated and reported / visually expressed based on the filtered IPD map (which can also be referred to as an IPD-based asymmetry map).

ご理解頂けるように、図２に形状勾配変化留数ベースＩＰＤ算出プロセスを示したが、これは算出プロセスの例示に過ぎず限定を意味するものではない。考えるに、他のＩＰＤ算出技術、例えば非特許文献１（この参照を以てその全容を本願に繰り入れることにする）に記載の有限要素モデリングベースＩＰＤ（ＦＥ−ＩＰＤ）のほか、本願にて具体的に言及していないその他のＩＰＤ算出技術を利用し、ＩＰＤを算出してもよいのであり、それにより本件開示の神髄及び技術的範囲から離隔するわけではない。 As you can see, Fig. 2 shows the shape gradient change residue-based IPD calculation process, but this is only an example of the calculation process and does not mean any limitation. Considering that, in addition to other IPD calculation techniques, for example, the finite element modeling-based IPD (FE-IPD) described in Non-Patent Document 1 (the whole of which is incorporated into the present application by reference), specifically in the present application. IPD may be calculated using other IPD calculation techniques not mentioned, which does not depart from the essence and technical scope of the present disclosure.

なお、ＩＰＤマップを対象にして対称性分析を実行することで、ある処理工程が潜在的に非対称性を誘起しうるか否かにつき非常に有用な予測結果がもたらされうるものの、ＩＰＤマップを用いるだけでは、非対称性の度合及びオーバレイに対するその影響を正確に定量するのに十分な情報を得られないことがありうる。従って、ある種の実現形態に従い、ＩＰＤ指標及び局所形状曲率（ＬＳＣ）指標を組み合わせ併用することで、非対称性の度合及びオーバレイに対するその影響を定量する助けとした方がよい。 It should be noted that performing a symmetry analysis on an IPD map can provide very useful predictions as to whether a processing process can potentially induce asymmetry, but an IPD map is used. Alone may not provide sufficient information to accurately quantify the degree of asymmetry and its effect on overlays. Therefore, the combination of the IPD index and the local shape curvature (LSC) index should be used in combination to help quantify the degree of asymmetry and its effect on overlays, according to certain implementations.

ＬＳＣ指標は、非特許文献２（この参照を以てその全容を本願に繰り入れることにする）に記載の如く、プロセス誘起応力の予測子として用いうる形状曲率変化指標である。図３は、そうした形状曲率変化指標を取得する方法３００の一実施形態を示すフロー図である。 The LSC index is a shape / curvature change index that can be used as a predictor of process-induced stress, as described in Non-Patent Document 2 (the whole of which will be incorporated into the present application with reference to this). FIG. 3 is a flow chart showing an embodiment of the method 300 for acquiring such a shape curvature change index.

より具体的には、ウェハ幾何ツールを利用し、所与ウェハのウェハ幾何を処理工程の前（ステップ３０２）及び後（ステップ３０４）に計測することができる。ステップ３０２及び３０４にてウェハの幾何計測結果が得られた暁には、ステップ３０６にてそれら二組の計測結果間の差異を算出することができる。その結果得られるのは形状変化マップと呼びうるものであり、その形状変化マップの二次導関数を求めることで局所形状曲率（ＬＳＣ）の変化に関する情報を得ること、ひいてはステップ３０８に示す如くＬＳＣマップをもたらすことができる。 More specifically, the wafer geometry tool can be used to measure the wafer geometry of a given wafer before (step 302) and after (step 304) the processing step. When the geometric measurement results of the wafer are obtained in steps 302 and 304, the difference between the two sets of measurement results can be calculated in step 306. The result is what can be called a shape change map, and by obtaining the quadratic derivative of the shape change map, information on changes in local shape curvature (LSC) can be obtained, and by extension, LSC as shown in step 308. Can bring a map.

考えるに、ＬＳＣマップを対象にして対称性分析を実行することで、非対称性を推定することができる。例えば、ステップ３１０にて、多項式例えばゼルニケ多項式等をＬＳＣマップに当てはめればよい。ステップ３１２では、この当てはめ処理を経て得られる軸対称成分（例．Ｚ０ ２，Ｚ０ ４，…）を非軸対称成分から分離させることができる。軸対称成分が除去されたＬＳＣマップはＬＳＣベース非対称性マップと呼びうるものであり、ステップ３１４にてそれを子細に処理することで非対称成分を定量することができる。 Considering that, asymmetry can be estimated by performing a symmetry analysis on the LSC map. For example, in step 310, a polynomial such as a Zernike polynomial may be applied to the LSC map. In step 312, it is possible to separate the axisymmetric component obtained through this fitting process (Example .Z 0 2, Z 0 4, ...) from the non-axisymmetric components. The LSC map from which the axisymmetric component has been removed can be called an LSC-based asymmetry map, and the asymmetric component can be quantified by processing it in detail in step 314.

ある種の実現形態によれば、それら非対称成分を“非対称性因数”に基づき定量することができる。非対称性因数は、全多項式当てはめに対する非軸対称成分のウェイト（比重・荷重）として定義することができる。言い換えれば、所与の処理工程又は処理工程群により誘起された非対称性の度合を定める上で非対称性因数が助けとなりうる。 According to certain implementations, these asymmetric components can be quantified based on an "asymmetric factor". The asymmetry factor can be defined as the weight (specific gravity / load) of the non-axisymmetric component for the all-polynomial fit. In other words, the asymmetry factor can help determine the degree of asymmetry induced by a given treatment step or group of treatment steps.

とはいえ、非対称性因数自体を知るだけでは、オーバレイに対する非対称性の影響を正確に定量するのに十分でないことに、注意すべきである。例えば高周波の視野内成分が存在している場合、通常はウェハレベル（低次）変動として定まる非対称性が、それら高周波成分によって支配及び曖昧化されることがままある。従って、高周波因数を非対称性因数と併用することでオーバレイに対する非対称性の影響を推定し、その高周波因数が過大な場合（所定のしきい値より大きい場合）に非対称性因数のウェイトを抑えるようにした方がよい。逆に、高周波因数が小さい場合は、非対称性因数のウェイトを定格通りとすればよい。高周波因数は、多項式当てはめでは捉え得ない留数として定義することができる。 However, it should be noted that knowing the asymmetry factor itself is not enough to accurately quantify the effect of asymmetry on overlays. For example, in the presence of high frequency in-field components, the asymmetry usually defined as wafer level (low order) variation is often dominated and obscured by these high frequency components. Therefore, by using the high frequency factor together with the asymmetric factor, the effect of asymmetry on the overlay is estimated, and when the high frequency factor is excessive (greater than a predetermined threshold value), the weight of the asymmetric factor is suppressed. You should do it. On the contrary, when the high frequency factor is small, the weight of the asymmetric factor may be set as rated. The high frequency factor can be defined as a residue that cannot be captured by polynomial fitting.

ある種の実現形態によれば、ＩＰＤを高周波因数として利用し、それを非対称性因数との組合せで用いることで、下流プロセスに対する非対称性の影響（例．オーバレイ誤差）を確認することができる。例えば、非対称性因数にＩＰＤの規模（例．標準偏差の３倍即ち３σ）を乗ずることで、オーバレイに対する非対称性の影響を推定することができる。この場合、ウェハが高度な非対称性を呈しえても、ＩＰＤの規模が小さければオーバレイに対する非対称性の影響が小さくなりうる。逆に、ウェハが低度な非対称性を呈することもあろうが、ＩＰＤの規模が大きければ、非対称性の影響は顕著なものになりうる。 According to certain implementations, the effect of asymmetry on downstream processes (eg, overlay error) can be identified by using IPD as a high frequency factor and using it in combination with an asymmetry factor. For example, the effect of asymmetry on overlays can be estimated by multiplying the asymmetry factor by the magnitude of the IPD (eg, 3 times the standard deviation or 3σ). In this case, even if the wafer can exhibit a high degree of asymmetry, the influence of the asymmetry on the overlay can be reduced if the scale of the IPD is small. Conversely, the wafer may exhibit a low degree of asymmetry, but if the IPD is large, the effect of the asymmetry can be significant.

ご理解頂けるように、ＩＰＤを高周波因数として利用しうるとはいえ、高周波因数としてのＩＰＤの利用には限定の意図はない。考えるに、他のウェハ幾何計測結果例えば形状、形状勾配、ナノトポグラフィ等を非対称性因数との組合せで利用することで、下流プロセスに対する非対称性の影響を確認してもよいのであり、上述の如く軸対称成分及び低周波成分が適切なフィルタリングで除去されている限りは、それにより本件開示の神髄及び技術的範囲から離隔するわけではない。 As you can see, although IPD can be used as a high frequency factor, there is no limitation in using IPD as a high frequency factor. Considering that, by using other wafer geometric measurement results such as shape, shape gradient, nanotopography, etc. in combination with the asymmetry factor, the influence of asymmetry on the downstream process may be confirmed, as described above. As long as the asymmetric and low frequency components are removed by proper filtering, it does not depart from the essence and technical scope of the present disclosure.

図４は、取得した非対称性検出及び定量結果の例示的ケースを示す図である。図４に示すように、本件開示に従いＬＳＣマップ４０２を処理することで、対応する非対称性マップと併せ、対応する非対称性因数４０４を得ることができる。そして、得られた非対称性マップ並びに非対称性因数４０４をＩＰＤ情報との組合せで利用することで、オーバレイに対する非対称性の影響を指し示すマップ４０６を生成することができる。考えるに、このマップ４０６をユーザ（例．プロセスエンジニア等）に提示することで、観測された非対称性シグネチャをユーザが視認する助けとすることができる。 FIG. 4 is a diagram showing an exemplary case of the acquired asymmetry detection and quantification results. As shown in FIG. 4, by processing the LSC map 402 in accordance with the present disclosure, the corresponding asymmetry factor 404 can be obtained together with the corresponding asymmetry map. Then, by using the obtained asymmetry map and the asymmetry factor 404 in combination with the IPD information, it is possible to generate a map 406 indicating the influence of the asymmetry on the overlay. Considering that, presenting this map 406 to the user (eg, process engineer, etc.) can help the user to see the observed asymmetry signature.

これに加え及び／又はこれに代え、マップ４０６をプロセス制御パラメタとして利用し、それをフィーフォワード又はフィードバックすることで、オーバレイ誤差の補正、根本原因分析、並びにプロセス制御最適化を実行することができる。例えば、ウェハ幾何を用いたウェハグルーピングのプロセスが、「オーバレイ誤差のフィードフォワード及びフィードバック補正、根本原因分析並びにプロセス制御のための統計的オーバレイ誤差予測」(Statistical Overlay Error Prediction for Feed Forward and Feedback Correction of Overlay Errors, Root Cause Analysis and Process Control)と題しこの参照を以てその全容が本願に繰り入れられる２０１４年３月２０日付米国特許出願第１４／２２０６６５号に記載されている。考えるに、ウェハ幾何を用いウェハを様々なウェハグループに分類するのに代え（又は加え）、非対称性マップを利用することでも、その分類プロセスを遜色なく実行することができる。考えるに、非対称性マップに基づくグルーピングはグルーピングの正確性を改善する助力となりえ、ひいてはオーバレイ誤差の補正、根本原因分析、並びにプロセス制御最適化を改善する助力となりうる。 In addition and / or instead, map 406 can be used as a process control parameter and fed back or fed back to perform overlay error correction, root cause analysis, and process control optimization. .. For example, the process of wafer grouping using wafer geometry is "Statistical Overlay Error Prediction for Feed Forward and Feedback Correction of" (Statistical Overlay Error Prediction for Feed Forward and Feedback Correction of). It is described in US Patent Application No. 14/220665 dated March 20, 2014, which is incorporated herein by reference in its entirety, entitled Overlay Errors, Root Cause Analysis and Process Control). Considering that, instead of (or adding) classifying wafers into various wafer groups using wafer geometry, the asymmetry map can also be used to perform the classification process as well. Given that, asymmetry map-based grouping can help improve grouping accuracy, which in turn can help improve overlay error correction, root cause analysis, and process control optimization.

図５は、パターン化ウェハ幾何計測を用いプロセス誘起非対称シグネチャを検出、定量及び制御するよう構成された検出システム５００を示すブロック図である。本検出システム５００には、所与ウェハ５０４のウェハ幾何を計測するよう構成されたウェハ幾何ツール５０２を具備させることができる。本検出システム５００には、そのウェハ幾何ツール５０２と通信するプロセッサ５０６をも具備させることができる。そのプロセッサ５０６は、上述した様々な分析方法を実行するよう構成することができる。考えるに、プロセッサ５０６は、スタンドアロン処理デバイスとしてもウェハ幾何ツール５０２の埋込／集積部材としても実現することができる。これもまた考えるに、プロセッサ５０６の出力を諸プロセスツール５０８に供給し、オーバレイ誤差の補正、根本原因分析、並びにプロセス制御最適化を上述の如く行わせることができる。 FIG. 5 is a block diagram showing a detection system 500 configured to detect, quantify, and control process-induced asymmetric signatures using patterned wafer geometry measurements. The detection system 500 can be equipped with a wafer geometry tool 502 configured to measure the wafer geometry of a given wafer 504. The detection system 500 can also be equipped with a processor 506 that communicates with the wafer geometry tool 502. The processor 506 can be configured to perform the various analytical methods described above. Considered, the processor 506 can be realized both as a stand-alone processing device and as an embedded / integrated member of the wafer geometry tool 502. Again, considering that the output of the processor 506 can be supplied to the process tools 508 to perform overlay error correction, root cause analysis, and process control optimization as described above.

考えるに、本件開示に係るシステム及び方法によりもたらされる長所は様々な用途で是認されうるものである。非対称性の検出及び定量双方をどの所与処理工程でも実行しうること、並びに何らオーバレイデータを必要とせず純粋にウェハ幾何に基づき推定を実行しうることに、注目すべきである。実質的に無歪みなウェハ幾何計測結果をチャック無しで且つ高空間分解能設定にて得られるので、かなり低レートな空間サンプリングしか可能でない従来の真空チャック使用型リソグラフィスキャナに比べ、非対称性推定の正確性を改善しうることにも、注目すべきである。 Given that, the advantages provided by the systems and methods involved in this disclosure can be endorsed in a variety of applications. It should be noted that both asymmetry detection and quantification can be performed in any given processing step, and that estimation can be performed purely on wafer geometry without the need for any overlay data. Since the wafer geometry measurement result with virtually no distortion can be obtained without a chuck and with a high spatial resolution setting, the asymmetry estimation is more accurate than the conventional vacuum chuck-based lithography scanner that can only perform spatial sampling at a considerably low rate. It should also be noted that it can improve sex.

考えるに、上掲の例のうち幾つかにてある特定のプロセスツールに言及しているが、本件開示に係るシステム及び方法は他種プロセスツールにも適用可能で、その場合も高分解能計測による利益を享受しうるのであり、それにより本件開示の神髄及び技術的範囲から離隔するわけではない。加えて、考えるに、本件開示にて用いられている語「ウェハ」は、集積回路その他のデバイスの製造に当たり用いられる半導体素材薄片のみならず、他の研磨薄板例えば磁気ディスク基板、ゲージブロック等をも包含しうる語である。 Considering that, although some of the above examples refer to certain process tools, the systems and methods involved in this disclosure are also applicable to other types of process tools, also by high resolution measurement. You can enjoy the benefits, which does not depart from the essence and technical scope of this disclosure. In addition, it is considered that the term "wafer" used in the present disclosure refers not only to semiconductor material flakes used in the manufacture of integrated circuits and other devices, but also to other polished flakes such as magnetic disk substrates and gauge blocks. Is also a word that can be included.

本願記載の方法は、様々なウェハ幾何計測ツールにて、１個又は複数個のプロセッサにより実行される命令群として実現すること、また単一の生産装置内で及び／又は複数個の生産装置を過ぎり実行することが可能である。更に、本願記載の方法における諸ステップの具体的な順序や階層性が例示的手法の例示であることをご理解頂けよう。ご理解頂けるように、同方法における諸ステップの具体的な順序や階層性は設計上の嗜好に基づき配置換えすることが可能であり、そうしたものも本件開示の技術的範囲及び神髄の枠内に留まるものである。別項の方法請求項では諸ステップの構成要素が見本的順序で提示されているのであり、提示されている具体的な順序又は階層性への限定を必ずしも意図していない。 The method described in the present application is realized as a group of instructions executed by one or more processors by various wafer geometry measurement tools, and in a single production device and / or a plurality of production devices. It is possible to run past. Furthermore, it should be understood that the specific order and hierarchy of the steps in the method described in the present application is an example of the exemplary method. As you can see, the specific order and hierarchy of the steps in the method can be rearranged based on design preferences, which are also within the technical scope and essence of the Disclosure. It stays. In the method claim of another paragraph, the components of the steps are presented in a sample order, and are not necessarily intended to be limited to the specific order or hierarchy presented.

思うに、本件開示のシステム及び方法及びそれに付随する長所の多くを上掲の記述によってご理解頂けるであろうし、被開示主題から離隔することなく又はその主要な長所を全て損なうことなく構成部材の形態、構成及び配置に様々な変形を施しうることは明らかであろう。記述されている形態は単なる説明用のものである。
I think you can understand many of the systems and methods of the Disclosure and its associated advantages by the above description, and of the components without separating from the subject to be disclosed or without compromising all of its major advantages. It will be clear that various modifications can be made to the morphology, composition and arrangement. The forms described are for illustration purposes only.

Claims (23)

ウェハが製造プロセスに供される前にそのウェハの第１組のウェハ幾何計測結果(wafer geometry measurements)を取得するステップと、
上記製造プロセスの後に上記ウェハの第２組のウェハ幾何計測結果を取得するステップと、
第１組のウェハ幾何計測結果及び第２組のウェハ幾何計測結果に基づき幾何変化マップ(geometry-change map)を算出するステップと、
上記製造プロセスによってウェハ幾何に誘起された非対称成分を検出すべく幾何変化マップを分析するステップと、
上記製造プロセスによって誘起された非対称オーバレイ誤差を、ウェハ幾何にて検出された上記非対称成分に基づき推定するステップと、
を有し、上記分析ステップが、更に、
幾何変化マップに少なくとも部分的に基づき上記ウェハの面内歪みを算出するステップと、
上記ウェハの面内歪みから対称成分を除去することで濾過面内歪みマップ(filtered in-plane distortion map)を生成するステップと、
濾過面内歪みマップに少なくとも部分的に基づき上記非対称成分を検出するステップと、
を含む方法。 The steps to obtain the first set of wafer geometry measurements for a wafer before it is put into the manufacturing process, and
After the manufacturing process, the step of acquiring the wafer geometric measurement result of the second set of the wafers and
Steps to calculate a geometry-change map based on the first set of wafer geometry measurement results and the second set of wafer geometry measurement results, and
The steps to analyze the geometric change map to detect the asymmetric components induced in the wafer geometry by the above manufacturing process,
A step of estimating the asymmetric overlay error induced by the manufacturing process based on the asymmetric component detected in the wafer geometry, and
It has a said analysis step further,
The step of calculating the in-plane strain of the wafer based on the geometric change map at least partially, and
A step of generating a filtered in-plane distortion map by removing a symmetric component from the in-plane strain of the wafer,
The step of detecting the asymmetric component based at least partially on the in-plane strain map,
How to include . 請求項１記載の方法であって、更に、
第１組のウェハ幾何計測結果及び第２組のウェハ幾何計測結果に基づき局所形状曲率マップ(local shape curvature map)を生成するステップと、
局所形状曲率マップに少なくとも部分的に基づき上記非対称成分を検出するステップと、
を有する方法。 The method according to claim 1, further
A step to generate a local shape curvature map based on the first set of wafer geometry measurement results and the second set of wafer geometry measurement results, and
The step of detecting the asymmetric component based at least partially on the local shape curvature map,
Method to have. 請求項２記載の方法であって、上記非対称成分検出ステップが、更に、
局所形状曲率マップから対称成分を除去することで濾過局所形状曲率マップ(filtered local shape curvature map)を生成するステップと、
濾過局所形状曲率マップに少なくとも部分的に基づき上記非対称成分を検出するステップと、
を含む方法。 The method according to claim 2, wherein the asymmetric component detection step is further performed.
Steps to generate a filtered local shape curvature map by removing the symmetric component from the local shape curvature map,
The step of detecting the asymmetric component based at least partially on the filtration local shape curvature map,
How to include. 請求項３記載の方法であって、更に、
オーバレイに対する上記非対称成分の影響を定量するステップを有する方法。 The method according to claim 3, further
A method comprising the step of quantifying the effect of the asymmetric component on the overlay. 請求項４記載の方法であって、上記定量ステップが、更に、
局所形状曲率マップ内に含まれる非対称成分のウェイトに基づき非対称性因数(asymmetry factor)を特定するステップと、
上記ウェハの面内歪みの規模を判別するステップと、
オーバレイに対する上記非対称成分の影響を、非対称性因数と上記ウェハの面内歪みの規模との積に基づき定量するステップと、
を含む方法。 The method according to claim 4, wherein the quantification step is further performed.
Steps to identify the asymmetry factor based on the weights of the asymmetric components contained in the local shape curvature map, and
Steps to determine the magnitude of in-plane distortion of the wafer and
A step of quantifying the effect of the asymmetric component on the overlay based on the product of the asymmetry factor and the magnitude of the in-plane strain of the wafer.
How to include. 請求項５記載の方法であって、更に、
濾過面内歪みマップ、濾過局所形状曲率マップ、並びにオーバレイに対する上記非対称成分の影響、のうち少なくとも１個に基づき、上記ウェハを複数個のウェハグループのうち１個へと分類するステップを有する方法。 The method according to claim 5, further
A method comprising the steps of classifying the wafer into one of a plurality of wafer groups based on at least one of a filtration plane strain map, a filtration local shape curvature map, and the effect of the asymmetric component on the overlay. 請求項５記載の方法であって、更に、
上記製造プロセスを実行した製造プロセスツールを制御するフィードバック制御手段に、濾過面内歪みマップ、濾過局所形状曲率マップ、並びにオーバレイに対する上記非対称成分の影響、のうち少なくとも１個を通知するステップを、有する方法。 The method according to claim 5, further
The feedback control means that controls the manufacturing process tool that performed the manufacturing process has a step of notifying at least one of a filtration plane strain map, a filtration local shape curvature map, and the effect of the asymmetric component on the overlay. Method. 請求項５記載の方法であって、更に、
後続の製造プロセスツールを制御するフィードフォワード制御手段に、濾過面内歪みマップ、濾過局所形状曲率マップ、並びにオーバレイに対する上記非対称成分の影響、のうち少なくとも１個を通知するステップを、有する方法。 The method according to claim 5, further
A method comprising a step of notifying the feedforward control means controlling the subsequent manufacturing process tool of at least one of an in-plane strain map, a filtration local shape curvature map, and the effect of the asymmetric component on the overlay. ウェハが製造プロセスに供される前にそのウェハの第１組のウェハ幾何計測結果を取得するステップと、
上記製造プロセスの後に上記ウェハの第２組のウェハ幾何計測結果を取得するステップと、
第１組のウェハ幾何計測結果及び第２組のウェハ幾何計測結果に基づき幾何変化マップを算出するステップと、
幾何変化マップに少なくとも部分的に基づき上記ウェハの面内歪みマップ及び局所形状曲率マップのうち少なくとも一方を生成するステップと、
上記ウェハの面内歪みマップ及び局所形状曲率マップのうち少なくとも一方に少なくとも部分的に基づきプロセス誘起非対称成分(process-induced asymmetric component)を検出するステップと、
を有する方法。 The step of acquiring the wafer geometry measurement result of the first set of wafers before the wafer is put into the manufacturing process,
After the manufacturing process, the step of acquiring the wafer geometric measurement result of the second set of the wafers and
Steps to calculate a geometric change map based on the first set of wafer geometry measurement results and the second set of wafer geometry measurement results, and
A step of generating at least one of the in-plane strain map and the local shape curvature map of the wafer based on the geometric change map at least partially.
A step of detecting a process-induced asymmetric component based at least partially on at least one of the in-plane strain map and the local shape curvature map of the wafer.
Method to have. 請求項９記載の方法であって、上記プロセス誘起非対称成分検出ステップが、更に、
局所形状曲率マップから対称成分を除去することで濾過局所形状曲率マップを生成するステップと、
濾過局所形状曲率マップに少なくとも部分的に基づきプロセス誘起非対称成分を検出するステップと、
を含む方法。 The process-induced asymmetric component detection step according to claim 9, further.
The steps to generate a filtered local shape curvature map by removing the symmetric component from the local shape curvature map,
Steps to detect process-induced asymmetric components, at least partially based on the filtration local shape curvature map,
How to include. 請求項１０記載の方法であって、更に、
オーバレイに対するプロセス誘起非対称成分の影響を定量するステップを有する方法。 The method according to claim 10, further
A method having steps to quantify the effect of process-induced asymmetric components on overlays. 請求項１１記載の方法であって、オーバレイに対するプロセス誘起非対称成分の影響を定量する上記ステップが、更に、
局所形状曲率マップ内に含まれる非対称成分のウェイトに基づき非対称性因数を特定するステップと、
第１組のウェハ幾何計測結果及び第２組のウェハ幾何計測結果に基づき高周波因数(high-frequency factor)を特定するステップと、
オーバレイに対するプロセス誘起非対称成分の影響を、非対称性因数と高周波因数との積に基づき定量するステップと、
を含む方法。 The method of claim 11 further comprises the step of quantifying the effect of process-induced asymmetric components on overlays.
Steps to identify the asymmetry factor based on the weights of the asymmetric components contained in the local shape curvature map,
Steps to identify the high-frequency factor based on the wafer geometry measurement results of the first set and the wafer geometry measurement results of the second set,
Steps to quantify the effect of process-induced asymmetric components on overlays based on the product of the asymmetry factor and the high frequency factor,
How to include. 請求項１２記載の方法であって、上記高周波因数が上記ウェハの面内歪みの規模を含む方法。 The method according to claim 12, wherein the high frequency factor includes the magnitude of in-plane distortion of the wafer. 請求項１１記載の方法であって、更に、
オーバレイに対するプロセス誘起非対称成分の影響を、上記製造プロセスを実行した製造プロセスツールを制御するフィードバック制御手段に通知するステップを、有する方法。 The method according to claim 11, further
A method comprising the step of notifying the feedback control means controlling the manufacturing process tool performing the manufacturing process of the effect of the process-induced asymmetric component on the overlay. 請求項１１記載の方法であって、更に、
オーバレイに対するプロセス誘起非対称成分の影響を、後続の製造プロセスツールを制御するフィードフォワード制御手段に通知するステップを、有する方法。 The method according to claim 11, further
A method having a step of notifying a feedforward control means controlling a subsequent manufacturing process tool of the effect of a process-induced asymmetric component on an overlay. ウェハが製造プロセスに供される前にそのウェハの第１組のウェハ幾何計測結果を取得するよう、且つその製造プロセスの後にそのウェハの第２組のウェハ幾何計測結果を取得するよう、構成された幾何計測ツールと、
上記幾何計測ツールと通信するプロセッサと、
を備え、上記プロセッサが、
第１組のウェハ幾何計測結果及び第２組のウェハ幾何計測結果に基づき幾何変化マップを算出するよう、
上記製造プロセスによってウェハ幾何に誘起された非対称成分を検出すべく幾何変化マップを分析するよう、且つ
上記製造プロセスによって誘起された非対称オーバレイ誤差を、ウェハ幾何にて検出された上記非対称成分に基づき推定するよう、
構成され、上記プロセッサが、更に、
幾何変化マップに少なくとも部分的に基づき上記ウェハの面内歪みを算出するよう、
上記ウェハの面内歪みから対称成分を除去することで濾過面内歪みマップを生成するよう、且つ
濾過面内歪みマップに少なくとも部分的に基づき上記非対称成分を検出するよう、
構成されているシステム。 It is configured to obtain the wafer geometry measurement results of the first set of wafers before the wafer is subjected to the manufacturing process, and to obtain the wafer geometry measurement results of the second set of wafers after the manufacturing process. Geometric measurement tool and
A processor that communicates with the above geometric measurement tool,
The above processor is equipped with
To calculate the geometric change map based on the first set of wafer geometry measurement results and the second set of wafer geometry measurement results.
Analyze the geometric change map to detect the asymmetric component induced in the wafer geometry by the manufacturing process, and estimate the asymmetric overlay error induced by the manufacturing process based on the asymmetric component detected in the wafer geometry. To do
The above processor is further configured
To calculate the in-plane strain of the wafer, at least partially based on the geometric change map
To generate a filtration in-plane strain map by removing the symmetric component from the in-plane strain of the wafer, and
To detect the asymmetric component at least partially based on the in-plane strain map
The system that is configured . 請求項１６記載のシステムであって、上記プロセッサが、更に、
第１組のウェハ幾何計測結果及び第２組のウェハ幾何計測結果に基づき局所形状曲率マップを生成するよう、且つ
局所形状曲率マップに少なくとも部分的に基づき上記非対称成分を検出するよう、
構成されているシステム。 The system according to claim 16, wherein the processor further comprises.
To generate a local shape curvature map based on the results of the first set of wafer geometry measurement and the result of the second set of wafer geometry measurement, and to detect the asymmetric component based on at least a part of the local shape curvature map.
The system that is configured. 請求項１７記載のシステムであって、上記プロセッサが、更に、
局所形状曲率マップから対称成分を除去することで濾過局所形状曲率マップを生成するよう、且つ
濾過局所形状曲率マップに少なくとも部分的に基づき上記非対称成分を検出するよう、
構成されているシステム。 The system according to claim 17, wherein the processor further comprises.
To generate a filtered local shape curvature map by removing the symmetric component from the local shape curvature map, and to detect the asymmetric component at least partially based on the filtered local shape curvature map.
The system that is configured. 請求項１８記載のシステムであって、上記プロセッサが、更に、
オーバレイに対する上記非対称成分の影響を定量するよう、構成されているシステム。 The system according to claim 18, wherein the processor further comprises.
A system configured to quantify the effect of the asymmetric component on the overlay. 請求項１９記載のシステムであって、上記プロセッサが、更に、
局所形状曲率マップ内に含まれる非対称成分のウェイトに基づき非対称性因数を特定するよう、
上記ウェハの面内歪みの規模を判別するよう、且つ
オーバレイに対する上記非対称成分の影響を、非対称性因数と上記ウェハの面内歪みの規模との積に基づき定量するよう、
構成されているシステム。 The system according to claim 19, wherein the processor further comprises.
To identify the asymmetry factor based on the weights of the asymmetric components contained in the local shape curvature map
To determine the magnitude of the in-plane strain of the wafer and to quantify the effect of the asymmetric component on the overlay based on the product of the asymmetry factor and the magnitude of the in-plane strain of the wafer.
The system that is configured. 請求項２０記載のシステムであって、上記プロセッサが、更に、
濾過面内歪みマップ、濾過局所形状曲率マップ、並びにオーバレイに対する上記非対称成分の影響、のうち少なくとも１個に基づき、上記ウェハを複数個のウェハグループのうち１個へと分類するよう、構成されているシステム。 The system according to claim 20, wherein the processor further comprises.
The wafer is configured to be classified into one of a plurality of wafer groups based on at least one of the in-plane strain map, the filtration local shape curvature map, and the effect of the asymmetric component on the overlay. System. 請求項２０記載のシステムであって、上記プロセッサが、更に、
上記製造プロセスを実行した製造プロセスツールを制御するフィードバック制御手段に、濾過面内歪みマップ、濾過局所形状曲率マップ、並びにオーバレイに対する上記非対称成分の影響、のうち少なくとも１個を通知するよう、構成されているシステム。 The system according to claim 20, wherein the processor further comprises.
The feedback control means that controls the manufacturing process tool that performed the manufacturing process is configured to notify at least one of the in-plane strain map, the filtered local shape curvature map, and the effect of the asymmetric component on the overlay. System. 請求項２０記載のシステムであって、上記プロセッサが、更に、
後続の製造プロセスツールを制御するフィードフォワード制御手段に、濾過面内歪みマップ、濾過局所形状曲率マップ、並びにオーバレイに対する上記非対称成分の影響、のうち少なくとも１個を通知するよう、構成されているシステム。 The system according to claim 20, wherein the processor further comprises.
A system configured to notify the feedforward control means controlling subsequent manufacturing process tools of at least one of an in-plane strain map, a filtration local shape curvature map, and the effect of the asymmetric component on the overlay. ..
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