JP6781983B2 - Electronic devices and their manufacturing methods - Google Patents

Electronic devices and their manufacturing methods Download PDF

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JP6781983B2
JP6781983B2 JP2016154163A JP2016154163A JP6781983B2 JP 6781983 B2 JP6781983 B2 JP 6781983B2 JP 2016154163 A JP2016154163 A JP 2016154163A JP 2016154163 A JP2016154163 A JP 2016154163A JP 6781983 B2 JP6781983 B2 JP 6781983B2
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semiconductor circuit
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小林　健
健 小林
俊弘 竹下
俊弘 竹下
亮平 武井
亮平 武井
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National Institute of Advanced Industrial Science and Technology AIST
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本発明は電子デバイス及びその製造方法に係り、特にフレキシブルで極薄の電子デバイス及びその製造方法に関する。 The present invention relates to an electronic device and a method for manufacturing the same, and particularly to a flexible and ultrathin electronic device and a method for manufacturing the same.

近年、生体に装着して生体情報を検出するセンサデバイスが注目を集めており、中でも人体に装着する衣類型ウェアラブルデバイスが新たなエレクトロニクス市場を牽引していく電子デバイスとして期待されている。この種の衣類型ウェアラブルデバイスにとって重要視される点として、如何に違和感無く装着できるかという柔軟な構造を有したフレキシブル性があげられる。このフレキシブルな電子デバイスの作製技術として、従来より高伸縮配線やセンサなどをフレキシブル基板に印刷する印刷技術の開発が進められた。しかし、印刷技術では、センサから得られる信号を処理するマイクロコンピュータ（以下、「マイコン」と略す）や、数百ＭＨｚ帯で無線通信を行うためのＲＦ-ＩＣ(Radio Frequency Integrated Circuit)などは、作製が困難である（例えば、非特許文献１参照）。 In recent years, sensor devices that are attached to living organisms to detect biological information have been attracting attention, and among them, clothing-type wearable devices that are attached to the human body are expected as electronic devices that will drive the new electronics market. An important point for this type of clothing-type wearable device is its flexibility, which has a flexible structure of how it can be worn without discomfort. As a technology for manufacturing this flexible electronic device, the development of a printing technology for printing highly elastic wiring and sensors on a flexible substrate has been promoted. However, in printing technology, microcomputers (hereinafter abbreviated as "microcomputers") that process signals obtained from sensors and RF-ICs (Radio Frequency Integrated Circuits) for wireless communication in the hundreds of MHz band are used. It is difficult to produce (see, for example, Non-Patent Document 1).

そのため、現在ではシリコン（Ｓi）基板やＳＯＩ(Silicon On Insulation)基板の上にマイコンやＲＦ-ＩＣなどが集積回路化された半導体回路チップ（ＩＣチップ）を作製して薄化した後（例えば、非特許文献２，３参照）、それをフレキシブル基板上に接着して電子デバイスを製造する方法が採用されている。また、フレキシブルな電子デバイスに柔軟性を持たせ、フレキシブル基板の十分な屈曲性を有しつつＩＣチップの割れや剥離を防止するため、特許文献１にはＩＣチップを、その中央領域のみで接着層を介してフレキシブル基板に固定することで、フレキシブル基板が屈曲しても実装されたＩＣチップが殆ど追従しないようにした方法が開示されている。 Therefore, at present, a semiconductor circuit chip (IC chip) in which an integrated circuit such as a microcomputer or RF-IC is integrated on a silicon (Si) substrate or an SOI (Silicon On Insulation) substrate is manufactured and thinned (for example,). Non-Patent Documents 2 and 3), a method of manufacturing an electronic device by adhering it on a flexible substrate is adopted. Further, in order to give flexibility to a flexible electronic device and prevent the IC chip from cracking or peeling while maintaining sufficient flexibility of the flexible substrate, Patent Document 1 states that the IC chip is adhered only in the central region thereof. A method is disclosed in which the mounted IC chip hardly follows even if the flexible substrate is bent by fixing it to the flexible substrate via a layer.

更に、特許文献２には基板上に作製した極薄化した電子デバイス構造体（機能性素子、電極及び電極パッドからなる）を基板から剥離してフレキシブル基板に接着して転写することでフレキシブルな電子デバイスを製造する方法が開示されている。この特許文献２に記載の電子デバイスは、電子デバイス全体がフレキシブルになるため、より柔軟なフレキシブルな電子デバイスを実現することができる。このような従来のシリコンを基板としたＩＣ製造技術と印刷技術を組み合わせた電子デバイスは、フレキシブル・ハイブリッド・エレクトロニクスと呼ばれ近年注目を集めている（例えば、非特許文献４参照）。 Further, in Patent Document 2, an ultrathin electronic device structure (consisting of a functional element, an electrode and an electrode pad) manufactured on a substrate is peeled from the substrate, adhered to a flexible substrate, and transferred to be flexible. A method of manufacturing an electronic device is disclosed. In the electronic device described in Patent Document 2, since the entire electronic device becomes flexible, a more flexible and flexible electronic device can be realized. Such an electronic device that combines conventional silicon-based IC manufacturing technology and printing technology is called flexible hybrid electronics and has been attracting attention in recent years (see, for example, Non-Patent Document 4).

H.Fuketa,et ai.,“Organic-Transistor-Based 2kV ESD-Tolerant Flexible Wet Sensor Sheet for Biomedical Applications with Wireless Power and Data Transmission Using 13.56MHz Magnetic Resonance”,2014 International Solid-State Circuits Conference(ISSCC),(2014)pp.490-491H.Fuketa, et ai., “Organic-Transistor-Based 2kV ESD-Tolerant Flexible Wet Sensor Sheet for Biomedical Applications with Wireless Power and Data Transmission Using 13.56MHz Magnetic Resonance”, 2014 International Solid-State Circuits Conference (ISSCC), ( 2014) pp.490-491 Y.S.Kim.et al.,“Ultra Thinning of DRAM wafer for 3D WOW Application:Impact of Thinning on Retention Characteristic and Atomic Level Analysis of Backside Damage”,Proc.Advanced Metalization Conference(2014)and ADMETA 2014.,pp.1-2YSKim.et al., “Ultra Thinning of DRAM wafer for 3D WOW Application: Impact of Thinning on Retention Characteristic and Atomic Level Analysis of Backside Damage”, Proc.Advanced Metalization Conference (2014) and ADMETA 2014., pp.1- 2 Y.S.Kim.et al.,“Hot Spt Co.etal.,oiling Evaluation using Closed-Channel Cooling System(C3S)for MPU 3DI Application”,IEEE symp.on VLSI Technol.,(2011)pp.140-145Y.S.Kim.et al., “Hot Spt Co.etal., Oiling Evaluation using Closed-Channel Cooling System (C3S) for MPU 3DI Application”, IEEE symp.on VLSI Technol., (2011) pp.140-145 大谷基之,“飛躍狙うフレキシブル・ハイブリッド・エレクトロニクス（ＦＨＥ）技術”，日経テクノロジー,(2016)Motoyuki Otani, "Flexible Hybrid Electronics (FHE) Technology Aiming for a Leap", Nikkei Technology, (2016)

特開２０１２−０３８９２１号公報Japanese Unexamined Patent Publication No. 2012-08921 特開２０１６−０３９３４３号公報Japanese Unexamined Patent Publication No. 2016-039343

しかしながら、上記の非特許文献４に記載のフレキシブル・ハイブリッド・エレクトロニクスで作製された電子デバイスを衣類型ウェアラブルデバイスに使用する場合、衣類型ウェアラブルが伸長したり曲がったりすると、それが電子デバイスのフレキシブル基板を通して、電子デバイスの機能性素子である半導体回路チップ（例えば、マイコンやＲＦ-ＩＣなどの集積回路化された半導体信号処理回路や無線通信回路）に歪みとして伝達されてしまう。その結果、従来は半導体回路チップがフレキシブル基板の屈曲に左右されない正確な生体情報の検出及びそれに基づく所期の特性を得ることができず、あるいは極薄の半導体回路チップ自体が破断してしまい、電子デバイスの信頼性や長寿命化を阻害するという問題がある。 However, when an electronic device manufactured by the flexible hybrid electronics described in Non-Patent Document 4 is used for a clothing-type wearable device, when the clothing-type wearable is stretched or bent, it is a flexible substrate of the electronic device. Through this, it is transmitted as distortion to a semiconductor circuit chip (for example, a semiconductor signal processing circuit or a wireless communication circuit integrated into an integrated circuit such as a microcomputer or RF-IC) which is a functional element of an electronic device. As a result, conventionally, the semiconductor circuit chip cannot detect accurate biometric information that is not affected by the bending of the flexible substrate and obtain the desired characteristics based on the detection, or the ultrathin semiconductor circuit chip itself breaks. There is a problem of impeding the reliability and longevity of electronic devices.

また、特許文献１に記載の方法は、パッケージされているＩＣチップ（半導体回路チップ）の実装に関する方法であり、ＩＣチップが極薄ではなく、また、フレキシブル基板の曲がりや伸長が接着層を介してＩＣチップに歪みとして伝達されることは避けられず、衣類型ウェアラブルデバイスに使用することは困難である。更に、特許文献２記載の電子デバイスでは、フレキシブル基板上の極薄化した電子デバイス構造体に、フレキシブル基板の屈曲が伝達しないようにした対策はとられていないため、衣類型ウェアラブルデバイスに使用した場合、正確な人体情報の検出及びそれに基づく所期の特性を得ることができない。 Further, the method described in Patent Document 1 is a method relating to mounting of a packaged IC chip (semiconductor circuit chip), the IC chip is not ultra-thin, and the flexible substrate is bent or stretched via an adhesive layer. It is inevitable that the strain is transmitted to the IC chip, and it is difficult to use it in a clothing-type wearable device. Further, in the electronic device described in Patent Document 2, since no measure is taken to prevent the bending of the flexible substrate from being transmitted to the ultrathin electronic device structure on the flexible substrate, the electronic device is used for a clothing type wearable device. In this case, it is not possible to detect accurate human body information and obtain the desired characteristics based on it.

本発明は以上の点に鑑みなされたもので、フレキシブル基板から当該フレキシブル基板に搭載された半導体回路チップへの歪みの伝達を大幅に低減した構造の電子デバイス及びその製造方法を提供することを目的とする。 The present invention has been made in view of the above points, and an object of the present invention is to provide an electronic device having a structure in which strain transmission from a flexible substrate to a semiconductor circuit chip mounted on the flexible substrate is significantly reduced, and a method for manufacturing the same. And.

上記の目的を達成するため、第１の発明に係る電子デバイスは、表面に端子が形成された電子回路を内蔵する半導体回路チップと、表面に少なくともフレキシブル配線膜及びフレキシブルセンサが形成されたフレキシブル基板と、表面に配線膜が形成された構造であり、前記半導体回路チップの前記端子に前記配線膜の一端を接続し、かつ、前記配線膜の他端を前記フレキシブル配線膜に接続すると共に、前記半導体回路チップの端部を前記半導体回路チップと前記フレキシブル基板とを離間させた状態で弾性的に固定・支持する構造の歪み緩衝構造部とを備えることを特徴とする。 In order to achieve the above object, the electronic device according to the first invention includes a semiconductor circuit chip containing an electronic circuit having terminals formed on its surface, and a flexible substrate having at least a flexible wiring film and a flexible sensor formed on its surface. A wiring film is formed on the surface of the semiconductor circuit chip, and one end of the wiring film is connected to the terminal of the semiconductor circuit chip, and the other end of the wiring film is connected to the flexible wiring film. It is characterized by including a strain buffer structure portion having a structure in which an end portion of the semiconductor circuit chip is elastically fixed and supported in a state where the semiconductor circuit chip and the flexible substrate are separated from each other.

また、上記の目的を達成するため、第２の発明に係る電子デバイスは、第１の発明の歪み緩衝構造部が、前記フレキシブル基板とは異なる極薄の基板に形成された前記半導体回路チップの側縁部と、前記極薄の基板の端部との間を別々に接続する、平面が所定形状の複数の接続用基板部分の上に前記配線膜が形成されており、前記複数の接続用基板部分の各一方の端部の上の前記配線膜の一端を前記半導体回路チップの端子に電気的に接続し、前記複数の接続用基板部分の各他方の端部のみを前記フレキシブル基板にそれぞれ前記半導体回路チップと前記フレキシブル基板とを離間させた状態で弾性的に固定・支持すると共に前記配線膜の他端を前記フレキシブル配線膜に電気的に接続した構造であることを特徴とする。 Further, in order to achieve the above object, the electronic device according to the second invention is the semiconductor circuit chip in which the strain buffer structure portion of the first invention is formed on an ultrathin substrate different from the flexible substrate. The wiring film is formed on a plurality of connection substrate portions having a predetermined flat surface, which separately connects the side edge portion and the end portion of the ultrathin substrate, and is used for the plurality of connections. One end of the wiring film on each one end of the substrate portion is electrically connected to the terminal of the semiconductor circuit chip, and only the other end of each of the plurality of connection substrate portions is connected to the flexible substrate. The semiconductor circuit chip and the flexible substrate are elastically fixed and supported in a separated state, and the other end of the wiring film is electrically connected to the flexible wiring film.

また、上記の目的を達成するため、第３の発明に係る電子デバイスは、第１の発明のフレキシブル基板が、前記半導体回路チップの搭載用矩形領域と、前記矩形領域の側縁部と基板側縁部に沿う四角枠との間を平面が所定形状の複数の接続部でそれぞれ接続する形状の基板部分を残した開口部を有するとともに、表面に少なくともフレキシブル配線膜及びフレキシブルセンサが形成されており、第１の発明の歪み緩衝構造部が、前記フレキシブル基板の前記接続部の表面に前記配線膜が形成された構造であり、前記フレキシブル基板の前記矩形領域に搭載された前記半導体回路チップを前記接続部及び前記四角枠で弾性的に固定・支持すると共に、前記配線膜の一端を前記半導体回路チップの前記端子に接続し、かつ、前記配線膜の他端を前記フレキシブル配線膜に接続することを特徴とする。 Further, in order to achieve the above object, in the electronic device according to the third invention, the flexible substrate of the first invention has a rectangular region for mounting the semiconductor circuit chip, a side edge portion of the rectangular region, and a substrate side. It has an opening that leaves a substrate portion having a shape in which a flat surface is connected to a square frame along the edge portion by a plurality of connection portions having a predetermined shape, and at least a flexible wiring film and a flexible sensor are formed on the surface. The strain buffer structure portion of the first invention has a structure in which the wiring film is formed on the surface of the connection portion of the flexible substrate, and the semiconductor circuit chip mounted on the rectangular region of the flexible substrate is described. It is elastically fixed and supported by the connecting portion and the square frame, one end of the wiring film is connected to the terminal of the semiconductor circuit chip, and the other end of the wiring film is connected to the flexible wiring film. It is characterized by.

また、上記の目的を達成するため、第４の発明に係る電子デバイスは、第１の発明の歪み緩衝構造部が、前記フレキシブル基板、及び前記半導体回路チップが形成された極薄の基板とはそれぞれ異なる弾性体基板に形成されており、前記弾性体基板が前記半導体回路チップの搭載用矩形領域と、前記矩形領域の側縁部にそれぞれの一端が接続された平面が所定形状の複数の接続部とからなり、かつ、前記複数の接続部の表面に配線膜が形成された構造であり、前記配線膜の一端を前記弾性体基板の矩形領域に搭載された前記半導体回路チップの端子に電気的に接続し、かつ、前記複数の接続部の他端をスペーサを介して前記フレキシブル基板に前記半導体回路チップと離間させた状態で弾性的に固定・支持するとともに、前記２つの接続部の他端上の前記配線膜と前記フレキシブル配線膜とを前記スペーサを覆う導電性部材で電気的に接続することを特徴とする。 Further, in order to achieve the above object, in the electronic device according to the fourth invention, the strain buffer structure portion of the first invention is different from the flexible substrate and the ultrathin substrate on which the semiconductor circuit chip is formed. A plurality of connections in which the elastic body substrate is formed on different elastic body substrates, and the plane in which one end of the elastic body substrate is connected to a rectangular region for mounting the semiconductor circuit chip and a side edge portion of the rectangular region is a predetermined shape. It has a structure in which a wiring film is formed on the surface of the plurality of connection portions, and one end of the wiring film is electrically connected to a terminal of the semiconductor circuit chip mounted in a rectangular region of the elastic body substrate. The other ends of the plurality of connecting portions are elastically fixed and supported on the flexible substrate via spacers while being separated from the semiconductor circuit chip, and the other two connecting portions are connected. It is characterized in that the wiring film on the end and the flexible wiring film are electrically connected by a conductive member covering the spacer.

ここで、第１乃至第４の発明における所定形状は、ジグザグ形状、Ｓ字形状又はメッシュ状である。 Here, the predetermined shape in the first to fourth inventions is a zigzag shape, an S-shape, or a mesh shape.

上記の目的を達成するため、第６の発明に係る電子デバイスの製造方法は、表面に端子が形成された電子回路を内蔵する半導体回路チップを作製する工程と、表面に少なくともフレキシブル配線膜及びフレキシブルセンサが形成されたフレキシブル基板を作製する工程と、表面に配線膜が形成された構造の歪み緩衝構造部により、前記半導体回路チップの前記端子に前記配線膜の一端を接続し、かつ、前記配線膜の他端を前記フレキシブル配線膜に接続すると共に、前記半導体回路チップの端部を前記半導体回路チップと前記フレキシブル基板とを離間させた状態で弾性的に固定・支持する固定工程とを含むことを特徴とする。 In order to achieve the above object, the method for manufacturing an electronic device according to the sixth invention includes a step of manufacturing a semiconductor circuit chip containing an electronic circuit having terminals formed on its surface, and at least a flexible wiring film and flexible on the surface. One end of the wiring film is connected to the terminal of the semiconductor circuit chip by the process of manufacturing the flexible substrate on which the sensor is formed and the strain buffer structure portion of the structure in which the wiring film is formed on the surface, and the wiring. Includes a fixing step of connecting the other end of the film to the flexible wiring film and elastically fixing and supporting the end of the semiconductor circuit chip with the semiconductor circuit chip and the flexible substrate separated from each other. It is characterized by.

また、上記の目的を達成するため、第７の発明に係る電子デバイスの製造方法は、第６の発明における半導体回路チップを作製する工程を、前記フレキシブル基板とは異なる極薄の基板に前記半導体回路チップを作製する工程とし、
第６の発明における前記固定工程を、平面が所定形状で、かつ、表面に配線膜が形成されており、前記配線膜の一端が前記半導体回路チップの前記端子にそれぞれの一端が別々に電気的に接続された複数の接続部を前記極薄の基板に形成する接続部形成工程と、前記複数の接続部のそれぞれの前記配線膜の他端を前記フレキシブル配線膜に電気的に接続すると共に、前記複数の接続部の前記配線膜の他端が形成されている前記極薄の基板部分で、前記半導体回路チップと前記フレキシブル基板とを離間させた状態で固定する工程とからなるようにしたことを特徴とする。 Further, in order to achieve the above object, in the method for manufacturing an electronic device according to a seventh invention, the step of manufacturing a semiconductor circuit chip according to the sixth invention is performed on an ultrathin substrate different from the flexible substrate. As a process for manufacturing circuit chips
In the fixing step of the sixth invention, a flat surface has a predetermined shape and a wiring film is formed on the surface, and one end of the wiring film is electrically connected to the terminal of the semiconductor circuit chip. A connection portion forming step of forming a plurality of connection portions connected to the ultra-thin substrate, and the other end of each of the wiring membranes of the plurality of connection portions are electrically connected to the flexible wiring membrane. The step of fixing the semiconductor circuit chip and the flexible substrate in a separated state at the ultra-thin substrate portion on which the other end of the wiring film of the plurality of connecting portions is formed. It is characterized by.

また、上記の目的を達成するため、第８の発明に係る電子デバイスの製造方法は、第７の発明における接続部形成工程を、前記半導体回路チップの前記端子に一端が別々に接続され、他端が開放とされた平面形状が前記所定形状の複数の配線膜をシリコン基板上に形成する工程と、前記半導体回路チップ及び前記配線膜がそれぞれ形成された前記シリコン基板の裏側からエッチングにより、前記半導体回路チップを残し、かつ、前記複数の配線膜が形成されている前記シリコン基板部分を薄く残した凹部を形成する工程と、前記凹部が形成された前記シリコン基板から、前記半導体回路チップ及び前記複数の配線膜が表面に形成された薄い前記シリコン基板部分を剥離し、前記複数の配線膜が表面に形成された薄い前記シリコン基板部分を前記極薄の基板上の複数の接続部として得る工程とより構成し、
第７の発明における半導体回路チップと前記フレキシブル基板とを離間させた状態で固定する工程を、前記複数の配線膜の各端部の直下の前記極薄の基板部分のみを、前記フレキシブル基板の表面と離間させた状態でスペーサを介して固定する工程と、前記フレキシブル配線膜と前記複数の配線膜の各端部とを導電性部材で電気的に接続する工程とよりなるようにしたことを特徴とする。 Further, in order to achieve the above object, in the method for manufacturing an electronic device according to the eighth invention, one end of the connection portion forming step in the seventh invention is separately connected to the terminal of the semiconductor circuit chip, and the like. The step of forming a plurality of wiring films having an open end flat shape on a silicon substrate and etching from the back side of the semiconductor circuit chip and the silicon substrate on which the wiring films are formed, respectively, From the step of forming a recess in which the semiconductor circuit chip is left and the silicon substrate portion on which the plurality of wiring films are formed thinly left, and the silicon substrate in which the recess is formed, the semiconductor circuit chip and the said A step of peeling off the thin silicon substrate portion having a plurality of wiring films formed on the surface and obtaining the thin silicon substrate portion having the plurality of wiring films formed on the surface as a plurality of connecting portions on the ultrathin substrate. And more composed,
In the step of fixing the semiconductor circuit chip and the flexible substrate in a separated state in the seventh invention, only the ultrathin substrate portion directly below each end of the plurality of wiring films is the surface of the flexible substrate. It is characterized by comprising a step of fixing the flexible wiring film and each end of the plurality of wiring films by a conductive member, and a step of electrically connecting the flexible wiring film and the respective ends of the plurality of wiring films with a conductive member. And.

また、上記の目的を達成するため、第９の発明に係る電子デバイスの製造方法は、第６の発明におけるフレキシブル基板を作製する工程を、表面に少なくともフレキシブル配線膜及びフレキシブルセンサが形成された加工前のフレキシブル基板に対し、前記半導体回路チップの搭載用矩形領域と、前記矩形領域の側縁部と基板側縁部に沿う四角枠との間を平面が所定形状で、かつ、表面に前記配線膜が形成されるとともに、前記配線膜の一端が前記フレキシブル配線膜にそれぞれ電気的に接続された形状の複数の接続部とを残した開口部を形成して加工処理したフレキシブル基板を作製する工程とし、
第６の発明における固定工程を、前記加工処理したフレキシブル基板の前記矩形領域に、前記半導体回路チップの端子が前記複数の接続部のそれぞれの配線膜の他端に電気的に接続されるように前記半導体回路チップを搭載する工程を有し、前記半導体回路チップを前記複数の接続部及び前記四角枠で弾性的に固定・支持するようにしたことを特徴とする。 Further, in order to achieve the above object, the method for manufacturing an electronic device according to the ninth invention is a process of manufacturing a flexible substrate according to the sixth invention, in which at least a flexible wiring film and a flexible sensor are formed on the surface. With respect to the previous flexible substrate, the flat surface has a predetermined shape between the rectangular region for mounting the semiconductor circuit chip and the side edge portion of the rectangular region and the square frame along the side edge portion of the substrate, and the wiring is provided on the surface. A step of forming a film and forming an opening in which one end of the wiring film is electrically connected to the flexible wiring film, leaving a plurality of connection portions, respectively, to produce a processed flexible substrate. age,
The fixing step in the sixth invention is performed so that the terminal of the semiconductor circuit chip is electrically connected to the rectangular region of the processed flexible substrate to the other end of each wiring film of the plurality of connection portions. It has a step of mounting the semiconductor circuit chip, and is characterized in that the semiconductor circuit chip is elastically fixed and supported by the plurality of connecting portions and the square frame.

また、上記の目的を達成するため、第１０の発明に係る電子デバイスの製造方法は、第６の発明における前記固定工程を、前記フレキシブル基板、及び前記半導体回路チップが形成された極薄の基板とはそれぞれ異なる弾性体基板に対し、前記半導体回路チップの搭載用矩形領域と、前記矩形領域の側縁部にそれぞれの一端が接続された平面が所定形状で、かつ、表面に配線膜が形成された複数の接続部とを形成する工程と、前記極薄の基板に形成された前記半導体回路チップの端子が、前記複数の接続部のそれぞれの配線膜の一端に電気的に接続されるように前記半導体回路チップを前記矩形領域に搭載する工程と、前記複数の接続部の他端をスペーサを介して前記フレキシブル基板に前記半導体回路チップと離間させた状態で弾性的に固定・支持するとともに、前記複数の接続部の他端上の前記配線膜と前記フレキシブル配線膜とを前記スペーサを覆う導電性部材で電気的に接続する工程とからなるようにしたことを特徴とする。 Further, in order to achieve the above object, in the method for manufacturing an electronic device according to the tenth invention, the fixing step in the sixth invention is performed on the flexible substrate and the ultrathin substrate on which the semiconductor circuit chip is formed. A rectangular region for mounting the semiconductor circuit chip and a flat surface in which one end of each is connected to a side edge portion of the rectangular region have a predetermined shape and a wiring film is formed on the surface of the elastic substrate different from the above. The step of forming the plurality of connection portions and the terminals of the semiconductor circuit chip formed on the ultrathin substrate are electrically connected to one end of each wiring film of the plurality of connection portions. In addition to the step of mounting the semiconductor circuit chip in the rectangular region, the other end of the plurality of connecting portions is elastically fixed and supported on the flexible substrate in a state of being separated from the semiconductor circuit chip via a spacer. It is characterized in that the wiring film on the other end of the plurality of connecting portions and the flexible wiring film are electrically connected by a conductive member covering the spacer.

ここで、第６乃至第１０の発明における所定形状は、ジグザグ形状、Ｓ字形状又はメッシュ状である。 Here, the predetermined shape in the sixth to tenth inventions is a zigzag shape, an S-shape, or a mesh shape.

本発明によれば、フレキシブル基板から当該フレキシブル基板に搭載された半導体回路チップへの歪みの伝達を大幅に低減することができる。 According to the present invention, it is possible to significantly reduce the transmission of strain from the flexible substrate to the semiconductor circuit chip mounted on the flexible substrate.

本発明に係る電子デバイスの第１の実施形態の概略模式的構成図である。It is a schematic schematic block diagram of the 1st Embodiment of the electronic device which concerns on this invention. 本発明に係る電子デバイスの第１の実施形態の製造方法を説明する各製造工程時の素子平面図及び素子断面図である。It is an element plan view and element sectional view at each manufacturing process explaining the manufacturing method of 1st Embodiment of the electronic device which concerns on this invention. 本発明に係る電子デバイスの第２の実施形態の製造方法（その１）を説明する各製造工程時の素子平面図及び素子断面図である。It is an element plan view and element sectional view at each manufacturing process explaining the manufacturing method (the 1) of the 2nd Embodiment of the electronic device which concerns on this invention. 本発明に係る電子デバイスの第２の実施形態の製造方法（その２）を説明する各製造工程時の素子平面図及び素子断面図である。It is an element plan view and element sectional view at each manufacturing process explaining the manufacturing method (the 2) of the 2nd Embodiment of the electronic device which concerns on this invention. 本発明に係る電子デバイスの第３の実施形態の製造方法（その１）を説明する各製造工程時の素子平面図及び素子断面図である。It is an element plan view and element sectional view at each manufacturing process explaining the manufacturing method (the 1) of the 3rd Embodiment of the electronic device which concerns on this invention. 本発明に係る電子デバイスの第３の実施形態の製造方法（その２）を説明する各製造工程時の素子平面図及び素子断面図である。It is an element plan view and element sectional view at each manufacturing process explaining the manufacturing method (the 2) of the 3rd Embodiment of the electronic device which concerns on this invention. 本発明に係る電子デバイスの第３の実施形態の製造方法（その３）を説明する各製造工程時の素子平面図及び素子断面図である。It is an element plan view and element sectional view at each manufacturing process explaining the manufacturing method (the 3) of the 3rd Embodiment of the electronic device which concerns on this invention. 本発明に係る電子デバイスを用いたウェアラブルデバイスの一例の全体構成図である。It is an overall block diagram of an example of the wearable device using the electronic device which concerns on this invention. 本発明に係る電子デバイスを用いたウェアラブルデバイスの一例の使用例を示す図である。It is a figure which shows the use example of an example of the wearable device using the electronic device which concerns on this invention. 本発明の第１の実施形態の電子デバイスをウェアラブルデバイスに適用した場合の概略模式的構成図である。It is a schematic schematic block diagram when the electronic device of 1st Embodiment of this invention is applied to a wearable device. 本発明の第１の実施形態の電子デバイスをウェアラブルデバイスに適用した場合の概略模式的構成図である。It is a schematic schematic block diagram when the electronic device of 1st Embodiment of this invention is applied to a wearable device. 本発明の第１の実施形態の電子デバイスをウェアラブルデバイスに適用した場合の概略模式的構成図である。It is a schematic schematic block diagram when the electronic device of 1st Embodiment of this invention is applied to a wearable device. 歪み緩衝構造部の平面形状の他の例の説明図である。It is explanatory drawing of another example of the planar shape of a strain buffer structure part. 半導体回路チップと歪み緩衝構造部との接続の他の例（その１）の説明図である。It is explanatory drawing of another example (the 1) of connection of a semiconductor circuit chip and a strain buffer structure part. 半導体回路チップと歪み緩衝構造部との接続の他の例（その２）の説明図である。It is explanatory drawing of another example (the 2) of connection of a semiconductor circuit chip and a strain buffer structure part. 半導体回路チップと歪み緩衝構造部との接続の他の例（その３）の説明図である。It is explanatory drawing of another example (the 3) of connection of a semiconductor circuit chip and a strain buffer structure part.

次に、本発明の各実施形態について図面を参照して説明する。
（第１の実施形態）
図１は、本発明に係る電子デバイスの第１の実施形態の概略模式的構成図を示す。同図に模式的に示すように、本実施形態の電子デバイス１０は、フレキシブル基板１１と、極薄の半導体回路チップ１２と、表面に配線膜が形成されている歪み緩衝構造部１３ａ及び１３ｂとより構成されている。フレキシブル基板１１は、表面にフレキシブル配線膜、フレキシブルセンサ、フレキシブルバッテリなどが形成されており、その伸長率は例えば１％〜１０％である。半導体回路チップ１２は、半導体信号処理回路（マイコン含む）や無線通信回路などの電子回路の半導体集積回路（ＩＣ）を内蔵するＩＣチップであり、その伸長率は例えば０.１％〜０.０１％で、また極薄に形成されている。 Next, each embodiment of the present invention will be described with reference to the drawings.
(First Embodiment)
FIG. 1 shows a schematic schematic configuration diagram of a first embodiment of the electronic device according to the present invention. As schematically shown in the figure, the electronic device 10 of the present embodiment includes a flexible substrate 11, an ultrathin semiconductor circuit chip 12, and strain buffer structure portions 13a and 13b having a wiring film formed on the surface thereof. It is composed of. The flexible substrate 11 has a flexible wiring film, a flexible sensor, a flexible battery, and the like formed on the surface thereof, and the elongation rate thereof is, for example, 1% to 10%. The semiconductor circuit chip 12 is an IC chip containing a semiconductor integrated circuit (IC) of an electronic circuit such as a semiconductor signal processing circuit (including a microcomputer) or a wireless communication circuit, and its elongation rate is, for example, 0.1% to 0.01. It is formed in% and very thin.

また、歪み緩衝構造部１３ａ及び１３ｂは、半導体回路チップ１２の底面とフレキシブル基板１１の上面との間に間隔ｄを設けた状態で、半導体回路チップ１２の対向する２つの端部とフレキシブル基板１１の対向する２つの端部との間を別々に固定している。したがって、半導体回路チップ１２は、歪み緩衝構造部１３ａ及び１３ｂによりフレキシブル基板１１に弾性的に固定されており、半導体回路チップ１２は、フレキシブル基板１１が屈曲しても、それに関係なく、緩衝構造部１３ａ及び１３ｂによりフレキシブル基板１１から間隔ｄだけ浮いた状態でほぼ静止しているため、フレキシブル基板１１の屈曲が半導体回路チップ１２に歪みとして伝達されることを大幅に低減できる。 Further, the strain buffer structure portions 13a and 13b are provided with a space d between the bottom surface of the semiconductor circuit chip 12 and the top surface of the flexible substrate 11, and the two opposing ends of the semiconductor circuit chip 12 and the flexible substrate 11 are provided. It is fixed separately between the two opposite ends of the. Therefore, the semiconductor circuit chip 12 is elastically fixed to the flexible substrate 11 by the strain buffer structure portions 13a and 13b, and the semiconductor circuit chip 12 has the buffer structure portion regardless of the bending of the flexible substrate 11. Since the 13a and 13b are substantially stationary in a state of being floated from the flexible substrate 11 by an interval d, it is possible to significantly reduce the bending of the flexible substrate 11 being transmitted to the semiconductor circuit chip 12 as distortion.

また、歪み緩衝構造部１３ａ及び１３ｂは、表面に形成された配線膜の一端が半導体回路チップ１２の固定した端部を介して半導体回路チップ１２の端子に電気的に接続され、配線膜の他端がフレキシブル基板１１の表面のフレキシブル配線膜に電気的に接続されている。すなわち、歪み緩衝構造部１３ａ及び１３ｂは、半導体回路チップ１２の端部のみをフレキシブル基板１１から浮いた状態で弾性的に固定支持すると共に、半導体回路チップ１２とフレキシブル基板１１との間を電気的に接続する。なお、歪み緩衝構造部１３ａ及び１３ｂにより端部が固定された半導体回路チップ１２の底面とフレキシブル基板１１の上面との間の間隔ｄの値は、使用用途などに応じて適宜決定される設計事項である。 Further, in the strain buffer structure portions 13a and 13b, one end of the wiring film formed on the surface is electrically connected to the terminal of the semiconductor circuit chip 12 via the fixed end portion of the semiconductor circuit chip 12, and the wiring film and the like. The ends are electrically connected to the flexible wiring film on the surface of the flexible substrate 11. That is, the strain buffer structure portions 13a and 13b elastically fix and support only the end portion of the semiconductor circuit chip 12 in a state of floating from the flexible substrate 11, and electrically fix and support the semiconductor circuit chip 12 and the flexible substrate 11. Connect to. The value of the distance d between the bottom surface of the semiconductor circuit chip 12 whose ends are fixed by the strain buffer structure portions 13a and 13b and the top surface of the flexible substrate 11 is a design item that is appropriately determined according to the intended use and the like. Is.

次に、本実施形態の電子デバイス１０の製造方法について説明する。
図２（Ａ１）〜（Ｇ１）及び（Ａ２）〜（Ｇ２）は、本発明に係る電子デバイスの第１の実施形態の製造方法を説明する各製造工程時の素子平面図及び素子断面図を示す。同図中、図１と同一構成部分には同一符号を付してある。なお、図２（Ｃ２）〜（Ｇ２）は、図２（Ｃ１）〜（Ｇ１）の一点鎖線に沿う断面図を示す。本実施形態の製造方法は、ＳＯＩ基板集積型の製造方法で、まず、図２（Ａ１）の平面図及び同図（Ａ２）の断面図に示すように、シリコン基板２１、シリコン酸化膜層２２及び表層シリコン層２３が積層されたＳＯＩ基板２０を用意する。表層シリコン層２３はシリコン基板２１に比し極薄の厚さである。続いて、図２（Ｂ１）の平面図及び（Ｂ２）の断面図に示すように、表層シリコン層２３の中央位置に、公知の方法で半導体信号処理回路や無線通信回路などの電子回路を集積回路（ＩＣ）化した半導体回路チップ１２を形成する。半導体回路チップ１２の端子は表層シリコン層２３の表面に形成される。 Next, a method of manufacturing the electronic device 10 of the present embodiment will be described.
2 (A1) to (G1) and (A2) to (G2) show a plan view and a cross-sectional view of an element at each manufacturing process for explaining the manufacturing method of the first embodiment of the electronic device according to the present invention. Shown. In the figure, the same components as those in FIG. 1 are designated by the same reference numerals. Note that FIGS. 2 (C2) to (G2) show cross-sectional views taken along the alternate long and short dash line of FIGS. 2 (C1) to (G1). The manufacturing method of the present embodiment is an SOI substrate integrated manufacturing method. First, as shown in the plan view of FIG. 2 (A1) and the cross-sectional view of FIG. 2 (A2), the silicon substrate 21 and the silicon oxide film layer 22 And the SOI substrate 20 on which the surface silicon layer 23 is laminated is prepared. The surface silicon layer 23 has an ultrathin thickness as compared with the silicon substrate 21. Subsequently, as shown in the plan view of FIG. 2 (B1) and the cross-sectional view of FIG. 2 (B2), electronic circuits such as a semiconductor signal processing circuit and a wireless communication circuit are integrated at the center position of the surface silicon layer 23 by a known method. The semiconductor circuit chip 12 which is made into a circuit (IC) is formed. The terminals of the semiconductor circuit chip 12 are formed on the surface of the surface silicon layer 23.

次に、図２（Ｃ１）の平面図及び（Ｃ２）の断面図に示すように、表層シリコン層２３の表面に導電膜を成膜した後、その導電膜に対しフォトリソグラフィ及びエッチングなどの公知技術を適用して一端が半導体回路チップ１２の端子に接続され、他端が表層シリコン層２３の端部付近に位置するような平面形状がジグザグ状の配線膜２４ａ及び２４ｂをパターニング形成する。続いて、図２（Ｄ１）の平面図及び（Ｄ２）の断面図に示すように、シリコン基板２１の裏側から深掘りＲＩＥ（DRIE;Deep Reactive Ion Etching）により、シリコン基板２１及びシリコン酸化膜層２２の長手方向の端部と半導体回路チップ１２を残し、かつ、ジグザグ状の配線膜２４ａ及び２４ｂの下側の表層シリコン層２３を極薄く残し、それ以外を除去する。 Next, as shown in the plan view of FIG. 2 (C1) and the cross-sectional view of FIG. 2 (C2), a conductive film is formed on the surface of the surface silicon layer 23, and then photolithography and etching are known for the conductive film. Applying the technique, the wiring films 24a and 24b having a planar shape in which one end is connected to the terminal of the semiconductor circuit chip 12 and the other end is located near the end of the surface silicon layer 23 are patterned and formed. Subsequently, as shown in the plan view of FIG. 2 (D1) and the cross-sectional view of (D2), the silicon substrate 21 and the silicon oxide film layer are subjected to deep reactive Ion Etching (RIE) from the back side of the silicon substrate 21. The longitudinal end of 22 and the semiconductor circuit chip 12 are left, and the surface silicon layer 23 under the zigzag wiring films 24a and 24b is left extremely thin, and the rest is removed.

このようにして、公知のＭＥＭＳ(Micro Electro Mechanical Systems)デバイスの作製方法と同様の工程を経て、シリコン基板２１が２１’で、シリコン酸化膜層２２が２２’で、表層シリコン層２３が２３’でそれぞれ示すように大部分が除去され、一部のみが残された凹部２５が形成されると共に、表層シリコン層２３’上にジグザグ状の配線膜２４ａ及び２４ｂが形成され、かつ、半導体回路チップ１２が極薄に形成された構造体が製造される。 In this way, the silicon substrate 21 is 21', the silicon oxide film layer 22 is 22', and the surface silicon layer 23 is 23', through the same steps as the method for manufacturing a known MEMS (Micro Electro Mechanical Systems) device. As shown in each of the above, most of the recesses 25 are removed to form a recess 25 in which only a part is left, and zigzag wiring films 24a and 24b are formed on the surface silicon layer 23', and the semiconductor circuit chip. A structure in which 12 is formed extremely thin is manufactured.

続いて、ポリジメチルシロキサン（ＰＤＭＳ）などの粘着材を上記構造体の上部に粘着し、その粘着状態を保ったまま粘着材を引き上げると、上記構造体は厚さが厚い長手方向の両端部分で切断されて、ジグザグ状の配線膜２４ａ及び２４ｂが表面に形成され、かつ、半導体回路チップ１２が形成された表層シリコン層２３’が粘着材と共に引き上げられる。すなわち、図２（Ｅ１）の平面図及び（Ｅ２）の断面図に示すように、上記構造体の両端部分以外のジグザグ状の配線膜２４ａ及び２４ｂが表面に形成され、かつ、半導体回路チップ１２が形成された表層シリコン層２３’が、シリコン基板２１’及びシリコン酸化膜層２２’から剥離される。なお、この剥離は粘着材ではなく、ピンセットを用いて行ってもよい。このようにして、図２（Ｅ１）の平面図及び（Ｅ２）の断面図に示すように、半導体回路チップ１２の対向する両側に、表層シリコン層２３’とジグザグ状の配線膜２４ａ及び２４ｂとからなり、一端が半導体回路チップ１２の端子に接続された歪緩衝構造部１３ａ及び１３ｂが形成される。 Subsequently, an adhesive material such as polydimethylsiloxane (PDMS) is adhered to the upper part of the structure, and when the adhesive material is pulled up while maintaining the adhesive state, the structure is thick at both ends in the longitudinal direction. The surface silicon layer 23'on which the zigzag wiring films 24a and 24b are formed on the surface and the semiconductor circuit chip 12 is formed is pulled up together with the adhesive material. That is, as shown in the plan view of FIG. 2 (E1) and the cross-sectional view of (E2), the zigzag wiring films 24a and 24b other than both end portions of the structure are formed on the surface, and the semiconductor circuit chip 12 The surface silicon layer 23'formed by the above is peeled off from the silicon substrate 21'and the silicon oxide film layer 22'. Note that this peeling may be performed using tweezers instead of an adhesive material. In this way, as shown in the plan view of FIG. 2 (E1) and the cross-sectional view of FIG. 2 (E2), the surface silicon layer 23'and the zigzag-shaped wiring films 24a and 24b are formed on the opposite sides of the semiconductor circuit chip 12. A strain buffer structure portion 13a and 13b having one end connected to a terminal of the semiconductor circuit chip 12 are formed.

次に、表面にフレキシブル配線膜２６ａ、２６ｂやフレキシブルセンサ及びフレキシブルバッテリなど（図示せず）が形成されると共に、表面の所定位置に所定高さのプラスチックなどの絶縁体製のスペーサ２７ａ及び２７ｂが離間して形成されたフレキシブル基板１１が用意される。フレキシブル基板１１の材質は、例えばポリウレタン系やポリエステル系の伸縮性を有する樹脂である。そして、図２（Ｆ１）の平面図及び（Ｆ２）の断面図に示すように、フレキシブル基板１１上にスペーサ２７ａ、２７ｂを介して上記の半導体回路チップ１２及び歪み緩衝構造部１３ａ、１３ｂからなる主構造体が実装される。 Next, flexible wiring films 26a and 26b, a flexible sensor, a flexible battery, and the like (not shown) are formed on the surface, and spacers 27a and 27b made of an insulator such as plastic having a predetermined height are formed at predetermined positions on the surface. Flexible substrates 11 formed apart from each other are prepared. The material of the flexible substrate 11 is, for example, a polyurethane-based or polyester-based resin having elasticity. Then, as shown in the plan view of FIG. 2 (F1) and the cross-sectional view of (F2), the semiconductor circuit chip 12 and the strain buffer structure portions 13a and 13b are formed on the flexible substrate 11 via spacers 27a and 27b. The main structure is implemented.

ここで、スペーサ２７ａ、２７ｂは、表層シリコン層２３’の長手方向の両端部の裏面位置に対応して設けられており、また、主構造体のフレキシブル基板１２上への実装は、スペーサ２７ａ、２７ｂと表層シリコン層２３’の長手方向の両端部の裏面との間でのみ公知の方法で固着される。したがって、それぞれ歪み緩衝構造部１３ａ及び１３ｂの長手方向の両端部の一方の端部に接続されている半導体回路チップ１２は、歪み緩衝構造部１３ａ及び１３ｂの長手方向の両端部の他方の端部でのみスペーサ２７ａ、２７ｂを介してフレキシブル基板１１に、スペーサ２７ａ及び２７ｂの高さ分だけ浮いた状態で固定される。すなわち、半導体回路チップ１２は、歪み緩衝構造部１３ａ及び１３ｂによりフレキシブル基板１１に対して浮いた状態で弾性的に固定・支持される。 Here, the spacers 27a and 27b are provided corresponding to the positions of the back surfaces of both ends of the surface silicon layer 23'in the longitudinal direction, and the main structure can be mounted on the flexible substrate 12 with the spacers 27a and 27b. It is fixed by a known method only between 27b and the back surface of both ends of the surface silicon layer 23'in the longitudinal direction. Therefore, the semiconductor circuit chip 12 connected to one end of both ends of the strain buffer structure portions 13a and 13b in the longitudinal direction is the other end portion of both ends of the strain buffer structure portions 13a and 13b in the longitudinal direction. It is fixed to the flexible substrate 11 via the spacers 27a and 27b only by the height of the spacers 27a and 27b in a floating state. That is, the semiconductor circuit chip 12 is elastically fixed and supported by the strain buffer structure portions 13a and 13b in a floating state with respect to the flexible substrate 11.

そして、最後に、図２（Ｇ１）の平面図及び（Ｇ２）の断面図に示すように、フレキシブル基板１１に形成されているフレキシブル配線膜２６ａ、２６ｂの電極パッドとジグザグ状の配線膜２４ａ、２４ｂの端部との間を、スクリーン印刷などにより導電性ペースト２８ａ、２８ｂを塗布して電気的に接続し、電子デバイス１０の製造が終了する。 Finally, as shown in the plan view of FIG. 2 (G1) and the cross-sectional view of (G2), the electrode pads of the flexible wiring films 26a and 26b formed on the flexible substrate 11 and the zigzag-shaped wiring film 24a, Conductive pastes 28a and 28b are applied and electrically connected to the end of 24b by screen printing or the like, and the production of the electronic device 10 is completed.

このようにして製造された本実施形態の電子デバイス１０によれば、極薄の半導体回路チップ１２をフレキシブル基板１１に対して浮いた状態で固定する歪緩衝構造部１３ａ及び１３ｂは、半導体回路チップ１２の両端部のみを固定するとともに、平面形状がジグザグ状であるため半導体回路チップ１２を弾性的に固定する。このため、フレキシブル基板１１が屈曲しても半導体回路チップ１２はほぼ静止しており、半導体回路チップ１２に歪みとして伝達されることは殆どない。その結果、本実施形態の電子デバイス１０を例えば衣類型ウェアラブルデバイスに使用した場合、衣類型ウェアラブルが伸長したり曲がったりしても、半導体回路チップ１２がフレキシブル基板１１の屈曲に殆ど影響されることなく正確な生体情報の検出及びそれに基づく所期の特性を得ることができ、また極薄の半導体回路チップ１２自体が破断することを防止できる。 According to the electronic device 10 of the present embodiment manufactured in this manner, the strain buffer structure portions 13a and 13b for fixing the ultrathin semiconductor circuit chip 12 in a floating state with respect to the flexible substrate 11 are semiconductor circuit chips. Only both ends of the 12 are fixed, and the semiconductor circuit chip 12 is elastically fixed because the planar shape is zigzag. Therefore, even if the flexible substrate 11 is bent, the semiconductor circuit chip 12 is substantially stationary and is hardly transmitted to the semiconductor circuit chip 12 as distortion. As a result, when the electronic device 10 of the present embodiment is used for, for example, a clothing-type wearable device, the semiconductor circuit chip 12 is almost affected by the bending of the flexible substrate 11 even if the clothing-type wearable is stretched or bent. Accurate detection of biological information and desired characteristics based on the detection can be obtained, and the ultrathin semiconductor circuit chip 12 itself can be prevented from breaking.

（第２の実施形態）
次に、本発明に係る電子デバイスの第２の実施形態について図面と共に説明する。
図３（Ａ１）〜（Ｄ１）及び（Ａ２）〜（Ｄ２）は、本発明に係る電子デバイスの第２の実施形態の製造方法（その１）を説明する各製造工程時の素子平面図及び素子断面図、図４（Ａ１）〜（Ｄ１）及び（Ａ２）〜（Ｄ２）は、本発明に係る電子デバイスの第２の実施形態の製造方法（その２）を説明する各製造工程時の素子平面図及び素子断面図を示す。なお、図３（Ｂ２）〜（Ｄ２）は、同図（Ｂ１）〜（Ｄ１）中の一点鎖線に沿う断面図を示す。本実施形態の製造方法は、フレキシブル基板加工型の製造方法で、本実施形態の電子デバイス３０は、図３及び図４の両方の製造工程により最終的に図３（Ｄ１）の平面図及び図３（Ｄ２）の断面図に示すように、配線膜３２ａ及び３２ｂが表面に形成された歪み緩衝構造部を有するように加工処理されたフレキシブル基板３７と、極薄の半導体回路チップ４０とよりなる構造に製造される。 (Second Embodiment)
Next, a second embodiment of the electronic device according to the present invention will be described with reference to the drawings.
3 (A1) to (D1) and (A2) to (D2) are element plan views during each manufacturing process for explaining the manufacturing method (No. 1) of the second embodiment of the electronic device according to the present invention. The element sectional views, FIGS. 4 (A1) to (D1) and (A2) to (D2), show the manufacturing method (No. 2) of the second embodiment of the electronic device according to the present invention in each manufacturing step. The element plan view and the element sectional view are shown. Note that FIGS. 3 (B2) to (D2) show cross-sectional views taken along the alternate long and short dash line in FIGS. (B1) to (D1). The manufacturing method of the present embodiment is a flexible substrate processing type manufacturing method, and the electronic device 30 of the present embodiment is finally a plan view and a view of FIG. 3 (D1) by the manufacturing steps of both FIGS. 3 and 4. As shown in the cross-sectional view of 3 (D2), the flexible substrate 37 is processed so that the wiring films 32a and 32b have a strain buffering structure formed on the surface thereof, and an ultrathin semiconductor circuit chip 40. Manufactured in structure.

まず、図３（Ａ１）の平面図及び同図（Ａ２）の断面図に示す加工処理前のフレキシブル基板３１を用意する。ただし、このフレキシブル基板３１の表面には、既にフレキシブル配線膜、フレキシブルセンサ、フレキシブルバッテリなどが形成されている。次に、このフレキシブル基板３１の表面に導電膜を成膜した後、その導電膜に対しフォトリソグラフィ及びエッチングなどの公知技術を適用して、図３（Ｂ１）の平面図及び（Ｂ２）の断面図に示すように、中央の所定サイズの領域に対して、長手方向の各端部から平面がジグザグ形状の配線膜３２ａ及び３２ｂと、複数の電極パッド３３ａ及び３３ｂとをそれぞれパターニング形成する。配線膜３２ａ及び３２ｂのフレキシブル基板３１の側縁部側の端部は、フレキシブル基板３１のフレキシブル配線膜に接続されている。上記中央の所定サイズの領域は、後に半導体回路チップを搭載することを想定したサイズの領域であり、その領域内の複数の電極パッド３３ａ、３３ｂが配線膜３２ａ、３２ｂの端部に接続されている。 First, the flexible substrate 31 before processing shown in the plan view of FIG. 3 (A1) and the cross-sectional view of FIG. 3 (A2) is prepared. However, a flexible wiring film, a flexible sensor, a flexible battery, and the like are already formed on the surface of the flexible substrate 31. Next, after forming a conductive film on the surface of the flexible substrate 31, a known technique such as photolithography and etching is applied to the conductive film, and the plan view of FIG. 3 (B1) and the cross section of (B2) are applied. As shown in the figure, wiring films 32a and 32b having a zigzag-shaped plane and a plurality of electrode pads 33a and 33b are patterned and formed from each end in the longitudinal direction with respect to a region having a predetermined size in the center. The ends of the wiring films 32a and 32b on the side edge side of the flexible substrate 31 are connected to the flexible wiring film of the flexible substrate 31. The central predetermined size region is a region of a size assuming that a semiconductor circuit chip will be mounted later, and a plurality of electrode pads 33a and 33b in the region are connected to the ends of the wiring films 32a and 32b. There is.

続いて、図３（Ｃ１）の平面図及び（Ｃ２）の断面図に示すように、上記中央の所定サイズの領域内に設けられた半導体回路チップの搭載用矩形領域３４と、矩形領域３４の対向する２つの辺の各中央部と、フレキシブル基板３１の側縁部に沿う四角枠３５との間を平面がジグザグ形状の２つの配線膜３２ａ及び３２ｂでそれぞれ接続する形状の基板部分を残した開口部３６を、例えばレーザー加工装置を用いて開口する。このようにフレキシブル基板３１は開口部３６を有するように加工処理されてフレキシブル基板３７となる。この加工処理後のフレキシブル基板３７の、配線膜３２ａ及び３２ｂが表面に形成されたジグザグ状形成部分は歪み緩衝構造部を構成する。 Subsequently, as shown in the plan view of FIG. 3 (C1) and the cross-sectional view of (C2), the rectangular region 34 for mounting the semiconductor circuit chip provided in the region of the predetermined size in the center and the rectangular region 34. A substrate portion having a shape in which two wiring films 32a and 32b having a zigzag flat surface are connected between the central portions of the two opposing sides and the square frame 35 along the side edge portion of the flexible substrate 31 is left. The opening 36 is opened using, for example, a laser processing device. In this way, the flexible substrate 31 is processed so as to have the opening 36 to become the flexible substrate 37. The zigzag-shaped formed portion of the flexible substrate 37 after this processing, in which the wiring films 32a and 32b are formed on the surface, constitutes a strain buffer structure portion.

一方、図３の製造工程とは別に、図４（Ａ１）の平面図及び（Ａ２）の断面図に示すシリコン基板３９を用意し、そのシリコン基板３９に図４（Ｂ１）の平面図及び（Ｂ２）の断面図に示すように、極薄の半導体回路チップ４０を公知の方法で作製する。半導体回路チップ４０は、半導体信号処理回路（マイコン含む）や無線通信回路などの電子回路の半導体集積回路（ＩＣ）を内蔵するＩＣチップである。半導体回路チップ４０の表面には、接続用端子である電極パッド４１ａ及び４１ｂが形成される。 On the other hand, apart from the manufacturing process of FIG. 3, the silicon substrate 39 shown in the plan view of FIG. 4 (A1) and the cross-sectional view of (A2) is prepared, and the silicon substrate 39 has the plan view of FIG. 4 (B1) and ( As shown in the cross-sectional view of B2), an ultrathin semiconductor circuit chip 40 is manufactured by a known method. The semiconductor circuit chip 40 is an IC chip incorporating a semiconductor integrated circuit (IC) of an electronic circuit such as a semiconductor signal processing circuit (including a microcomputer) or a wireless communication circuit. Electrode pads 41a and 41b, which are connection terminals, are formed on the surface of the semiconductor circuit chip 40.

続いて、図４（Ｃ１）の平面図及び（Ｃ２）の断面図に３９’で示すように、ＤＲＩＥなどの公知のエッチング方法を適用してシリコン基板３９の厚さを半導体回路チップ４０を残して薄化処理する。続いて、図４（Ｄ１）の平面図及び（Ｄ２）の断面図に示すように、薄化処理したシリコン基板３９’を更に半導体回路チップ４０を残して、その周辺部分を除去するダイシング処理をレーザーを用いて行う。これにより、シリコン基板３９’から極薄の半導体回路チップ４０が切り出される。ダイシング処理後のシリコン基板４２は半導体回路チップ４０の側面のみを覆う。 Subsequently, as shown by 39'in the plan view of FIG. 4 (C1) and the cross-sectional view of FIG. 4 (C2), a known etching method such as DRIE is applied to leave the semiconductor circuit chip 40 at the thickness of the silicon substrate 39. To thin it. Subsequently, as shown in the plan view of FIG. 4 (D1) and the cross-sectional view of FIG. 4 (D2), a dicing process is performed in which the thinned silicon substrate 39'is further left with the semiconductor circuit chip 40 and the peripheral portion thereof is removed. This is done using a laser. As a result, the ultrathin semiconductor circuit chip 40 is cut out from the silicon substrate 39'. The silicon substrate 42 after the dicing process covers only the side surface of the semiconductor circuit chip 40.

そして、図３（Ｃ１）の平面図及び（Ｃ２）の断面図に示したフレキシブル基板３７の表面の矩形領域３４に、図４の製造工程により得られた極薄の半導体回路チップ４０が、図３（Ｄ１）の平面図及び（Ｄ２）の断面図に示すように、フェースダウンでボンディングされる。このボンディングは、フレキシブル基板３７の表面の電極パッド３３ａ、３３ｂと半導体回路チップ４０の端子である電極バッド４１ａ、４１ｂとが接合されるように、アライメントマークを設けて顕微鏡などで観察しながら微小な位置調整を行った後実行される。これにより、本実施形態の電子デバイス３０が製造される。 Then, in the rectangular region 34 on the surface of the flexible substrate 37 shown in the plan view of FIG. 3 (C1) and the cross-sectional view of FIG. 3 (C2), the ultrathin semiconductor circuit chip 40 obtained by the manufacturing process of FIG. 4 is shown. As shown in the plan view of 3 (D1) and the cross-sectional view of (D2), the bonding is performed face-down. In this bonding, an alignment mark is provided so that the electrode pads 33a and 33b on the surface of the flexible substrate 37 and the electrode pads 41a and 41b which are terminals of the semiconductor circuit chip 40 are bonded, and the bonding is minute while observing with a microscope or the like. It is executed after adjusting the position. As a result, the electronic device 30 of the present embodiment is manufactured.

このようにして製造された本実施形態の電子デバイス３０によれば、フレキシブル基板３７の配線膜３２ａ及び３２ｂが表面に形成されたジグザグ状形成部分は歪み緩衝構造部を構成し、一端が四角枠３５上のフレキシブル配線膜に接続されると共に固定されており、他端が半導体回路チップ４０の端部の電極パッドに接続されると共に、半導体回路チップ４０をフレキシブル基板３７の表面に接しないように浮いた状態で弾性的に固定する。このため、フレキシブル基板３７が屈曲しても半導体回路チップ４０はほぼ静止しており、半導体回路チップ４０に歪みとして伝達されることは殆どない。その結果、本実施形態の電子デバイス３０を例えば衣類型ウェアラブルデバイスに使用した場合、衣類型ウェアラブルが伸長したり曲がったりしても、半導体回路チップ４０がフレキシブル基板３７の屈曲に左右されない正確な生体情報の検出及びそれに基づく所期の特性を得ることができ、また極薄の半導体回路チップ４０自体が破断することを防止できる。 According to the electronic device 30 of the present embodiment manufactured in this manner, the zigzag-shaped formed portion formed on the surface of the wiring films 32a and 32b of the flexible substrate 37 constitutes a strain absorbing structure portion, and one end thereof is a square frame. It is connected to and fixed to the flexible wiring film on the 35, the other end is connected to the electrode pad at the end of the semiconductor circuit chip 40, and the semiconductor circuit chip 40 is not in contact with the surface of the flexible substrate 37. It is elastically fixed in a floating state. Therefore, even if the flexible substrate 37 is bent, the semiconductor circuit chip 40 is almost stationary and is hardly transmitted to the semiconductor circuit chip 40 as distortion. As a result, when the electronic device 30 of the present embodiment is used for, for example, a clothing-type wearable device, the semiconductor circuit chip 40 is not affected by the bending of the flexible substrate 37 even if the clothing-type wearable is stretched or bent. Information can be detected and desired characteristics based on the information can be obtained, and the ultrathin semiconductor circuit chip 40 itself can be prevented from breaking.

（第３の実施形態）
次に、本発明に係る電子デバイスの第３の実施形態について図面と共に説明する。
図５（Ａ１）〜（Ｄ１）及び（Ａ２）〜（Ｄ２）は、本発明に係る電子デバイスの第３の実施形態の製造方法（その１）を、図６（Ａ１）〜（Ｄ１）及び（Ａ２）〜（Ｄ２）は、本発明に係る電子デバイスの第３の実施形態の製造方法（その２）を、図７（Ａ１）〜（Ｃ１）及び（Ａ２）〜（Ｃ２）は、本発明に係る電子デバイスの第３の実施形態の製造方法（その３）を、それぞれ説明する各製造工程時の素子平面図及び素子断面図を示す。なお、図５（Ｂ２）〜（Ｄ２）は、図５（Ｂ１）〜（Ｄ１）中の一点鎖線に沿う断面図、図７（Ａ２）〜（Ｃ２）は、図７（Ａ１）〜（Ｃ１）中の一点鎖線に沿う断面図を示す。本実施形態の製造方法は、弾性体基板接合型の製造方法で、前述したＳＯＩ基板集積型とフレキシブル基板加工型の中間的な製造方法である。本実施形態で製造される電子デバイス５０は、図５乃至図７の製造工程により最終的に図７（Ｃ１）の平面図及び図７（Ｃ２）の断面図に示すように、歪み緩衝構造部を有するように加工処理されたフレキシブル基板６４と、極薄の半導体回路チップ６０と、表面に配線膜５２ａ及び５２ｂが形成された歪み緩衝構造部とよりなる構造である。 (Third Embodiment)
Next, a third embodiment of the electronic device according to the present invention will be described with reference to the drawings.
5 (A1) to (D1) and (A2) to (D2) show the manufacturing method (No. 1) of the third embodiment of the electronic device according to the present invention in FIGS. 6 (A1) to (D1). (A2) to (D2) are the manufacturing methods (No. 2) of the third embodiment of the electronic device according to the present invention, and FIGS. 7 (A1) to (C1) and (A2) to (C2) are the present methods. The element plan view and element cross-sectional view at each manufacturing process for explaining the manufacturing method (No. 3) of the third embodiment of the electronic device according to the invention are shown. 5 (B2) to (D2) are cross-sectional views taken along the alternate long and short dash line in FIGS. 5 (B1) to (D1), and FIGS. 7 (A2) to 7 (C2) are FIGS. 7 (A1) to (C1). ) Shows a cross-sectional view along the alternate long and short dash line. The manufacturing method of this embodiment is a manufacturing method of an elastic substrate bonding type, which is an intermediate manufacturing method between the SOI substrate integrated type and the flexible substrate processing type described above. The electronic device 50 manufactured in the present embodiment is finally a strain buffer structure portion as shown in the plan view of FIG. 7 (C1) and the cross-sectional view of FIG. 7 (C2) by the manufacturing process of FIGS. 5 to 7. It is a structure including a flexible substrate 64 processed so as to have the above, an ultra-thin semiconductor circuit chip 60, and a strain buffering structure portion in which wiring films 52a and 52b are formed on the surface.

次に、本実施形態の製造方法について図５乃至図７と共に説明する。まず、図５（Ａ１）の平面図及び同図（Ａ２）の断面図に示す弾性体基板５１を用意する。弾性体基板５１は、ポリウレタン系あるいはポリエステル系の柔軟性のある樹脂からなる第２のフレキシブル基板で、本実施形態の電子デバイス５０を構成する後述する第１のフレキシブル基板６４と材質及び伸長率は同様であるが、その伸長率は第１のフレキシブル基板６４とやや大きくてもよい（若干剛性があってもよい）。ただし、弾性体基板５１にはフレキシブル配線膜やフレキシブルバッテリなどは形成されていない。 Next, the manufacturing method of this embodiment will be described with reference to FIGS. 5 to 7. First, the elastic substrate 51 shown in the plan view of FIG. 5 (A1) and the cross-sectional view of FIG. 5 (A2) is prepared. The elastic substrate 51 is a second flexible substrate made of a polyurethane-based or polyester-based flexible resin, and has the same material and elongation as the first flexible substrate 64, which will be described later, which constitutes the electronic device 50 of the present embodiment. Similar, but the elongation rate may be slightly larger than that of the first flexible substrate 64 (may be slightly rigid). However, a flexible wiring film, a flexible battery, or the like is not formed on the elastic substrate 51.

続いて、弾性体基板５１の表面に導電膜を成膜した後、その導電膜に対しフォトリソグラフィ及びエッチングなどの公知技術を適用して、図５（Ｂ１）の平面図及び（Ｂ２）の断面図に示すように、中央の所定サイズの領域に対して、長手方向の各端部から平面がジグザグ形状の配線膜５２ａ及び５２ｂと、複数の電極パッド５３ａ及び５３ｂとをそれぞれパターニング形成する。上記中央の所定サイズの領域は、後に半導体回路チップを搭載することを想定したサイズの領域であり、その領域内に複数の電極パッド５３ａ、５３ｂが形成され、配線膜５２ａ、５２ｂの端部に接続されている。 Subsequently, after forming a conductive film on the surface of the elastic substrate 51, a known technique such as photolithography and etching is applied to the conductive film, and the plan view of FIG. 5 (B1) and the cross section of (B2) are applied. As shown in the figure, the wiring films 52a and 52b having a zigzag-shaped plane from each end in the longitudinal direction and the plurality of electrode pads 53a and 53b are patterned and formed with respect to a region having a predetermined size in the center. The central predetermined size region is a region of a size assuming that a semiconductor circuit chip will be mounted later, and a plurality of electrode pads 53a and 53b are formed in the region, and are formed at the ends of the wiring films 52a and 52b. It is connected.

続いて、図５（Ｃ１）の平面図及び（Ｃ２）の断面図に示すように、上記中央の所定サイズの領域内に設けられた半導体回路チップの搭載用矩形領域５４と、矩形領域５４の対向する２つの辺の各中央部と、弾性体基板５１の側縁部に沿う四角枠５５との間を平面がジグザグ形状の２つの配線膜５２ａ及び５２ｂでそれぞれ接続する形状の基板部分を残した開口部５６を、例えばレーザー加工装置を用いて開口する。このように弾性体基板５１は開口部５６を有するように加工処理されて弾性体基板５７となる。この加工処理後の弾性体基板５７の、配線膜５２ａ及び５２ｂが表面に形成されたジグザグ状形成部分は歪み緩衝構造部を構成する。 Subsequently, as shown in the plan view of FIG. 5 (C1) and the cross-sectional view of FIG. 5 (C2), the rectangular region 54 for mounting the semiconductor circuit chip provided in the region of the predetermined size in the center and the rectangular region 54. A substrate portion having a shape in which two wiring films 52a and 52b having a zigzag plane are connected between the central portions of the two opposing sides and the square frame 55 along the side edge portion of the elastic substrate 51 is left. The opening 56 is opened using, for example, a laser processing device. In this way, the elastic substrate 51 is processed so as to have the opening 56 to become the elastic substrate 57. The zigzag-shaped formed portion of the elastic substrate 57 after this processing, in which the wiring films 52a and 52b are formed on the surface, constitutes a strain buffering structure portion.

続いて、図５（Ｄ１）の平面図及び（Ｄ２）の断面図に示すように、加工処理後の弾性体基板５７の四角枠５５から、粘着剤を用いてあるいはピンセットを用いて、矩形領域５４を、配線膜５２ａ及び５２ｂが表面に形成された平面がジグザグ形状の２つの基板部分でそれぞれ接続する形状の構造体５８が剥離される。 Subsequently, as shown in the plan view of FIG. 5 (D1) and the cross-sectional view of FIG. 5 (D2), a rectangular region is formed from the square frame 55 of the elastic substrate 57 after the processing by using an adhesive or tweezers. The structure 58 having a shape in which the planes formed on the surfaces of the wiring films 52a and 52b are connected by two zigzag-shaped substrate portions is peeled off.

一方、図５の製造工程とは別に、図６（Ａ１）の平面図及び（Ａ２）の断面図に示すシリコン基板５９を用意し、そのシリコン基板５９に図６（Ｂ１）の平面図及び（Ｂ２）の断面図に示すように、極薄の半導体回路チップ６０を公知の方法で作製する。半導体回路チップ６０は、半導体信号処理回路（マイコン含む）や無線通信回路などの電子回路の半導体集積回路（ＩＣ）を内蔵するＩＣチップである。半導体回路チップ６０の表面には、接続用端子である電極パッド６１ａ及び６１ｂが形成される。 On the other hand, apart from the manufacturing process of FIG. 5, the silicon substrate 59 shown in the plan view of FIG. 6 (A1) and the cross-sectional view of (A2) is prepared, and the silicon substrate 59 has the plan view of FIG. 6 (B1) and ( As shown in the cross-sectional view of B2), an ultrathin semiconductor circuit chip 60 is manufactured by a known method. The semiconductor circuit chip 60 is an IC chip incorporating a semiconductor integrated circuit (IC) of an electronic circuit such as a semiconductor signal processing circuit (including a microcomputer) or a wireless communication circuit. Electrode pads 61a and 61b, which are connection terminals, are formed on the surface of the semiconductor circuit chip 60.

続いて、図６（Ｃ１）の平面図及び（Ｃ２）の断面図に５９’で示すように、ＤＲＩＥなどの公知のエッチング方法を適用してシリコン基板５９の厚さを半導体回路チップ６０を残して薄化処理する。続いて、図６（Ｄ１）の平面図及び（Ｄ２）の断面図に示すように、薄化処理したシリコン基板５９’を更に半導体回路チップ６０を残して、その周辺部分を除去するダイシング処理をレーザーを用いて行う。これにより、シリコン基板５９’から極薄の半導体回路チップ６０が切り出される。ダイシング処理後のシリコン基板６２は半導体回路チップ６０の側面のみを覆う。 Subsequently, as shown by 59'in the plan view of FIG. 6 (C1) and the cross-sectional view of FIG. 6 (C2), a known etching method such as DRIE is applied to leave the semiconductor circuit chip 60 at the thickness of the silicon substrate 59. To thin it. Subsequently, as shown in the plan view of FIG. 6 (D1) and the cross-sectional view of FIG. 6 (D2), a dicing process is performed in which the thinned silicon substrate 59'is further left with the semiconductor circuit chip 60 and the peripheral portion thereof is removed. This is done using a laser. As a result, the ultrathin semiconductor circuit chip 60 is cut out from the silicon substrate 59'. The silicon substrate 62 after the dicing process covers only the side surface of the semiconductor circuit chip 60.

そして、図５（Ｄ１）の平面図及び（Ｄ２）の断面図に示した弾性体基板５７の表面の矩形領域５４に、図６の製造工程により得られた極薄の半導体回路チップ６０がフェースダウンでボンディングされ、図７（Ａ１）の平面図及び（Ａ２）の断面図に示す主構造体が作製される。このボンディングは、弾性体基板５７の表面の電極パッド５３ａ、５３ｂと半導体回路チップ６０の端子である電極バッド６１ａ、６１ｂとが接合されるように、アライメントマークを設けて顕微鏡などで観察しながら微小な位置調整を行った後実行される。 Then, in the rectangular region 54 on the surface of the elastic substrate 57 shown in the plan view of FIG. 5 (D1) and the cross-sectional view of (D2), the ultrathin semiconductor circuit chip 60 obtained by the manufacturing process of FIG. 6 is faced. Bonded down to produce the main structure shown in the plan view of FIG. 7 (A1) and the cross-sectional view of FIG. 7 (A2). In this bonding, alignment marks are provided so that the electrode pads 53a and 53b on the surface of the elastic substrate 57 and the electrode pads 61a and 61b which are terminals of the semiconductor circuit chip 60 are bonded, and the bonding is performed while observing with a microscope or the like. It is executed after performing various position adjustments.

続いて、矩形領域５４にボンディングされた半導体回路チップ６０を配線膜５２ａ及び５２ｂが表面に形成された平面がジグザグ形状の２つの基板部分でそれぞれ接続する形状の主構造体が、図７（Ｂ１）の平面図及び（Ｂ２）の断面図に示すように、所定高さのプラスチックなどの絶縁体製のスペーサ６５ａ及び６５ｂを介してフレキシブル基板６４に実装される。フレキシブル基板６４は、表面にフレキシブル配線膜やフレキシブルセンサ及びフレキシブルバッテリなど（図示せず）が形成されると共に、表面の所定位置にスペーサ６５ａ及び６５ｂが離間して形成されており、その材質は例えばポリウレタン系やポリエステル系の伸縮性を有する樹脂である。 Subsequently, FIG. 7 (B1) shows a main structure having a shape in which the semiconductor circuit chip 60 bonded to the rectangular region 54 is connected by two substrate portions having a zigzag-shaped plane on which the wiring films 52a and 52b are formed on the surface. ) And the cross-sectional view of (B2), it is mounted on the flexible substrate 64 via spacers 65a and 65b made of an insulator such as plastic having a predetermined height. The flexible substrate 64 has a flexible wiring film, a flexible sensor, a flexible battery, and the like (not shown) formed on the surface thereof, and spacers 65a and 65b are formed at predetermined positions on the surface so as to be separated from each other. It is a polyurethane-based or polyester-based elastic resin.

ここで、スペーサ６５ａ及び６５ｂは、主構造体の長手方向の両端部の裏面位置に対応して設けられており、また、主構造体のフレキシブル基板６４上への実装は、スペーサ６５ａ、６５ｂとの間でのみ公知の方法で固着される。したがって、半導体回路チップ６０は、配線膜５２ａ及び５２ｂが表面に形成された平面がジグザグ形状の２つの基板部分をそれぞれ歪み緩衝構造部とし、その２つの歪み緩衝構造部の両端部及び２つのスペーサ２７ａ、２７ｂのみを介して、フレキシブル基板６４の表面に対してスペーサ６５ａ及び６５ｂの高さ分だけ浮いた状態で固定される。すなわち、半導体回路チップ６０は、２つの歪み緩衝構造部によりフレキシブル基板６４に対して浮いた状態で弾性的に固定・支持される。 Here, the spacers 65a and 65b are provided corresponding to the positions of the back surfaces of both ends in the longitudinal direction of the main structure, and the main structure is mounted on the flexible substrate 64 with the spacers 65a and 65b. It is fixed by a known method only between. Therefore, in the semiconductor circuit chip 60, two substrate portions having a zigzag-shaped plane formed on the surfaces of the wiring films 52a and 52b are used as strain buffer structure portions, and both ends of the two strain buffer structure portions and two spacers are used. It is fixed to the surface of the flexible substrate 64 via only 27a and 27b in a state of being floated by the heights of the spacers 65a and 65b. That is, the semiconductor circuit chip 60 is elastically fixed and supported by the two strain buffering structures in a floating state with respect to the flexible substrate 64.

そして、最後に、図７（Ｃ１）の平面図及び（Ｃ２）の断面図に示すように、フレキシブル基板６４に形成されているフレキシブル配線膜６３ａ、６３ｂとジグザグ状の配線膜５２ａ、５２ｂの端部との間を、スクリーン印刷などにより導電性ペースト６６ａ、６６ｂを塗布して電気的に接続し、電子デバイス５０の製造が終了する。 Finally, as shown in the plan view of FIG. 7 (C1) and the cross-sectional view of (C2), the ends of the flexible wiring films 63a and 63b and the zigzag-shaped wiring films 52a and 52b formed on the flexible substrate 64. Conductive pastes 66a and 66b are applied and electrically connected to the portions by screen printing or the like, and the production of the electronic device 50 is completed.

このようにして製造された本実施形態の電子デバイス５０によれば、半導体回路チップ６０をフレキシブル基板６４に対して浮いた状態で固定する２つの歪緩衝構造部（構造体５８中の配線膜５２ａ、５２ｂが表面に形成された平面ジグザグ形状基板部分）は、半導体回路チップ６０の両端部のみを固定するとともに、平面形状がジグザグ状であるため半導体回路チップ６０を弾性的に固定する。このため、フレキシブル基板６４が屈曲しても半導体回路チップ６０はほぼ静止しており、半導体回路チップ６０に歪みとして伝達されることを大幅に低減できる。その結果、本実施形態の電子デバイス５０を例えば衣類型ウェアラブルデバイスに使用した場合、衣類型ウェアラブルが伸長したり曲がったりしても、半導体回路チップ６０がフレキシブル基板６４の屈曲に殆ど影響されることなく正確な生体情報の検出及びそれに基づく所期の特性を得ることができ、また極薄の半導体回路チップ６０自体が破断することを防止できる。 According to the electronic device 50 of the present embodiment manufactured in this manner, the two strain-absorbing structural portions (wiring film 52a in the structure 58) that fix the semiconductor circuit chip 60 in a floating state with respect to the flexible substrate 64. , 52b is formed on the surface of the flat zigzag-shaped substrate portion), and only both ends of the semiconductor circuit chip 60 are fixed, and the semiconductor circuit chip 60 is elastically fixed because the flat shape is zigzag. Therefore, even if the flexible substrate 64 is bent, the semiconductor circuit chip 60 is substantially stationary, and transmission as distortion to the semiconductor circuit chip 60 can be significantly reduced. As a result, when the electronic device 50 of the present embodiment is used for, for example, a clothing-type wearable device, the semiconductor circuit chip 60 is almost affected by the bending of the flexible substrate 64 even if the clothing-type wearable is stretched or bent. Accurate detection of biological information and desired characteristics based on the detection can be obtained, and the ultrathin semiconductor circuit chip 60 itself can be prevented from breaking.

以上説明した第１乃至第３の実施形態の製造方法によれば、製造プロセス及び歪み緩衝構造部の材質などの違いはあるが、いずれも極薄の半導体回路チップ１２、４０、６０の端部のみが歪み緩衝構造部により弾性的に固定されているという点、及び極薄の半導体回路チップ１２、４０、６０が直接フレキシブル基板１１、３７、６４と接していないという点で共通する。これにより、いずれの製造方法で作成した電子デバイス１０、３０、５０も前述した所期の効果を得ることができる。なお、第１の実施形態のＳＯＩ基板集積型の製造方法は、半導体回路チップと歪み緩衝構造部とを同じ基板に集積化するため、一枚のウェハ（基板）に作製できる半導体回路チップの数が少ないのに対し、第２の実施形態及び第３の実施形態の製造方法では半導体回路チップを歪み緩衝構造部と異なる基板に作製するため一枚のウェハ（基板）に作製できる半導体回路チップの数を多くでき、単価を安価にできるという効果もある。半導体回路チップの単価はウェハ一枚にどれだけ組み込めるかで決まるからである。 According to the manufacturing methods of the first to third embodiments described above, although there are differences in the manufacturing process and the material of the strain buffer structure, all of them are the ends of the ultrathin semiconductor circuit chips 12, 40, 60. It is common in that only the strain buffer structure is elastically fixed, and that the ultrathin semiconductor circuit chips 12, 40, 60 are not in direct contact with the flexible substrates 11, 37, 64. As a result, the electronic devices 10, 30, and 50 produced by any of the manufacturing methods can obtain the desired effects described above. In the SOI substrate integrated manufacturing method of the first embodiment, since the semiconductor circuit chip and the strain buffer structure are integrated on the same substrate, the number of semiconductor circuit chips that can be manufactured on one wafer (board). However, in the manufacturing methods of the second embodiment and the third embodiment, the semiconductor circuit chip can be manufactured on a single wafer (board) because the semiconductor circuit chip is manufactured on a substrate different from the strain buffer structure portion. It also has the effect of increasing the number and reducing the unit price. This is because the unit price of a semiconductor circuit chip is determined by how much it can be incorporated into one wafer.

次に、本発明に係る電子デバイスを用いたウェアラブルデバイスについて説明する。図８は、本発明に係る電子デバイスを用いたウェアラブルデバイスの一例の全体構成図を示す。同図において、ウェアラブルデバイス１００は、本発明に係る電子デバイスの半導体回路チップ及び歪み緩衝構造部からなる主構造体１０１がフレキシブル基板１０２上に形成されている。主構造体１０１を構成する平面形状がジグザグ状の歪み緩衝構造部の一方の端部は、同じ主構造体１０１を構成する半導体回路チップの端部の端子に電気的に接続されるとともにフレキシブル基板１０２の表面に接しないように離間した状態で弾性的に固定し、他方の端部がフレキシブル基板１０２の表面に形成されているフレキシブル配線膜１０３に電気的に接続されている。また、フレキシブル基板１０２には、フレキシブルセンサ・バッテリ等１０４が形成されている。ウェアラブルデバイス１００は、フレキシブル基板１０２上に実装された主構造体１０１の上面を、ポリエチレンナフタレート（ＰＥＮ）やポリエチレンテレフタレート（ＰＥＴ）などの樹脂からなるカバーフィルム１０５で被覆した構造である。カバーフィルム１０５は保護膜として機能する。 Next, a wearable device using the electronic device according to the present invention will be described. FIG. 8 shows an overall configuration diagram of an example of a wearable device using the electronic device according to the present invention. In the figure, in the wearable device 100, a main structure 101 including a semiconductor circuit chip and a strain buffer structure portion of the electronic device according to the present invention is formed on a flexible substrate 102. One end of the strain buffer structure having a zigzag-shaped planar shape constituting the main structure 101 is electrically connected to the terminal at the end of the semiconductor circuit chip forming the same main structure 101, and is a flexible substrate. It is elastically fixed in a separated state so as not to come into contact with the surface of the 102, and the other end is electrically connected to the flexible wiring film 103 formed on the surface of the flexible substrate 102. Further, a flexible sensor, a battery, and the like 104 are formed on the flexible substrate 102. The wearable device 100 has a structure in which the upper surface of the main structure 101 mounted on the flexible substrate 102 is covered with a cover film 105 made of a resin such as polyethylene naphthalate (PEN) or polyethylene terephthalate (PET). The cover film 105 functions as a protective film.

次に、本発明に係る電子デバイスを用いたウェアラブルデバイスの使用例について説明する。図９は、本発明に係る電子デバイスを用いたウェアラブルデバイスの一例の使用例を示す図である。図９において、図８の構成の電子デバイス１００は、例えばシャツ１５０の設定位置に装着され、シャツ１５０を着た人体の心拍数、呼吸その他必要な人体情報をフレキシブルセンサにより収集する衣類型ウェアラブルデバイスを構成している。このような衣類型ウェアラブルデバイスに本発明に係る電子デバイス１００を用いた場合、シャツ１５０の伸縮に伴いフレキシブル基板（図８の１０２）が伸縮しても、半導体回路チップにはフレキシブル基板の伸縮が歪みとして殆ど伝達されないため、人体情報の検出が正確にできる。 Next, an example of using a wearable device using the electronic device according to the present invention will be described. FIG. 9 is a diagram showing a usage example of an example of a wearable device using the electronic device according to the present invention. In FIG. 9, the electronic device 100 having the configuration of FIG. 8 is a clothing-type wearable device that is attached to, for example, a set position of a shirt 150 and collects heart rate, respiration, and other necessary human body information of a human body wearing the shirt 150 by a flexible sensor. Consists of. When the electronic device 100 according to the present invention is used for such a clothing-type wearable device, even if the flexible substrate (102 in FIG. 8) expands and contracts as the shirt 150 expands and contracts, the semiconductor circuit chip expands and contracts. Since it is hardly transmitted as distortion, human body information can be detected accurately.

次に、前述した実施形態の電子デバイスをウェアラブルデバイスに適用した場合の概略について説明する。図１０は、第１の実施形態をウェアラブルデバイスに適用した場合の概略模式的構成図、図１１は、第２の実施形態をウェアラブルデバイスに適用した場合の概略模式的構成図、図１２は、第３の実施形態をウェアラブルデバイスに適用した場合の概略模式的構成図を示す。図１０、図１１及び図１２中、図２、図３及び図７と同一構成部分には同一符号を付し、その説明を省略する。第１の実施形態の電子デバイスは、図１０に模式的に示すようにフレキシブル基板１１の下面全面が衣料のテキスタイル１６０に接着されている。第２の実施形態の電子デバイスは、図１１に模式的に示すようにフレキシブル基板３７の端部が衣料のテキスタイル１６０に接着されている。ただし、フレキシブル基板３７の中央の半導体回路チップ４０が搭載されている領域は、テキスタイル１６０の表面に接着されておらず離間している。また、第３の実施形態の電子デバイスは、図１２に模式的に示すようにフレキシブル基板６４の下面全面が衣料のテキスタイル１６０に接着されている。なお、テキスタイル１６０は例えば伸長率１％〜１０％である。 Next, an outline when the electronic device of the above-described embodiment is applied to a wearable device will be described. 10 is a schematic schematic configuration diagram when the first embodiment is applied to a wearable device, FIG. 11 is a schematic schematic configuration diagram when the second embodiment is applied to a wearable device, and FIG. 12 is a schematic schematic configuration diagram. A schematic schematic configuration diagram when the third embodiment is applied to a wearable device is shown. In FIGS. 10, 11 and 12, the same components as those in FIGS. 2, 3 and 7 are designated by the same reference numerals, and the description thereof will be omitted. In the electronic device of the first embodiment, the entire lower surface of the flexible substrate 11 is adhered to the textile 160 of clothing as schematically shown in FIG. In the electronic device of the second embodiment, the end portion of the flexible substrate 37 is adhered to the textile 160 of the garment as schematically shown in FIG. However, the region where the semiconductor circuit chip 40 is mounted in the center of the flexible substrate 37 is not adhered to the surface of the textile 160 and is separated from each other. Further, in the electronic device of the third embodiment, the entire lower surface of the flexible substrate 64 is adhered to the textile 160 of clothing as schematically shown in FIG. The textile 160 has, for example, an elongation rate of 1% to 10%.

なお、本発明は以上の実施形態に限定されるものではなく、例えば歪み緩衝構造部１３ａ、１３ｂ等の平面形状はジグザグ状に限定されるものではなく、半導体回路チップ１２、３６の端部のみを弾性的に支持できる他の形状、例えば図１３の（Ａ）に示すＳ字状や同図（Ｂ）に示すメッシュ状であってもよい。なお、Ｓ字型の歪み緩衝構造で電子回路を保持し、フレキシブル基板で覆うことでフレキシブルな生体センサを作製する研究報告が文献（C.H.Lee,et al.,”Soft Core/Shell Packages for Stretchable Electronics”,Advanced Matrerials,(2015) pp.3698-3704）に記載されている。しかし、この手法は半導体回路チップがパッケージ化されている点と、半導体回路チップが直接フレキシブル基板に接している点とで本発明における歪み緩衝構造部とは異なる。 The present invention is not limited to the above embodiments. For example, the planar shapes of the strain buffer structure portions 13a and 13b are not limited to the zigzag shape, and only the ends of the semiconductor circuit chips 12 and 36. It may have another shape that can elastically support, for example, an S-shape shown in FIG. 13A or a mesh shape shown in FIG. 13B. In addition, there is a research report (CH Lee, et al., "Soft Core / Shell Packages for Stretchable Electronics" that holds an electronic circuit with an S-shaped strain buffer structure and covers it with a flexible substrate to produce a flexible biosensor. ”, Advanced Matrerials, (2015) pp.3698-3704). However, this method differs from the strain buffer structure portion in the present invention in that the semiconductor circuit chip is packaged and that the semiconductor circuit chip is in direct contact with the flexible substrate.

また、半導体回路チップの端部を直接的に又は間接的に固定・保持する歪み緩衝構造部は２つに限定されるものではなく、複数あればよい。例えば図１４に模式的に示すように半導体回路チップ１７０の３か所の端部をそれぞれ固定・保持する３つの歪み緩衝構造部１７０を有するようにしてもよい。また、図１５に模式的に示すように半導体回路チップ１８０の４か所の端部をそれぞれ固定・保持する４つの歪み緩衝構造部１９０を有するようにしてもよい。更に、図１６に模式的に示すように半導体回路チップ１７０の各辺３か所の端部をそれぞれ別々に固定・保持するメッシュ状の９つの歪み緩衝構造部２００を有するようにしてもよい。 Further, the strain buffer structure portion that directly or indirectly fixes and holds the end portion of the semiconductor circuit chip is not limited to two, and may be plurality. For example, as schematically shown in FIG. 14, the semiconductor circuit chip 170 may have three strain buffer structure portions 170 that fix and hold the three end portions, respectively. Further, as schematically shown in FIG. 15, the semiconductor circuit chip 180 may have four strain buffer structure portions 190 that fix and hold the four end portions, respectively. Further, as schematically shown in FIG. 16, the semiconductor circuit chip 170 may have nine mesh-shaped strain buffering structure portions 200 that separately fix and hold the ends at three locations on each side.

人間や動物などの健康モニタリングを目的とした衣類型ウェアラブルデバイスなど、フレキシブルな電子デバイスの使用可能な分野に広く応用可能である。 It can be widely applied to the fields where flexible electronic devices can be used, such as clothing-type wearable devices for the purpose of monitoring the health of humans and animals.

１０、３０、５０ 電子デバイス
１１、６４、１０２ フレキシブル基板
１２、４０、６０、１７０ 半導体回路チップ
１３ａ、１３ｂ、１８０、１９０、２００ 歪み緩衝構造部
２０ ＳＯＩ基板
２１、２１’、３９、３９’、４２、５９、５９’ シリコン基板
２２、２２’ シリコン酸化膜層
２３、２３’ 表層シリコン層
２４ａ、２４ｂ、３２ａ、３２ｂ、５２ａ、５２ｂ 配線膜
２５ 凹部
２６ａ、２６ｂ、６３ａ、６３ｂ、１０３ フレキシブル配線膜
２７ａ、２７ｂ、６５ａ、６５ｂ スペーサ
２８ａ、２８ｂ、６６ａ、６６ｂ 導電性ペースト
３１ 加工処理前のフレキシブル基板
３３ａ、３３ｂ、４１ａ、４１ｂ、５３ａ、５３ｂ、６１ａ、６１ｂ 電極パッド
３４、５４ 矩形領域
３５、５５ 四角枠
３６、５６ 開口部
３７ 加工処理後のフレキシブル基板
５１ 弾性体基板（第２のフレキシブル基板）
５７ 加工処理後の弾性体基板
５８ 構造体
１００ ウェアラブルデバイス
１０１ 主構造体
１０４ フレキシブルセンサ・バッテリ等
１５０ シャツ



10, 30, 50 Electronic devices 11, 64, 102 Flexible substrates 12, 40, 60, 170 Semiconductor circuit chips 13a, 13b, 180, 190, 200 Strain buffer structure 20 SOI substrates 21, 21', 39, 39', 42, 59, 59'Silicon substrates 22, 22'Silicon oxide film layers 23, 23'Surface silicon layers 24a, 24b, 32a, 32b, 52a, 52b Wiring film 25 Recesses 26a, 26b, 63a, 63b, 103 Flexible wiring film 27a, 27b, 65a, 65b Spacer 28a, 28b, 66a, 66b Conductive paste 31 Flexible substrate before processing 33a, 33b, 41a, 41b, 53a, 53b, 61a, 61b Electrode pads 34, 54 Rectangular regions 35, 55 Square frames 36, 56 Openings 37 Flexible substrate after processing 51 Elastic substrate (second flexible substrate)
57 Elastic substrate after processing 58 Structure 100 Wearable device 101 Main structure 104 Flexible sensor, battery, etc. 150 Shirt

Claims (14)

表面に端子が形成された電子回路を内蔵する半導体回路チップと、
表面に少なくともフレキシブル配線膜が形成されたフレキシブル基板と、
表面に配線膜が形成された構造であり、前記半導体回路チップの前記端子に前記配線膜の一端を接続し、かつ、前記配線膜の他端を前記フレキシブル配線膜に接続すると共に、前記半導体回路チップと前記フレキシブル基板とを離間させた状態で前記半導体回路チップの端部を弾性的に固定・支持する構造の歪み緩衝構造部と、
を備える、電子デバイス。 A semiconductor circuit chip with a built-in electronic circuit with terminals formed on the surface,
A flexible substrate with at least a flexible wiring film formed on its surface,
The structure has a wiring film formed on the surface thereof, and one end of the wiring film is connected to the terminal of the semiconductor circuit chip, the other end of the wiring film is connected to the flexible wiring film, and the semiconductor circuit. A strain buffer structure portion having a structure that elastically fixes and supports the end portion of the semiconductor circuit chip with the chip and the flexible substrate separated from each other .
Equipped with an electronic device. 前記フレキシブル基板は、フレキシブルセンサが形成されてなる、請求項１記載の電子デバイス。The electronic device according to claim 1, wherein the flexible substrate is formed with a flexible sensor. 前記半導体回路チップは、前記フレキシブル基板の表面と離間されてなる、請求項１または２記載の電子デバイス。The electronic device according to claim 1 or 2, wherein the semiconductor circuit chip is separated from the surface of the flexible substrate. 前記歪み緩衝構造部は、
前記フレキシブル基板とは異なる極薄の基板に形成された前記半導体回路チップの側縁部と、前記極薄の基板の端部との間を別々に接続する、平面が所定形状の複数の接続用基板部分の上に前記配線膜が形成されており、前記複数の接続用基板部分の各一方の端部の上の前記配線膜の一端を前記半導体回路チップの端子に電気的に接続し、前記複数の接続用基板部分の各他方の端部のみを前記フレキシブル基板にそれぞれ前記半導体回路チップと前記フレキシブル基板とを離間させた状態で弾性的に固定・支持すると共に前記配線膜の他端を前記フレキシブル配線膜に電気的に接続した構造である、請求項１〜３のうちいずれか一項記載の電子デバイス。 The strain buffer structure is
For connecting a plurality of connections having a predetermined flat surface, which separately connect the side edge portion of the semiconductor circuit chip formed on an ultrathin substrate different from the flexible substrate and the end portion of the ultrathin substrate. The wiring film is formed on the substrate portion, and one end of the wiring film on one end of each of the plurality of connection substrate portions is electrically connected to the terminal of the semiconductor circuit chip. Only the other end of each of the plurality of connection substrate portions is elastically fixed and supported on the flexible substrate with the semiconductor circuit chip and the flexible substrate separated from each other, and the other end of the wiring film is attached to the flexible substrate. it is a structure that is electrically connected to the flexible wiring layer, the electronic device of any one of claims 1-3. 前記フレキシブル基板は、
前記半導体回路チップの搭載用矩形領域と、前記矩形領域の側縁部と基板側縁部に沿う四角枠との間を平面が所定形状の複数の接続部でそれぞれ接続する形状の基板部分を残した開口部を有するとともに、表面に少なくともフレキシブル配線膜及びフレキシブルセンサが形成されており、
前記歪み緩衝構造部は、
前記フレキシブル基板の前記接続部の表面に前記配線膜が形成された構造であり、前記フレキシブル基板の前記矩形領域に搭載された前記半導体回路チップを前記接続部及び前記四角枠で弾性的に固定・支持すると共に、前記配線膜の一端を前記半導体回路チップの前記端子に接続し、かつ、前記配線膜の他端を前記フレキシブル配線膜に接続する、請求項１〜３のうちいずれか一項記載の電子デバイス。 The flexible substrate is
A substrate portion having a shape in which the rectangular region for mounting the semiconductor circuit chip and the side edge portion of the rectangular region and the square frame along the side edge portion of the substrate are connected by a plurality of connection portions having a predetermined plane is left. It has a rectangular opening and at least a flexible wiring film and a flexible sensor are formed on the surface.
The strain buffer structure is
The structure is such that the wiring film is formed on the surface of the connection portion of the flexible substrate, and the semiconductor circuit chip mounted on the rectangular region of the flexible substrate is elastically fixed by the connection portion and the square frame. The invention according to any one of claims 1 to 3 , wherein one end of the wiring film is connected to the terminal of the semiconductor circuit chip, and the other end of the wiring film is connected to the flexible wiring film. Electronic device. 前記歪み緩衝構造部は、
前記フレキシブル基板、及び前記半導体回路チップが形成された極薄の基板とはそれぞれ異なる弾性体基板に形成されており、前記弾性体基板が前記半導体回路チップの搭載用矩形領域と、前記矩形領域の側縁部にそれぞれの一端が接続された平面が所定形状の複数の接続部とからなり、かつ、前記複数の接続部の表面に配線膜が形成された構造であり、
前記配線膜の一端を前記弾性体基板の矩形領域に搭載された前記半導体回路チップの端子に電気的に接続し、かつ、前記複数の接続部の他端をスペーサを介して前記フレキシブル基板に前記半導体回路チップと離間させた状態で弾性的に固定・支持するとともに、前記２つの接続部の他端上の前記配線膜と前記フレキシブル配線膜とを前記スペーサを覆う導電性部材で電気的に接続する、請求項１〜３のうちいずれか一項記載の電子デバイス。 The strain buffer structure is
The flexible substrate and the ultrathin substrate on which the semiconductor circuit chip is formed are formed on an elastic substrate, and the elastic substrate is formed of a rectangular region for mounting the semiconductor circuit chip and the rectangular region. The structure is such that a flat surface to which one end of each is connected to a side edge portion is composed of a plurality of connecting portions having a predetermined shape, and a wiring film is formed on the surface of the plurality of connecting portions.
One end of the wiring film is electrically connected to the terminal of the semiconductor circuit chip mounted in the rectangular region of the elastic body substrate, and the other end of the plurality of connecting portions is connected to the flexible substrate via a spacer. It is elastically fixed and supported in a state of being separated from the semiconductor circuit chip, and the wiring film and the flexible wiring film on the other ends of the two connecting portions are electrically connected by a conductive member covering the spacer. to the electronic device of any one of claims 1-3. 前記所定形状は、ジグザグ形状、Ｓ字形状又はメッシュ状であることを特徴とする請求項４〜６のうちいずれか一項記載の電子デバイス。 The electronic device according to any one of claims 4 to 6 , wherein the predetermined shape is a zigzag shape, an S shape, or a mesh shape. 表面に端子が形成された電子回路を内蔵する半導体回路チップを作製する工程と、
表面に少なくともフレキシブル配線膜が形成されたフレキシブル基板を作製する工程と、
表面に配線膜が形成された構造の歪み緩衝構造部により、前記半導体回路チップの前記端子に前記配線膜の一端を接続し、かつ、前記配線膜の他端を前記フレキシブル配線膜に接続すると共に、前記半導体回路チップと前記フレキシブル基板とを離間させた状態で前記半導体回路チップの端部を弾性的に固定・支持する固定工程と、
を含む、電子デバイスの製造方法。 The process of manufacturing a semiconductor circuit chip containing an electronic circuit with terminals formed on the surface,
The process of manufacturing a flexible substrate with at least a flexible wiring film formed on the surface,
One end of the wiring film is connected to the terminal of the semiconductor circuit chip, and the other end of the wiring film is connected to the flexible wiring film by the strain buffer structure portion having a structure in which the wiring film is formed on the surface. A fixing step of elastically fixing and supporting the end portion of the semiconductor circuit chip with the semiconductor circuit chip and the flexible substrate separated from each other .
Manufacturing methods for electronic devices, including . 前記フレキシブル基板を作製する工程は、前記フレキシブル基板の表面にフレキシブルセンサを形成する工程を含む、請求項８記載の電子デバイスの製造方法。The method for manufacturing an electronic device according to claim 8, wherein the step of manufacturing the flexible substrate includes a step of forming a flexible sensor on the surface of the flexible substrate. 前記半導体回路チップを作製する工程は、前記フレキシブル基板とは異なる極薄の基板に前記半導体回路チップを作製する工程であり、
前記固定工程は、
平面が所定形状で、かつ、表面に配線膜が形成されており、前記配線膜の一端が前記半導体回路チップの前記端子にそれぞれの一端が別々に電気的に接続された複数の接続部を前記極薄の基板に形成する接続部形成工程と、
前記複数の接続部のそれぞれの前記配線膜の他端を前記フレキシブル配線膜に電気的に接続すると共に、前記複数の接続部の前記配線膜の他端が形成されている前記極薄の基板部分で、前記半導体回路チップと前記フレキシブル基板とを離間させた状態で固定する工程とからなる、請求項８または９記載の電子デバイスの製造方法。 The step of manufacturing the semiconductor circuit chip is a step of manufacturing the semiconductor circuit chip on an ultrathin substrate different from the flexible substrate.
The fixing step is
A plurality of connecting portions having a predetermined shape on a flat surface and a wiring film formed on the surface thereof, one end of which is electrically connected to the terminal of the semiconductor circuit chip separately. The process of forming a connection on an ultra-thin substrate,
The ultra-thin substrate portion in which the other end of the wiring film of each of the plurality of connection portions is electrically connected to the flexible wiring film and the other end of the wiring film of the plurality of connection portions is formed. The method for manufacturing an electronic device according to claim 8 or 9 , further comprising a step of fixing the semiconductor circuit chip and the flexible substrate in a separated state. 前記接続部形成工程は、
前記半導体回路チップの前記端子に一端が別々に接続され、他端が開放とされた平面形状が前記所定形状の複数の配線膜をシリコン基板上に形成する工程と、
前記半導体回路チップ及び前記配線膜がそれぞれ形成された前記シリコン基板の裏側からエッチングにより、前記半導体回路チップを残し、かつ、前記複数の配線膜が形成されている前記シリコン基板部分を薄く残した凹部を形成する工程と、
前記凹部が形成された前記シリコン基板から、前記半導体回路チップ及び前記複数の配線膜が表面に形成された薄い前記シリコン基板部分を剥離し、前記複数の配線膜が表面に形成された薄い前記シリコン基板部分を前記極薄の基板上の複数の接続部として得る工程とからなり、
前記半導体回路チップと前記フレキシブル基板とを離間させた状態で固定する工程は、
前記複数の配線膜の各端部の直下の前記極薄の基板部分のみを、前記フレキシブル基板の表面と離間させた状態でスペーサを介して固定する工程と、
前記フレキシブル配線膜と前記複数の配線膜の各端部とを導電性部材で電気的に接続する工程とからなる、請求項１０記載の電子デバイスの製造方法。 The connection portion forming step is
A step of forming a plurality of wiring films having a planar shape having a predetermined shape with one end separately connected to the terminal of the semiconductor circuit chip and the other end open on a silicon substrate.
A recess in which the semiconductor circuit chip is left by etching from the back side of the silicon substrate on which the semiconductor circuit chip and the wiring film are formed, and the silicon substrate portion on which the plurality of wiring films are formed is left thin. And the process of forming
The semiconductor circuit chip and the thin silicon substrate portion on which the plurality of wiring films are formed are peeled off from the silicon substrate on which the recess is formed, and the thin silicon on which the plurality of wiring films are formed on the surface. becomes a substrate portion and a step of obtaining a plurality of connections on the substrate of the ultrathin,
The step of fixing the semiconductor circuit chip and the flexible substrate in a separated state is
A step of fixing only the ultrathin substrate portion directly below each end of the plurality of wiring films with a spacer in a state of being separated from the surface of the flexible substrate.
The composed with each end of the flexible wiring film and the plurality of wiring films and a step of electrically connecting a conductive member, a method for fabricating an electronic device of claim 10, wherein. 前記フレキシブル基板を作製する工程は、
表面に少なくともフレキシブル配線膜及びフレキシブルセンサが形成された加工前のフレキシブル基板に対し、前記半導体回路チップの搭載用矩形領域と、前記矩形領域の側縁部と基板側縁部に沿う四角枠との間を平面が所定形状で、かつ、表面に前記配線膜が形成されるとともに、前記配線膜の一端が前記フレキシブル配線膜にそれぞれ電気的に接続された形状の複数の接続部とを残した開口部を形成して加工処理したフレキシブル基板を作製する工程であり、
前記固定工程は、
前記加工処理したフレキシブル基板の前記矩形領域に、前記半導体回路チップの端子が前記複数の接続部のそれぞれの配線膜の他端に電気的に接続されるように前記半導体回路チップを搭載する工程を有し、前記半導体回路チップを前記複数の接続部及び前記四角枠で弾性的に固定・支持する、請求項８または９記載の電子デバイスの製造方法。 The step of manufacturing the flexible substrate is
For a flexible substrate before processing in which at least a flexible wiring film and a flexible sensor are formed on the surface, a rectangular region for mounting the semiconductor circuit chip, a side edge portion of the rectangular region, and a square frame along the side edge portion of the substrate are provided. An opening in which a flat surface has a predetermined shape and the wiring film is formed on the surface thereof, and one end of the wiring film is electrically connected to the flexible wiring film. This is the process of producing a flexible substrate that has been processed by forming a portion.
The fixing step is
A step of mounting the semiconductor circuit chip in the rectangular region of the processed flexible substrate so that the terminals of the semiconductor circuit chip are electrically connected to the other ends of the wiring films of the plurality of connection portions. The method for manufacturing an electronic device according to claim 8 or 9 , wherein the semiconductor circuit chip is elastically fixed and supported by the plurality of connecting portions and the square frame. 前記固定工程は、
前記フレキシブル基板、及び前記半導体回路チップが形成された極薄の基板とはそれぞれ異なる弾性体基板に対し、前記半導体回路チップの搭載用矩形領域と、前記矩形領域の側縁部にそれぞれの一端が接続された平面が所定形状で、かつ、表面に配線膜が形成された複数の接続部とを形成する工程と、
前記極薄の基板に形成された前記半導体回路チップの端子が、前記複数の接続部のそれぞれの配線膜の一端に電気的に接続されるように前記半導体回路チップを前記矩形領域に搭載する工程と、
前記複数の接続部の他端をスペーサを介して前記フレキシブル基板に前記半導体回路チップと離間させた状態で弾性的に固定・支持するとともに、前記複数の接続部の他端上の前記配線膜と前記フレキシブル配線膜とを前記スペーサを覆う導電性部材で電気的に接続する工程とからなる、請求項８または９記載の電子デバイスの製造方法。 The fixing step is
For an elastic substrate different from the flexible substrate and the ultrathin substrate on which the semiconductor circuit chip is formed, one end of each is provided on a rectangular region for mounting the semiconductor circuit chip and a side edge portion of the rectangular region. A step of forming a plurality of connecting portions having a predetermined shape on the connected flat surface and having a wiring film formed on the surface thereof.
A step of mounting the semiconductor circuit chip in the rectangular region so that the terminals of the semiconductor circuit chip formed on the ultrathin substrate are electrically connected to one end of each wiring film of the plurality of connection portions. When,
The other ends of the plurality of connecting portions are elastically fixed and supported on the flexible substrate in a state of being separated from the semiconductor circuit chip via spacers, and the wiring film on the other ends of the plurality of connecting portions is attached. wherein comprising a step of electrically connecting the flexible wiring film by a conductive member for covering the spacer, a method for fabricating an electronic device according to claim 8 or 9, wherein. 前記所定形状は、ジグザグ形状、Ｓ字形状又はメッシュ状である、請求項１０〜１３のうちいずれか一項記載の電子デバイスの製造方法。 Wherein the predetermined shape, a zigzag shape, an S-shaped or mesh-like, a method for fabricating an electronic device of any one of claims 10 to 13.
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