JP6777815B2 - 半導体装置の製造方法および半導体装置の中間体 - Google Patents
半導体装置の製造方法および半導体装置の中間体 Download PDFInfo
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- JP6777815B2 JP6777815B2 JP2019517685A JP2019517685A JP6777815B2 JP 6777815 B2 JP6777815 B2 JP 6777815B2 JP 2019517685 A JP2019517685 A JP 2019517685A JP 2019517685 A JP2019517685 A JP 2019517685A JP 6777815 B2 JP6777815 B2 JP 6777815B2
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Description
[1] 支持基板上に、複数の半導体チップを、その回路面が前記支持基板と対向するように固定する第1工程と、前記複数の半導体チップ上に封止樹脂を含む封止材を3次元造形法で付与することにより、前記半導体チップが前記封止材によって埋め込まれた封止層を、間隔を空けて複数形成する第2工程と、前記封止層を硬化又は固化させる第3工程と、前記硬化又は固化された封止層を前記支持基板から剥離して、封止体を得る第4工程とを含む、半導体装置の製造方法。
[2] 前記第2工程において、前記支持基板を平面視したとき、隣り合う2つの前記封止層間の間隔の最小値の、前記封止層の最大幅に対する割合は、0.19〜10%である、[1]に記載の半導体装置の製造方法。
[3] 前記支持基板上に、前記半導体チップを囲む枠体を複数形成する工程をさらに含み、前記第2工程において、前記枠体の内側に前記封止材を付与することにより、前記半導体チップが封止材で埋め込まれた封止層を形成する、[1]又は[2]に記載の半導体装置の製造方法。
[4] 前記枠体は、60〜250℃における線膨脹係数が35ppm/K以下の材料を含む、[3]に記載の半導体装置の製造方法。
[5] 前記枠体は、60〜250℃における引張弾性率が、硬化又は固化後の前記封止材の引張弾性率よりも0.5GPa以上低い樹脂を含む、[3]に記載の半導体装置の製造方法。
[6] 前記封止材は、充填剤をさらに含んでいてもよく、前記封止材の全質量に対する前記充填剤の含有率は、10質量%以下である、[1]〜[5]のいずれかに記載の半導体装置の製造方法。
[7] 前記3次元造形法で前記封止材を前記半導体チップ上に付与する際の前記封止材の粘度は、1〜20mPa・sである、[1]〜[6]のいずれかに記載の半導体装置の製造方法。
[8] 前記封止層のガラス転移温度は、110℃以上である、[1]〜[7]のいずれかに記載の半導体装置の製造方法。
[9] 前記封止樹脂は、エポキシ樹脂、ポリイミド樹脂及び尿素樹脂からなる群より選ばれる少なくとも1種である、[1]〜[8]のいずれかに記載の半導体装置の製造方法。
[10] 前記封止体の前記半導体チップが露出した面に、再配線層を3次元造形法により形成する工程をさらに含む、[1]〜[9]のいずれかに記載の半導体装置の製造方法。
[11] 前記封止体の前記半導体チップが露出した面の前記半導体チップの外周部に、グランド配線を3次元造形法により形成する工程をさらに含む、[1]〜[10]のいずれかに記載の半導体装置の製造方法。
[12] 前記封止体の前記半導体チップが露出していない面の少なくとも一部に、電磁波シールド層を3次元造形法により形成する工程をさらに含む、[1]〜[11]のいずれかに記載の半導体装置の製造方法。
[13] 前記封止体は、複数の前記半導体チップを含み、前記封止体に含まれる前記複数の半導体チップ間を切断する工程をさらに含む、[1]〜[12]のいずれかに記載の半導体装置の製造方法。
[14] 支持基板と、前記支持基板上に、回路面が前記支持基板と対向するように固定された複数の半導体チップと、前記半導体チップが封止材に埋め込まれ、かつ互いに間隔を空けて配置された複数の封止層とを有する、半導体装置の中間体。
[15] 前記支持基板を平面視したとき、隣り合う2つの前記封止層間の間隔の最小値の、前記封止層の最大幅に対する割合は、0.19〜10%である、[14]に記載の半導体装置の中間体。
[16] 前記封止層の間隔の最小値は、0.18〜6mmであり、かつ前記封止層の最大幅は、10〜60mmである、[15]に記載の半導体装置の中間体。
まず、支持基板11を準備する(図1A参照)。支持基板11の例には、石英基板、無アルカリガラス基板等のガラス基板;SUS基板等の金属板;シリコンウェハ、SiCウェハ、GaAsウェハ等のウェハ基板;樹脂基板等が含まれる。中でも、封止体21の反りやダイシフトの抑制を目的とした熱膨張率制御の観点では線膨張係数が低いことが好ましく、ガラス基板やSUS基板が好ましい。
支持基板11上に固定された複数の半導体チップ13の裏面13B(回路面とは反対側の面)に、封止樹脂を含む封止材17を付与する。それにより、支持基板11上に、半導体チップ13が封止材17によって埋め込まれた封止層19を、間隔を空けて複数形成する。
得られた封止層19を硬化又は固化させる(図1E参照)。
得られた中間体の硬化又は固化された封止層19を支持基板11から剥離し、封止体21を得る(図1F参照)。
さらに、得られた封止体21の半導体チップ13が露出した面に、再配線層23を形成してもよい(再配線層23を形成する工程、図1G参照)。
支持基板11、半導体チップ13および封止層19の材質を以下のような組み合わせにし、室温(24℃)から150℃に加熱した後、室温まで冷却した際の半導体チップ13の移動距離の最大値を、解析ソフトウェアANSYSを用いて有限要素法で計算した。
そして、隣り合う封止層19同士の間隔dが半導体チップ13の移動距離の最大値を超えていれば、封止層19同士の接触を抑制できること、および半導体チップ13の移動距離は封止層19の最大幅(W)と比例することを考慮し、封止層19同士の間隔の最小値dの、封止層19の最大幅Wに対する割合(d/W×100)の範囲を特定した。
支持基板11の材質:SUS基板(ヤング率:197000MPa、ポアソン比:0.30、線膨張係数:17.3ppm/℃)
封止層19の材質:エポキシ樹脂(ヤング率:3000MPa、ポアソン比:0.34、線膨張係数:8ppm/℃(Tg以下の温度)、17.3ppm/℃(Tgを超える温度)、硬化温度:150℃)
半導体チップ13の材質:シリコン(ヤング率:131000MPa、ポアソン比:0.27、線膨張係数:2.62ppm/℃)
冷却過程での半導体チップ13の移動距離の最大値(即ち、ウェハ(支持基板11)の中心から最も離れた位置にある半導体チップ13の移動距離)は0.27mmであり、当該半導体チップ13の移動距離の最大値の、封止層19の最大幅(W)に対する割合は0.18%と算出された。このことから、隣り合う2つの封止層19同士の間隔の最小値dの、封止層19の最大幅Wに対する割合(d/W×100)が0.19%以上となるように、隣り合う封止層19同士の間隔を設定すれば、隣り合う封止層19同士の接触を高度に抑制できることがわかる。
13 半導体チップ
15 粘着シート
17 封止材
17’ 硬化又は固化した封止材
19 封止層
21 封止体
23 再配線層
25 バンプ
27、27’ 半導体パッケージ
29 枠体
W (封止層19の)最大幅
d (封止層19同士の)間隔の最小幅
L 光
Claims (16)
- 支持基板上に、複数の半導体チップを、その回路面が前記支持基板と対向するように固定する第1工程と、
前記複数の半導体チップ上に封止樹脂を含む封止材を3次元造形法で付与することにより、前記半導体チップが前記封止材によって埋め込まれた封止層を、間隔を空けて複数形成する第2工程と、
前記封止層を硬化又は固化させる第3工程と、
前記硬化又は固化された封止層を前記支持基板から剥離して、封止体を得る第4工程と
を含む、
半導体装置の製造方法。 - 前記第2工程において、前記支持基板を平面視したとき、隣り合う2つの前記封止層間の間隔の最小値の、前記封止層の最大幅に対する割合は、0.19〜10%である、
請求項1に記載の半導体装置の製造方法。 - 前記支持基板上に、前記半導体チップを囲む枠体を複数形成する工程をさらに含み、
前記第2工程において、前記枠体の内側に前記封止材を付与することにより、前記半導体チップが前記封止材で埋め込まれた封止層を形成する、
請求項1又は2に記載の半導体装置の製造方法。 - 前記枠体は、60〜250℃における線膨脹係数が35ppm/K以下の材料を含む、
請求項3に記載の半導体装置の製造方法。 - 前記枠体は、60〜250℃における引張弾性率が、硬化又は固化後の前記封止材の引張弾性率よりも0.5GPa以上低い樹脂を含む、
請求項3に記載の半導体装置の製造方法。 - 前記封止材は、充填剤をさらに含んでいてもよく、
前記封止材の全質量に対する前記充填剤の含有率は、10質量%以下である、
請求項1〜5のいずれか一項に記載の半導体装置の製造方法。 - 前記3次元造形法で前記封止材を前記半導体チップ上に付与する際の前記封止材の粘度は、1〜20mPa・sである、
請求項1〜6のいずれか一項に記載の半導体装置の製造方法。 - 前記封止層のガラス転移温度は、110℃以上である、
請求項1〜7のいずれか一項に記載の半導体装置の製造方法。 - 前記封止樹脂は、エポキシ樹脂、ポリイミド樹脂及び尿素樹脂からなる群より選ばれる少なくとも1種である、
請求項1〜8のいずれか一項に記載の半導体装置の製造方法。 - 前記封止体の前記半導体チップが露出した面に、再配線層を3次元造形法により形成する工程をさらに含む、
請求項1〜9のいずれか一項に記載の半導体装置の製造方法。 - 前記封止体の前記半導体チップが露出した面の前記半導体チップの外周部に、グランド配線を3次元造形法により形成する工程をさらに含む、
請求項1〜10のいずれか一項に記載の半導体装置の製造方法。 - 前記封止体の前記半導体チップが露出していない面の少なくとも一部に、電磁波シールド層を3次元造形法により形成する工程をさらに含む、
請求項1〜11のいずれか一項に記載の半導体装置の製造方法。 - 前記封止体は、複数の前記半導体チップを含み、
前記封止体に含まれる前記複数の半導体チップ間を切断する工程をさらに含む、
請求項1〜12のいずれか一項に記載の半導体装置の製造方法。 - 支持基板と、
前記支持基板上に、回路面が前記支持基板と対向するように配置された複数の半導体チップと、
前記支持基板と前記複数の半導体チップとの間に配置された粘着シートと、
前記半導体チップが封止材に埋め込まれ、かつ互いに間隔を空けて配置された複数の封止層とを有し、
前記半導体チップの回路面は、前記粘着シートと接して固定されている、
半導体装置の中間体。 - 前記支持基板を平面視したとき、隣り合う2つの前記封止層間の間隔の最小値の、前記封止層の最大幅に対する割合は、0.19〜10%である、
請求項14に記載の半導体装置の中間体。 - 前記封止層の間隔の最小値は、0.18〜6mmであり、かつ
前記封止層の最大幅は、10〜60mmである、
請求項15に記載の半導体装置の中間体。
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