JP6776709B2 - 電力増幅装置、半導体集積回路および電力増幅装置の制御方法 - Google Patents
電力増幅装置、半導体集積回路および電力増幅装置の制御方法 Download PDFInfo
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Description
Vgs1=Vgg1−Rs×Idc1 ・・・ [式1]
(付記1)
入力電力を増幅する主増幅器と、
前記入力電力が所定レベルを超えたときに前記入力電力を増幅する補助増幅器と、
前記主増幅器のソースとグラウンド間に設けられ、前記入力電力が所定の値以上になったとき、前記主増幅器のソース電位が増加するように制御する制御回路と、を有する、
ことを特徴とする電力増幅装置。
前記制御回路は、
前記主増幅器のソースとグラウンドの間に設けられた抵抗素子を含む、
ことを特徴とする付記1に記載の電力増幅装置。
前記制御回路は、さらに、
前記主増幅器のソースとグラウンドの間に、前記抵抗素子と並列に設けられた容量素子を含む、
ことを特徴とする付記2に記載の電力増幅装置。
前記制御回路は、さらに、
前記主増幅器のソースとグラウンドの間に、前記抵抗素子および前記容量素子と並列に設けられたダイオード素子を含む、
ことを特徴とする付記3に記載の電力増幅装置。
前記制御回路は、
前記主増幅器のソースとグラウンドの間に、並列に設けられたNTCサーミスタ素子および容量素子を含む、
ことを特徴とする付記1に記載の電力増幅装置。
前記容量素子は、前記主増幅器のソースと、前記グラウンドと、前記主増幅器のソースおよび前記グラウンド間に設けられた絶縁フィルムにより形成される、
ことを特徴とする付記3乃至付記5のいずれか1項に記載の電力増幅装置。
前記制御回路による前記主増幅器のソースとグラウンド間の電圧降下量は、前記主増幅器のゲートバイアス電圧と前記補助増幅器のゲートバイアス電圧の差に等しい、
ことを特徴とする付記1乃至付記6のいずれか1項に記載の電力増幅装置。
前記主増幅器は、A級またはAB級で動作する第1トランジスタで形成され、
前記補助増幅器は、B級またはC級で動作する第2トランジスタで形成される、
ことを特徴とする付記1乃至付記7のいずれか1項に記載の電力増幅装置。
前記電力増幅装置は、ドハティ型の電力増幅装置である、
ことを特徴とする付記1乃至付記8のいずれか1項に記載の電力増幅装置。
付記1乃至付記9のいずれか1項に記載の電力増幅装置を含む、
ことを特徴とする半導体集積回路。
入力電力を増幅する主増幅器と、前記入力電力が所定レベルを超えたときに前記入力電力を増幅する補助増幅器と、を含むドハティ型の電力増幅装置の制御方法であって、
前記入力電力が所定の値以上になったとき、前記主増幅器のソース電位が増加するように制御する、
ことを特徴とする電力増幅装置の制御方法。
前記入力電力が所定の値以上になったときに増加する前記主増幅器のソース電位は、前記主増幅器のゲートバイアス電圧と前記補助増幅器のゲートバイアス電圧の差に等しい、
ことを特徴とする付記11に記載の電力増幅装置の制御方法。
前記主増幅器は、A級またはAB級で動作する第1トランジスタで形成され、
前記補助増幅器は、B級またはC級で動作する第2トランジスタで形成される、
ことを特徴とする付記11または付記12に記載の電力増幅装置の制御方法。
2 補助増幅器(ピーク増幅器)
5 制御回路
31,32 λ/4伝送線路(1/4波長伝送線路)
41〜44 整合回路
51 抵抗素子
52 容量素子
53 ダイオード素子
54 サーミスタ素子
Claims (10)
- 入力信号が入力される入力端子と、
前記入力信号を受け取って増幅する主増幅トランジスタと、
前記入力信号を受け取り、前記入力信号が所定レベルを超えたときに前記入力信号を増幅する補助増幅トランジスタと、
前記主増幅トランジスタのソースとグラウンド間に設けられ、前記入力信号が所定の値以上になったとき、前記主増幅トランジスタのソース電位が増加するように制御する制御回路と、
前記主増幅トランジスタの出力信号および前記補助増幅トランジスタの出力信号が出力される出力端子と、を有する、
ことを特徴とする電力増幅装置。 - 前記制御回路は、
前記主増幅トランジスタのソースとグラウンドの間に設けられた抵抗素子を含む、
ことを特徴とする請求項1に記載の電力増幅装置。 - 前記制御回路は、さらに、
前記主増幅トランジスタのソースとグラウンドの間に、前記抵抗素子と並列に設けられた容量素子を含む、
ことを特徴とする請求項2に記載の電力増幅装置。 - 前記制御回路は、さらに、
前記主増幅トランジスタのソースとグラウンドの間に、前記抵抗素子および前記容量素子と並列に設けられたダイオード素子を含む、
ことを特徴とする請求項3に記載の電力増幅装置。 - 前記制御回路は、
前記主増幅トランジスタのソースとグラウンドの間に、並列に設けられたNTCサーミスタ素子および容量素子を含む、
ことを特徴とする請求項1に記載の電力増幅装置。 - 前記容量素子は、前記主増幅トランジスタのソースと、前記グラウンドと、前記主増幅トランジスタのソースおよび前記グラウンド間に設けられた絶縁フィルムにより形成される、
ことを特徴とする請求項3乃至請求項5のいずれか1項に記載の電力増幅装置。 - 前記制御回路による前記主増幅トランジスタのソースとグラウンド間の電圧降下量は、前記主増幅トランジスタのゲートバイアス電圧と前記補助増幅トランジスタのゲートバイアス電圧の差に等しい、
ことを特徴とする請求項1乃至請求項6のいずれか1項に記載の電力増幅装置。 - 請求項1乃至請求項7のいずれか1項に記載の電力増幅装置を含む、
ことを特徴とする半導体集積回路。 - 入力信号が入力される入力端子と、前記入力信号を受け取って増幅する主増幅トランジスタと、前記入力信号を受け取り、前記入力信号が所定レベルを超えたときに前記入力信号を増幅する補助増幅トランジスタと、前記主増幅トランジスタの出力信号および前記補助増幅トランジスタの出力信号が出力される出力端子と、を含むドハティ型の電力増幅装置の制御方法であって、
前記入力信号が所定の値以上になったとき、前記主増幅トランジスタのソース電位が増加するように制御する、
ことを特徴とする電力増幅装置の制御方法。 - 前記入力信号が所定の値以上になったときに増加する前記主増幅トランジスタのソース電位は、前記主増幅トランジスタのゲートバイアス電圧と前記補助増幅トランジスタのゲートバイアス電圧の差に等しい、
ことを特徴とする請求項9に記載の電力増幅装置の制御方法。
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US4631493A (en) * | 1985-03-18 | 1986-12-23 | Eaton Corporation | Circuit for DC biasing |
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US5374899A (en) * | 1993-11-10 | 1994-12-20 | Itt Corporation | Self biased power amplifier employing FETs |
US5892400A (en) * | 1995-12-15 | 1999-04-06 | Anadigics, Inc. | Amplifier using a single polarity power supply and including depletion mode FET and negative voltage generator |
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US6683499B2 (en) * | 2000-12-27 | 2004-01-27 | Emhiser Research, Inc. | Divided-voltage fet power amplifiers |
US20020130720A1 (en) * | 2001-03-15 | 2002-09-19 | Motorola, Inc. | Distributed amplifier with transistors in a cascode configuration and negative feedback |
KR100546491B1 (ko) * | 2001-03-21 | 2006-01-26 | 학교법인 포항공과대학교 | 초고주파 도허티 증폭기의 출력 정합 장치 |
ATE525800T1 (de) * | 2002-08-19 | 2011-10-15 | Nxp Bv | Hochleistungs-doherty-verstärker |
WO2008012883A1 (fr) * | 2006-07-26 | 2008-01-31 | Panasonic Corporation | Périphérique de communication sans fil |
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US20180041177A1 (en) | 2018-02-08 |
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