JP6747280B2 - Method for manufacturing semiconductor device - Google Patents

Method for manufacturing semiconductor device Download PDF

Info

Publication number
JP6747280B2
JP6747280B2 JP2016247972A JP2016247972A JP6747280B2 JP 6747280 B2 JP6747280 B2 JP 6747280B2 JP 2016247972 A JP2016247972 A JP 2016247972A JP 2016247972 A JP2016247972 A JP 2016247972A JP 6747280 B2 JP6747280 B2 JP 6747280B2
Authority
JP
Japan
Prior art keywords
semiconductor element
semiconductor device
substrate
manufacturing
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2016247972A
Other languages
Japanese (ja)
Other versions
JP2018101730A (en
Inventor
昌基 杉本
昌基 杉本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nichia Corp
Original Assignee
Nichia Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nichia Corp filed Critical Nichia Corp
Priority to JP2016247972A priority Critical patent/JP6747280B2/en
Publication of JP2018101730A publication Critical patent/JP2018101730A/en
Application granted granted Critical
Publication of JP6747280B2 publication Critical patent/JP6747280B2/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48257—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a die pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors

Landscapes

  • Die Bonding (AREA)

Description

本開示は、半導体装置の製造方法に関する。 The present disclosure relates to a method for manufacturing a semiconductor device.

半導体素子を搬送する際に、吸着孔を備えたコレットが用いられることが知られている。例えば、ダイボンド工程においては、まず、ウエハシート上に載置された半導体素子の上面にコレットの先端を当接させ、その先端に設けられた吸着孔の開口部によって半導体素子を吸着する。コレットで半導体素子を吸着した状態で、ウエハシート上から半導体素子をピックアップする。所定のダイボンド位置にコレットを移動し、吸着を解除することで半導体素子を移送する。コレットとして、吸着孔を複数備えたタイプが知られている（例えば、特許文献１） It is known that a collet having suction holes is used when a semiconductor element is transported. For example, in the die bonding process, first, the tip of the collet is brought into contact with the upper surface of the semiconductor element placed on the wafer sheet, and the semiconductor element is sucked by the opening of the suction hole provided at the tip. The semiconductor element is picked up from the wafer sheet while the semiconductor element is sucked by the collet. The semiconductor element is transferred by moving the collet to a predetermined die bond position and releasing the suction. As a collet, a type having a plurality of suction holes is known (for example, Patent Document 1).

特開２０００−３２３５０４号公報JP 2000-323504 A

コレットは、硬質な材料によって形成されているため、吸着時に半導体素子にダメージを与えたり、損傷させたりする場合がある。 Since the collet is made of a hard material, it may damage or damage the semiconductor element during adsorption.

本実施形態は、以下の構成を含む。
半導体素子が重ねて収容された収容部を備えた本体と、収容部の上側開口部に備えられ、エア供給口を備えたキャップと、収容部の下側開口部に備えられるストッパと、を備えた半導体素子収容済のカートリッジを準備する工程と、基板を準備する工程と、基板の上方にカートリッジを配置した後、エア供給口から収容部内にエアを供給し、半導体素子を下側開口部から放出し、基板の上面に半導体素子を載置する工程と、を備える半導体装置の製造方法。 The present embodiment includes the following configurations.
A main body having a housing portion in which semiconductor elements are stacked and housed; a cap provided at an upper opening of the housing portion and having an air supply port; and a stopper provided at a lower opening portion of the housing portion. The step of preparing the cartridge containing the semiconductor element, the step of preparing the substrate, and the step of arranging the cartridge above the substrate, and then supplying the air from the air supply port to the inside of the accommodating portion, the semiconductor element from the lower opening Discharging, and mounting a semiconductor element on the upper surface of the substrate.

以上により、半導体素子にダメージを与えにくくすることができる。 As described above, it is possible to make the semiconductor element less likely to be damaged.

図１は、実施形態に係る半導体装置の製造方法を示す概略図である。FIG. 1 is a schematic diagram showing a method for manufacturing a semiconductor device according to an embodiment. 図２は、実施形態に係る半導体装置の製造方法を示す概略図である。FIG. 2 is a schematic view showing the method of manufacturing the semiconductor device according to the embodiment. 図３は、実施形態に係る半導体装置の製造方法を示す概略図である。FIG. 3 is a schematic view showing the method for manufacturing the semiconductor device according to the embodiment. 図４Ａは、実施形態に係る半導体装置の製造方法に用いられる半導体素子の概略上面図である。FIG. 4A is a schematic top view of a semiconductor element used in the method for manufacturing a semiconductor device according to the embodiment. 図４Ａは、実施形態に係る半導体装置の製造方法に用いられる半導体素子の概略断面図である。FIG. 4A is a schematic cross-sectional view of a semiconductor element used in the semiconductor device manufacturing method according to the embodiment. 図５は、実施形態に係る半導体装置の製造方法によって得られる半導体装置の概略断面図である。FIG. 5 is a schematic cross-sectional view of a semiconductor device obtained by the method for manufacturing a semiconductor device according to the embodiment.

本発明を実施するための形態を、以下に図面を参照しながら説明する。ただし、以下に示す形態は、本発明の技術思想を具現化するためのコレット及び半導体装置の製造方法を例示するものであって、以下に限定するものではない。また、実施の形態に記載されている構成部品の寸法、材質、形状、その相対的配置等は、特定的な記載がない限り、本発明の範囲をそれのみに限定する趣旨ではい。尚、各図面が示す部材の大きさや位置関係等は、説明を明確にするために誇張していることがある。また、必要に応じて特定の方向や位置を示す用語（例えば、「上」、「下」、「右」、「左」および、それらの用語を含む別の用語）を用いる。これらの用語の使用は図面を参照した発明の理解を容易にするためであって、これらの用語の意味によって本発明の技術的範囲が限定されるものではない。 Modes for carrying out the present invention will be described below with reference to the drawings. However, the embodiments described below are examples of the method for manufacturing the collet and the semiconductor device for embodying the technical idea of the present invention, and are not limited to the following. Further, the dimensions, materials, shapes, relative arrangements, and the like of the component parts described in the embodiments are not intended to limit the scope of the present invention thereto unless otherwise specified. The sizes and positional relationships of the members shown in the drawings may be exaggerated for clarity of explanation. In addition, a term indicating a specific direction or position (for example, “upper”, “lower”, “right”, “left” and another term including those terms) is used as necessary. The use of these terms is to facilitate the understanding of the invention with reference to the drawings, and the technical scope of the present invention is not limited by the meanings of these terms.

実施形態に係る半導体装置の製造方法は、主として以下の工程を備える。
１）半導体素子が収容されたカートリッジを準備する工程
２）基板を準備する工程
３）カートリッジの開口部から半導体素子を放出し、基板上に載置する工程 The method for manufacturing a semiconductor device according to the embodiment mainly includes the following steps.
1) Step of preparing a cartridge containing a semiconductor element 2) Step of preparing a substrate 3) Step of discharging the semiconductor element from the opening of the cartridge and placing it on the substrate

（半導体素子が収容されたカートリッジを準備する工程）
図１は、実施形態で用いられるカートリッジ１０を示す概略断面図である。カートリッジ１０は、本体２０と、本体２０の上側に設けられるキャップ３０と、本体２０の下側に設けられるストッパ４０と、を備える。 (Process of preparing a cartridge containing a semiconductor element)
FIG. 1 is a schematic cross-sectional view showing a cartridge 10 used in the embodiment. The cartridge 10 includes a main body 20, a cap 30 provided on the upper side of the main body 20, and a stopper 40 provided on the lower side of the main body 20.

本体２０は、縦に長い筒状の部材である。本体２０は、半導体素子を収容可能な収容部２１を備える。図１は、収容部２１に半導体素子５０を収容した状態を示している。収容部２１は、上側開口部２３と下側開口部２４とを備えている。本体２０は、例えば、アルミなどの金属や、プラスチックなどを用いることができる。 The main body 20 is a vertically long tubular member. The main body 20 includes an accommodating portion 21 that can accommodate a semiconductor element. FIG. 1 shows a state in which the semiconductor element 50 is housed in the housing portion 21. The housing portion 21 includes an upper opening 23 and a lower opening 24. For the main body 20, for example, a metal such as aluminum or a plastic can be used.

収容部２１は、図１に示すように、半導体素子５０を重ねて収容可能である。つまり、収容部２１の幅（内径）は、半導体素子の幅よりも広くなっている。例えば、収容部２１の幅は、半導体素子の幅の１０５％〜１３０％程度とすることができる。収容部２１の内周形状（水平方向の断面視形状）は、半導体素子の上面形状と相似形の内周形状とすることが好ましい。例えば、半導体素子５０の上面形状が、各辺が３５０μｍの正方形である場合、収容部２１は内周形状が、各辺が４００μｍの正方形とすることができる。 As shown in FIG. 1, the accommodating portion 21 can accommodate the semiconductor elements 50 in a stacked manner. That is, the width (inner diameter) of the housing portion 21 is wider than the width of the semiconductor element. For example, the width of the housing portion 21 can be about 105% to 130% of the width of the semiconductor element. The inner peripheral shape (horizontal cross-sectional shape) of the housing portion 21 is preferably an inner peripheral shape similar to the upper surface shape of the semiconductor element. For example, when the top surface shape of the semiconductor element 50 is a square having 350 μm on each side, the accommodation portion 21 can have an inner peripheral shape having a square having each side of 400 μm.

本体２０の内側面２２は、上側開口部２３から下側開口部２４まで、同じ幅であることが好ましい。また、内側面２２は、鏡面加工などの加工を施していてもよく、ＤＬＣなどのコーティング膜を備えていてもよい。 The inner side surface 22 of the body 20 preferably has the same width from the upper opening 23 to the lower opening 24. Further, the inner side surface 22 may be subjected to processing such as mirror finishing, and may be provided with a coating film such as DLC.

本体２０の長さは、特に限定されるものではない。例えば、上述の１辺が３５０μｍの半導体素子の高さが１２０μｍの場合、本体２０の長さは３０ｃｍ〜１００ｃｍ程度とすることができる。収容される半導体素子の厚みと、本体２０の長さによって収容可能な半導体素子の数が決められる。 The length of the main body 20 is not particularly limited. For example, when the height of the semiconductor element whose one side is 350 μm is 120 μm, the length of the main body 20 can be about 30 cm to 100 cm. The number of semiconductor elements that can be accommodated is determined by the thickness of the semiconductor elements accommodated and the length of the main body 20.

キャップ３０は、本体２０の上側にある上側開口部２３に配置される。キャップ３０は、エア供給口３１を備えている。エア供給口３１は、外部のエア供給源と接続されるエアチューブ３２を備えている。尚、エアチューブ３２は、エア供給部３１と一体又は別体として設けることができる。キャップ３０は、例えば、樹脂材料、金属材料、ゴム材料などから構成することができる。また、キャップ３０は本体２０と着脱可能なように取り付けることができる。キャップ３０を本体２０とは、例えばそれぞれにネジ加工を施して固定してもよい。あるいは、これらとは別の固定治具などを用いて固定させてもよい。ゴム材料を用いる場合は、本体２０の上側開口部２３及び外側面を覆うように固定するキャップ３０としてもよい。あるいは、本体２０の上側開口部２３内に挿入して固定する栓状のキャップ３０としてもよい。 The cap 30 is arranged in the upper opening 23 on the upper side of the main body 20. The cap 30 includes an air supply port 31. The air supply port 31 includes an air tube 32 connected to an external air supply source. The air tube 32 may be provided integrally with or separately from the air supply unit 31. The cap 30 can be made of, for example, a resin material, a metal material, a rubber material, or the like. Further, the cap 30 can be detachably attached to the main body 20. The cap 30 and the main body 20 may be fixed by, for example, threading each. Alternatively, it may be fixed using a fixing jig or the like other than these. When a rubber material is used, the cap 30 may be fixed so as to cover the upper opening 23 and the outer surface of the main body 20. Alternatively, a plug-like cap 30 may be inserted and fixed in the upper opening 23 of the main body 20.

ストッパ４０は、本体２０の下側にある下側開口部２４に配置される。ストッパ４０は、下側開口部２４を覆うように本体２０の下端に取り付けられる開閉可能な部材である。ストッパ４０は、エアが供給されない状態では、収容部２１内の半導体素子が落下しないようにするストッパ（落下防止部材）として機能する。 The stopper 40 is arranged in the lower opening 24 on the lower side of the main body 20. The stopper 40 is an openable/closable member attached to the lower end of the main body 20 so as to cover the lower opening 24. The stopper 40 functions as a stopper (falling prevention member) that prevents the semiconductor element in the housing portion 21 from falling when air is not supplied.

収容部２１内に収容される半導体素子５０は、例えば、図４Ａ、図４Ｂに示すような、半導体層を含む積層構造体５１と、電極５２と、を備える。積層構造体５１は上面視形状が正方形、長方形などの矩形のほか、六角形などの多角形とすることができる。半導体素子５０を収容部２１内に収容する場合、例えば、コレット等を用いて個片化された半導体素子５０を、同じ向きとなるようにして収容する。同じ向き、とは、上下方向の向き、及び横方向の向き、を指す。例えば、電極５２を上側にして基板上に載置したい場合は、電極５２を上側にして収容部２１内に収容する。また、ｐ電極及びｎ電極の配置が同じようになるように収容部２１内に収容する。 The semiconductor element 50 accommodated in the accommodating portion 21 includes, for example, a stacked structure 51 including a semiconductor layer and an electrode 52, as shown in FIGS. 4A and 4B. The laminated structure 51 may have a rectangular shape such as a square or a rectangle when viewed from above, and a polygon such as a hexagon. When the semiconductor element 50 is housed in the housing portion 21, for example, the semiconductor elements 50 that are individualized by using a collet or the like are housed in the same direction. The same direction means a vertical direction and a horizontal direction. For example, when it is desired to place the electrode 52 on the upper side on the substrate, the electrode 52 is placed on the upper side and accommodated in the accommodating portion 21. Further, the p-electrode and the n-electrode are housed in the housing part 21 so that they are arranged in the same manner.

（基板を準備する工程）
基板６０は、例えば、例えば、半導体装置の筐体となる基板や、製造工程内において仮実装されるシート等の仮置き用の基板を用いることができる。仮置き用の基板とは、最終的には半導体装置を構成しない基板であり、工程内のみで用いられる基板を指す。半導体装置の筐体となる基板としては、配線を備えたセラミックパッケージ、リードを一体成形した樹脂パッケージ等が挙げられる。また、仮置き用の基板としては、耐熱シート等が挙げられる。 (Process of preparing a substrate)
As the substrate 60, for example, a substrate that serves as a housing of a semiconductor device or a temporary placement substrate such as a sheet that is temporarily mounted in the manufacturing process can be used. The temporary placement substrate is a substrate that does not finally form a semiconductor device, and refers to a substrate used only in the process. Examples of the substrate that serves as the housing of the semiconductor device include a ceramic package including wiring, a resin package in which leads are integrally formed, and the like. A heat resistant sheet or the like may be used as a temporary substrate.

基板６０上の半導体素子５０を載置するには、あらかじめ接合部材７０を設けておくことが好ましい。接合部材７０としては、樹脂等が挙げられる。 In order to mount the semiconductor element 50 on the substrate 60, it is preferable to previously provide the joining member 70. Examples of the joining member 70 include resin.

（カートリッジの開口部から半導体素子を放出し、基板上に載置する工程）
半導体素子５０を収容したカートリッジ１０を、基板６０の所定の位置の上方に配置する。そして、エア供給口３１から本体２０の収容部２１内にエアを供給する。これにより、収容部２１内の半導体素子５０が上方から押圧されると共に、ストッパ４０が下方に開放する。これにより、半導体素子５０は収容部２１の下側開口部２４から下方に放出され、基板６０の上面に載置される。 (Process of discharging the semiconductor element from the opening of the cartridge and mounting it on the substrate)
The cartridge 10 accommodating the semiconductor element 50 is arranged above the predetermined position of the substrate 60. Then, air is supplied from the air supply port 31 into the accommodation portion 21 of the main body 20. As a result, the semiconductor element 50 in the housing portion 21 is pressed from above, and the stopper 40 is opened downward. As a result, the semiconductor element 50 is discharged downward from the lower opening 24 of the housing portion 21 and placed on the upper surface of the substrate 60.

ストッパ４０は、１又は複数の部材で構成される。例えば、図１〜図３に示すストッパ４０は、本体２０の下端の、右端と左端にそれぞれ１つ、合計２つの部材として構成される。押圧により、左右の部材のそれぞれ対向する側が下方に移動する。ここでは、ストッパ４０として弾性体であるゴムを用いた例を示している。このような弾性体のストッパ４０の場合は、押圧によりストッパ４０が変形されることで下方に開放される。 The stopper 40 is composed of one or more members. For example, the stopper 40 shown in FIGS. 1 to 3 is configured as a total of two members, one at each of the right end and the left end of the lower end of the main body 20. By pressing, the opposite sides of the left and right members move downward. Here, an example in which rubber, which is an elastic body, is used as the stopper 40 is shown. In the case of such an elastic stopper 40, the stopper 40 is deformed by pressing and is opened downward.

ストッパ４０は、１つの半導体素子５０を放出した後に、元の位置に戻ることで、基板６０の同じ位置に複数の半導体素子が載置されることを抑制することができる。エアの供給量は半導体素子の大きさや重さ等によって適宜調整することができる。 After the stopper 40 releases one semiconductor element 50 and then returns to the original position, it is possible to prevent a plurality of semiconductor elements from being placed at the same position on the substrate 60. The supply amount of air can be appropriately adjusted depending on the size and weight of the semiconductor element.

以上のようにして、基板６０上に半導体素子５０を、ダメージを少なくして載置することができる。 As described above, the semiconductor element 50 can be mounted on the substrate 60 with less damage.

（その他の工程）
上述のようにして、半導体素子５０を基板６０上に載置した後、種々の工程を備えることができる。例えば、半導体素子５０として発光素子を用い、半導体装置１００として図５に示すような構成を備えた発光装置を得る場合について説明する。 (Other processes)
As described above, after mounting the semiconductor element 50 on the substrate 60, various steps can be provided. For example, a case where a light emitting element is used as the semiconductor element 50 and a light emitting device having a configuration as shown in FIG. 5 is obtained as the semiconductor device 100 will be described.

基板６０として、樹脂パッケージ６０を準備し、その上に樹脂材料を含む接合部材７０を配置する。次に、その接合部材７０の上に、上述のカートリッジ１０を用いて半導体素子５０として発光素子５０を載置する工程を経る。次に、発光素子５０の電極５２と、樹脂パッケージ６０の電極とをワイヤ８０で接合する。次に、発光素子５０及びワイヤ８０を封止部材９０で被覆する。これにより半導体装置として発光装置１００を得ることができる。 A resin package 60 is prepared as the substrate 60, and a joining member 70 containing a resin material is arranged thereon. Next, the step of placing the light emitting element 50 as the semiconductor element 50 on the joining member 70 using the cartridge 10 described above is performed. Next, the electrode 52 of the light emitting element 50 and the electrode of the resin package 60 are joined by the wire 80. Next, the light emitting element 50 and the wire 80 are covered with the sealing member 90. Thus, the light emitting device 100 can be obtained as a semiconductor device.

本発明に係る半導体装置の製造方法は、半導体素子を基板等の上に載置する工程において適用することができる。 The method for manufacturing a semiconductor device according to the present invention can be applied in the step of mounting a semiconductor element on a substrate or the like.

１０…カートリッジ
２０…本体
２１…収容部
２２…内側面
２３…上側開口部
２４…下側開口部
３０…キャップ
３１…エア供給口
３２…エア供給チューブ
４０…ストッパ
５０…半導体素子
５１…積層構造体
５２…電極
６０…基板
７０…接合部材
８０…ワイヤ
９０…封止部材
１００…半導体装置 DESCRIPTION OF SYMBOLS 10... Cartridge 20... Main body 21... Storage part 22... Inner side surface 23... Upper side opening 24... Lower side opening 30... Cap 31... Air supply port 32... Air supply tube 40... Stopper 50... Semiconductor element 51... Laminated structure 52... Electrode 60... Substrate 70... Joining member 80... Wire 90... Sealing member 100... Semiconductor device

Claims (6)

半導体素子が重ねて収容された収容部を備えた本体と、前記収容部の上側開口部に備えられ、エア供給口を備えたキャップと、前記収容部の下側開口部に備えられるストッパと、を備えた半導体素子収容済のカートリッジを準備する工程と、
基板を準備する工程と、
前記基板の上方に前記カートリッジを配置した後、前記エア供給口から前記収容部内にエアを供給し、前記半導体素子を前記下側開口部から放出し、前記基板の上面に前記半導体素子を載置する工程と、
を備える半導体装置の製造方法。 A main body having a housing portion in which semiconductor elements are stacked and housed, a cap provided at an upper opening of the housing portion and having an air supply port, and a stopper provided at a lower opening of the housing portion, A step of preparing a semiconductor element-containing cartridge having
A step of preparing a substrate,
After arranging the cartridge above the substrate, air is supplied into the accommodation portion from the air supply port, the semiconductor element is discharged from the lower opening, and the semiconductor element is mounted on the upper surface of the substrate. And the process of
A method for manufacturing a semiconductor device, comprising: 前記収容部の幅は、前記半導体素子の幅の１０５％〜１３０％程度である請求項１記載の半導体装置の製造方法。 The method of manufacturing a semiconductor device according to claim 1, wherein the width of the accommodation portion is about 105% to 130% of the width of the semiconductor element. 前記収容部の内側面は、鏡面加工された面である請求項１又は請求項２記載の半導体装置の製造方法。 The method of manufacturing a semiconductor device according to claim 1, wherein the inner surface of the housing portion is a mirror-finished surface. 前記収容部の内側面は、コーティング膜を備えている請求項１又は請求項２記載の半導体装置の製造方法。 The method of manufacturing a semiconductor device according to claim 1, wherein an inner surface of the housing portion is provided with a coating film. 前記ストッパは、弾性体である請求項１〜請求項４のいずれか１項に記載の半導体装置の製造方法。 The method for manufacturing a semiconductor device according to claim 1, wherein the stopper is an elastic body. 前記半導体素子は、発光素子である請求項１〜請求項５のいずれか１項に記載の半導体装置の製造方法。 The method for manufacturing a semiconductor device according to claim 1, wherein the semiconductor element is a light emitting element.
JP2016247972A 2016-12-21 2016-12-21 Method for manufacturing semiconductor device Active JP6747280B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2016247972A JP6747280B2 (en) 2016-12-21 2016-12-21 Method for manufacturing semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2016247972A JP6747280B2 (en) 2016-12-21 2016-12-21 Method for manufacturing semiconductor device

Publications (2)

Publication Number Publication Date
JP2018101730A JP2018101730A (en) 2018-06-28
JP6747280B2 true JP6747280B2 (en) 2020-08-26

Family

ID=62714481

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2016247972A Active JP6747280B2 (en) 2016-12-21 2016-12-21 Method for manufacturing semiconductor device

Country Status (1)

Country Link
JP (1) JP6747280B2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102141203B1 (en) * 2019-02-11 2020-08-04 세메스 주식회사 Bonding head and apparatus for bonding chips having the same

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55165832A (en) * 1979-06-13 1980-12-24 Sanyo Electric Co Ltd Delivery method of small-sized parts
JPS57183043A (en) * 1981-05-07 1982-11-11 Nec Home Electronics Ltd Mounting of semiconductor pellet
JPS58187000A (en) * 1982-04-26 1983-11-01 松下電器産業株式会社 Method of mounting rectangular electronic part
JPH0348226U (en) * 1989-09-13 1991-05-08
JP2891230B2 (en) * 1997-03-28 1999-05-17 日本電気株式会社 Electronic component storage pack
JPH10284881A (en) * 1997-04-08 1998-10-23 Matsushita Electric Ind Co Ltd Electronic parts mounter
JP3912637B2 (en) * 1998-04-27 2007-05-09 ソニー株式会社 Parts carrier
JP4172069B2 (en) * 1998-08-18 2008-10-29 ソニー株式会社 Magazine case for chip parts

Also Published As

Publication number Publication date
JP2018101730A (en) 2018-06-28

Similar Documents

Publication Publication Date Title
JP6491120B2 (en) Resin sealing device, resin sealing method, and resin molded product manufacturing method
WO2017156510A1 (en) Method for applying phosphor to light emitting diodes and apparatus thereof
JP2009044008A (en) Protective tape peeling method and device for wafer
TWI710100B (en) Reduced-height memory system and method for fabricating dynamic random access memory module
KR102101760B1 (en) Apparatus for manufacturing semiconductor, method of manufacturing semiconductor device and collet
JP6747280B2 (en) Method for manufacturing semiconductor device
KR20180124962A (en) Peeling device
US10833235B2 (en) Light source, method of manufacturing the light source, and method of mounting the light source
JP2010021261A (en) Method of manufacturing optical semiconductor device, optical semiconductor device, and method of manufacturing optical semiconductor apparatus
US20150115016A1 (en) Ball mount module
JP5679735B2 (en) Package board handling method
JP2008010814A (en) Substrate to be applied to ultra-thin led package, and its packaging method
CN109314062B (en) Method for mounting tube core
US20160254427A1 (en) Optoelectronic Component and Method for Securing Same
JP3933560B2 (en) Ball mounting apparatus and ball mounting method
WO2006066211A3 (en) Active and passive semiconductor device package
KR200460715Y1 (en) Semiconductor chip pick-up apparatus
TW201419466A (en) Method of forming semiconductor package
JP7091112B2 (en) Chip component placement jig and chip component placement method
JP2006273335A (en) Component supplying tray
KR20160081289A (en) Boat for semiconductor package fabrication and method for fabricating the semiconductor package
KR101902365B1 (en) Light emitting device and manufacturing method thereof
JP7177328B2 (en) light emitting device
JP2018148151A (en) Processing method and cutting device of package substrate
JP4234958B2 (en) Carrier tape

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20190808

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20200529

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20200707

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20200720

R150 Certificate of patent or registration of utility model

Ref document number: 6747280

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250