JP6725671B2 - 拡張されたシステム性能のための適応可能な値範囲のプロファイリング - Google Patents
拡張されたシステム性能のための適応可能な値範囲のプロファイリング Download PDFInfo
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- 230000003044 adaptive effect Effects 0.000 title description 10
- 238000000034 method Methods 0.000 claims description 53
- 238000013519 translation Methods 0.000 claims description 34
- 238000012545 processing Methods 0.000 claims description 20
- 238000013507 mapping Methods 0.000 claims description 19
- 238000006243 chemical reaction Methods 0.000 claims description 10
- 230000004044 response Effects 0.000 claims description 6
- 230000006978 adaptation Effects 0.000 claims 1
- 238000004581 coalescence Methods 0.000 claims 1
- 230000014616 translation Effects 0.000 description 33
- 239000000872 buffer Substances 0.000 description 23
- 238000010586 diagram Methods 0.000 description 9
- 239000000523 sample Substances 0.000 description 9
- 238000004364 calculation method Methods 0.000 description 4
- 230000007246 mechanism Effects 0.000 description 4
- 238000013461 design Methods 0.000 description 3
- 230000006399 behavior Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 238000004891 communication Methods 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 230000001627 detrimental effect Effects 0.000 description 1
- 230000007334 memory performance Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 230000000737 periodic effect Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 238000004088 simulation Methods 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
- 230000009466 transformation Effects 0.000 description 1
- 238000000844 transformation Methods 0.000 description 1
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-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
- G06F12/0815—Cache consistency protocols
- G06F12/0831—Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means
- G06F12/0833—Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means in combination with broadcast means (e.g. for invalidation or updating)
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
- G06F12/023—Free address space management
- G06F12/0238—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
- G06F12/0246—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory in block erasable memory, e.g. flash memory
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
- G06F12/0638—Combination of memories, e.g. ROM and RAM such as to permit replacement or supplementing of words in one module by words in another module
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
- G06F12/0811—Multiuser, multiprocessor or multiprocessing cache systems with multilevel cache hierarchies
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/10—Address translation
- G06F12/1009—Address translation using page tables, e.g. page table structures
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/10—Address translation
- G06F12/1027—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/12—Replacement control
- G06F12/121—Replacement control using replacement algorithms
- G06F12/122—Replacement control using replacement algorithms of the least frequently used [LFU] type, e.g. with individual count value
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/12—Replacement control
- G06F12/121—Replacement control using replacement algorithms
- G06F12/128—Replacement control using replacement algorithms adapted to multidimensional cache systems, e.g. set-associative, multicache, multiset or multilevel
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
- G06F3/061—Improving I/O performance
- G06F3/0611—Improving I/O performance in relation to response time
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0646—Horizontal data movement in storage systems, i.e. moving data in between storage devices or systems
- G06F3/0647—Migration mechanisms
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0653—Monitoring storage devices or systems
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
- G06F3/0671—In-line storage system
- G06F3/0683—Plurality of storage devices
- G06F3/0685—Hybrid storage combining heterogeneous device types, e.g. hierarchical storage, hybrid arrays
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/12—Replacement control
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/10—Providing a specific technical effect
- G06F2212/1016—Performance improvement
- G06F2212/1024—Latency reduction
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/10—Providing a specific technical effect
- G06F2212/1041—Resource optimization
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/62—Details of cache specific to multiprocessor cache arrangements
- G06F2212/621—Coherency control relating to peripheral accessing, e.g. from DMA or I/O device
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/65—Details of virtual memory and virtual address translation
- G06F2212/651—Multi-level translation tables
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/70—Details relating to dynamic memory management
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/72—Details relating to flash memory management
- G06F2212/7202—Allocation control and policies
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Description
Claims (13)
- メモリ要求のストリーム内のメモリアドレスの連続する範囲のセット及び対応するアクセス頻度を識別するために、処理システムにおいてメモリ要求のストリーム内のメモリアドレスの範囲を適応的にプロファイリングすることであって、前記適応的にプロファイリングすることは、マージ閾値及びスプリット閾値に基づいており、連続する範囲のセットは、メモリアドレスの範囲空間全体に及び、前記マージ閾値は、前記メモリアドレスの連続する範囲のセット内の前記メモリアドレスの範囲毎の最小アクセス頻度を示しており、前記スプリット閾値は、前記メモリアドレスの連続する範囲のセット内の前記メモリアドレスの範囲毎の最大アクセス頻度を示している、ことと、
所定の閾値アクセス頻度を上回る対応するアクセス頻度を有する前記メモリアドレスの範囲のターゲットセットを識別するために、前記メモリアドレスの連続する範囲のセット及び対応するアクセス頻度を周期的にトラバースすることであって、前記メモリアドレスの範囲のターゲットセットは、所定数の範囲以下の範囲の総数を有しており、前記メモリアドレスの範囲のターゲットセットの範囲は、前記メモリアドレスの範囲空間全体の少なくとも一部に及ぶ、ことと、
前記メモリアドレスの範囲のターゲットセット内の前記メモリアドレスの範囲を使用して第1動作を実行することと、を含み、
前記メモリアドレスは仮想メモリアドレスであって、
前記第1動作は、
前記メモリアドレスの範囲のターゲットセットを、ベースアドレス値及びリミット値に基づいて決定された物理アドレス範囲のセットに仮想−物理メモリアドレス変換することと、
物理アドレス範囲のセットを、対応するベースアドレス値及びリミット値のペアとして、ベースリミットレジスタのセットに記憶することであって、前記所定数の範囲は、ベースリミットレジスタのセット内のベースリミットレジスタの総数に対応している、ことと、を含む、
方法。 - 前記メモリアドレスの範囲のターゲットセットは、前記メモリアドレスの範囲空間全体より狭い、
請求項1の方法。 - 前記メモリアドレスの範囲のターゲットセットは、前記メモリアドレスの非連続範囲を含む、
請求項1又は2の方法。 - 前記第1動作は、
前記メモリアドレスの範囲のターゲットセットの連続する範囲を、メモリの大きなページのアドレス範囲に変換することをさらに含む、
請求項1又は2の方法。 - 前記第1動作は、
前記メモリアドレスのターゲット範囲に関連するメインメモリの内容を、マルチレベルのメモリシステム内の高帯域メモリに割り当てることをさらに含む、
請求項1又は2の方法。 - 前記第1動作を実行することは、
複数のリクエスタによるメモリアドレスへの複数のメモリ要求を識別することと、
複数の要求に応じてコヒーレンス動作を実行することと、を含む、
請求項1の方法。 - 前記コヒーレンス動作を実行することは、メモリアドレスに対応するキャッシュラインを無効にすることを含む、
請求項6の方法。 - メモリ要求のストリーム内のメモリアドレスの連続する範囲のセット及び対応するアクセス頻度を識別するために、処理システムにおいてメモリ要求のストリーム内のメモリアドレスの範囲を適応的にプロファイリングするように構成された適応範囲プロファイラであって、前記適応的にプロファイリングすることは、マージ閾値及びスプリット閾値に基づいており、連続する範囲のセットは、メモリアドレスの範囲空間全体に及び、前記マージ閾値は、前記メモリアドレスの連続する範囲のセット内の前記メモリアドレスの範囲毎の最小アクセス頻度を示しており、前記スプリット閾値は、前記メモリアドレスの連続する範囲のセット内の前記メモリアドレスの範囲毎の最大アクセス頻度を示している、適応範囲プロファイラと、
所定の閾値アクセス頻度を上回る対応するアクセス頻度を有する前記メモリアドレスの範囲のターゲットセットを識別するために、前記メモリアドレスの連続する範囲のセット及び対応するアクセス頻度を周期的にトラバースするように構成された範囲合体及びカリングロジックであって、前記メモリアドレスの範囲のターゲットセットは、所定数の範囲以下の範囲の総数を有しており、前記メモリアドレスの範囲のターゲットセットの範囲は、前記メモリアドレスの範囲空間全体の少なくとも一部に及ぶ、範囲合体及びカリングロジックと、
前記メモリアドレスの範囲のターゲットセット内の前記メモリアドレスの範囲を使用して第1動作を実行するように構成されたロジックと、を備え、
前記ロジックは、
前記メモリアドレスの範囲のターゲットセットを、ベースアドレス値及びリミット値を有する物理アドレスのセットに変換することを含む第1動作を実行するように構成された仮想−物理アドレストランスレータと、
物理アドレスの範囲のセットを記憶するように構成されたベースリミットレジスタのセットであって、前記所定数の範囲は、ベースリミットレジスタのセット内のベースリミットレジスタの総数に対応している、ベースリミットレジスタのセットと、を備える、
装置。 - 前記メモリアドレスの範囲のターゲットセットは、前記メモリアドレスの範囲空間全体より狭く、前記メモリアドレスの非連続範囲を含む、
請求項8の装置。 - ベースリミットレジスタのセットのメモリマッピングに対して冗長なメモリマッピングを含むページテーブルを備える、
請求項8の装置。 - 前記第1動作は、
前記メモリアドレスの範囲のターゲットセットの連続する範囲を、メモリの大きなページのアドレス範囲に変換することをさらに含む、
請求項8、9又は10の装置。 - 高帯域メモリを備え、
前記第1動作は、
前記メモリアドレスのターゲット範囲に関連するメインメモリの内容を前記高帯域メモリに割り当てることをさらに含む、
請求項8、9又は10の装置。 - 前記ロジックは、複数のリクエスタによるメモリアドレスへの複数のメモリ要求を識別し、複数の要求に応じてコヒーレンス動作を実行するように構成されている、
請求項8、9又は10の装置。
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US201662286618P | 2016-01-25 | 2016-01-25 | |
US62/286,618 | 2016-01-25 | ||
US15/130,793 | 2016-04-15 | ||
US15/130,793 US10019365B2 (en) | 2016-01-25 | 2016-04-15 | Adaptive value range profiling for enhanced system performance |
PCT/US2017/013934 WO2017132026A1 (en) | 2016-01-25 | 2017-01-18 | Adaptive value range profiling for enhanced system performance |
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-
2016
- 2016-04-11 US US15/095,778 patent/US10387315B2/en active Active
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- 2017-01-18 CN CN201780008128.4A patent/CN108496160B/zh active Active
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- 2017-01-18 KR KR1020187021915A patent/KR102165776B1/ko active IP Right Grant
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Publication number | Publication date |
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KR102165776B1 (ko) | 2020-10-14 |
US10019365B2 (en) | 2018-07-10 |
US20170212837A1 (en) | 2017-07-27 |
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EP3408748A4 (en) | 2019-08-21 |
EP3408748A1 (en) | 2018-12-05 |
KR20180099819A (ko) | 2018-09-05 |
US20170212845A1 (en) | 2017-07-27 |
US10387315B2 (en) | 2019-08-20 |
WO2017132026A1 (en) | 2017-08-03 |
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