JP6615902B2 - ニューラルネットワークプロセッサにおけるベクトル計算ユニット - Google Patents
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Description
本明細書は、ハードウェアにおいてニューラルネットワーク推測値を計算することに関する。
全体として、本明細書では、ニューラルネットワーク推測値を計算する特定目的ハードウェア回路について説明する。
本明細書の主題の1つ以上の実施形態の詳細が添付の図面および以下の説明に記載されている。主題の他の特徴、局面および利点は、説明、図面および特許請求の範囲から明らかになるであろう。
詳細な説明
複数の層を有するニューラルネットワークは、推測値の計算に使用することができる。たとえば、入力を前提として、ニューラルネットワークは当該入力について推測値を計算することができる。ニューラルネットワークは、ニューラルネットワークの各層を介して入力を処理することによってこの推測値を計算する。特に、ニューラルネットワークの層は、各々が重みのそれぞれのセットを有する状態で、ある順序で配置される。各層は、入力を受け取って、当該層の重みのセットに従って入力を処理して、出力を生成する。
Claims (11)
- 複数の層を備えるニューラルネットワークについてニューラルネットワーク計算を実行するための回路であって、
累積値のベクトルを受け取るように構成され、関数を各々の累積値に適用して活性化値のベクトルを生成するように構成された活性化回路と、
前記活性化回路に結合され、各々の活性化値についてそれぞれの正規化値を生成するように構成された正規化回路とを備え、
前記正規化回路は、複数の正規化レジスタ列を備え、各々の正規化レジスタ列は、複数の正規化レジスタを備え、各々の正規化レジスタ列は、それぞれの活性化値を受け取るように構成され、前記正規化回路は、複数のグループを形成するように構成され、各々のグループは、1つ以上の正規化レジスタを含み、かつ、正規化ユニットに対応し、各々の正規化ユニットは、前記それぞれの活性化値についてそれぞれの正規化値を算出するように構成される、回路。 - 前記活性化回路は、前記回路内のシストリックアレイから前記累積値のベクトルを受け取る、請求項1に記載の回路。
- 各々の正規化レジスタは、前記個別の活性化値を隣接する正規化レジスタに渡すように構成される、請求項1または2に記載の回路。
- 各々のグループに含まれる正規化レジスタの数は、正規化半径パラメータに基づいて決定される、請求項1〜3のいずれか1項に記載の回路。
- 各々の正規化ユニットは、
前記それぞれの活性化値を受け取るように構成され、
前記それぞれの活性化値からそれぞれの中間正規化値を生成するように構成され、
前記それぞれの中間正規化値を1つ以上の隣接する正規化ユニットに送るように構成される、請求項1〜4のいずれか1項に記載の回路。 - 前記それぞれの中間正規化値を生成することは、前記それぞれの活性化値の二乗を生成することを備える、請求項5に記載の回路。
- 各々の正規化ユニットはさらに、
活性化値から生成された1つ以上の中間正規化値を1つ以上の隣接する正規化ユニットから受け取るように構成され、
各々の中間正規化値を合計して、インデックスを生成するように構成され、
前記インデックスを使用して、ルックアップテーブルから1つ以上の値にアクセスするように構成され、
前記1つ以上の値および前記インデックスからスケーリングファクタを生成するように構成され、
前記スケーリングファクタおよび前記それぞれの活性化値から前記それぞれの正規化値を生成するように構成される、請求項5または6に記載の回路。 - 前記正規化値を受け取るように構成され、前記正規化値をプールしてプール値を生成するように構成されたプール回路をさらに備える、請求項1〜7のいずれか1項に記載の回路。
- 前記プール回路は、前記複数の正規化値を複数のレジスタおよび複数のメモリユニットに格納するように構成され、
前記複数のレジスタおよび前記複数のメモリユニットは、直列に接続され、各々のレジスタは、1つの正規化値を格納し、各々のメモリユニットは、複数の正規化値を格納し、
前記プール回路は、全てのクロックサイクルの後に、所与の正規化値を後続のレジスタまたはメモリユニットにシフトするように構成され、
前記プール回路は、前記正規化値から前記プール値を生成するように構成される、請求項8に記載の回路。 - 前記活性化値を受け取るように構成され、前記活性化値をプールしてプール値を生成するように構成されたプール回路をさらに備える、請求項1〜7のいずれか1項に記載の回路。
- 前記プール回路は、前記複数の活性化値を複数のレジスタおよび複数のメモリユニットに格納するように構成され、
前記複数のレジスタおよび前記複数のメモリユニットは、直列に接続され、各々のレジスタは、1つの正規化値を格納し、各々のメモリユニットは、複数の活性化値を格納し、
前記プール回路は、全てのクロックサイクルの後に、所与の活性化値を後続のレジスタまたはメモリユニットにシフトするように構成され、
前記プール回路は、前記活性化値から前記プール値を生成するように構成される、請求項10に記載の回路。
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