JP6614116B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
- Publication number
- JP6614116B2 JP6614116B2 JP2016237723A JP2016237723A JP6614116B2 JP 6614116 B2 JP6614116 B2 JP 6614116B2 JP 2016237723 A JP2016237723 A JP 2016237723A JP 2016237723 A JP2016237723 A JP 2016237723A JP 6614116 B2 JP6614116 B2 JP 6614116B2
- Authority
- JP
- Japan
- Prior art keywords
- electrode
- layer
- gate
- semiconductor
- source
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 239000004065 semiconductor Substances 0.000 title claims description 97
- 239000010410 layer Substances 0.000 claims description 219
- 239000000758 substrate Substances 0.000 claims description 15
- 239000011229 interlayer Substances 0.000 claims description 6
- 239000012535 impurity Substances 0.000 claims description 5
- 239000004020 conductor Substances 0.000 claims description 4
- 229910002601 GaN Inorganic materials 0.000 description 141
- 229910002704 AlGaN Inorganic materials 0.000 description 30
- 230000005684 electric field Effects 0.000 description 26
- 230000003071 parasitic effect Effects 0.000 description 11
- 230000015556 catabolic process Effects 0.000 description 10
- 230000000694 effects Effects 0.000 description 7
- 230000001965 increasing effect Effects 0.000 description 7
- 238000004088 simulation Methods 0.000 description 7
- 239000003990 capacitor Substances 0.000 description 6
- 230000007423 decrease Effects 0.000 description 6
- 239000000463 material Substances 0.000 description 5
- 239000013078 crystal Substances 0.000 description 4
- 229910052751 metal Inorganic materials 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- 230000004048 modification Effects 0.000 description 4
- 238000012986 modification Methods 0.000 description 4
- 230000010287 polarization Effects 0.000 description 4
- 239000000969 carrier Substances 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 230000001939 inductive effect Effects 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 238000004364 calculation method Methods 0.000 description 2
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 2
- 239000002344 surface layer Substances 0.000 description 2
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- RNQKDQAVIXDKAG-UHFFFAOYSA-N aluminum gallium Chemical compound [Al].[Ga] RNQKDQAVIXDKAG-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000003111 delayed effect Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000006073 displacement reaction Methods 0.000 description 1
- 239000007772 electrode material Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 230000007935 neutral effect Effects 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 229910052594 sapphire Inorganic materials 0.000 description 1
- 239000010980 sapphire Substances 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 230000002269 spontaneous effect Effects 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
- H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
- H01L29/201—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds including two or more compounds, e.g. alloys
- H01L29/205—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds including two or more compounds, e.g. alloys in different semiconductor regions, e.g. heterojunctions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66484—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with multiple gate, at least one gate being an insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7831—Field effect transistors with field effect produced by an insulated gate with multiple gate structure
- H01L29/7832—Field effect transistors with field effect produced by an insulated gate with multiple gate structure the structure comprising a MOS gate and at least one non-MOS gate, e.g. JFET or MESFET gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
- H01L29/808—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier with a PN junction gate, e.g. PN homojunction gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16238—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area protruding from the surface of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
- H01L29/2003—Nitride compounds
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41758—Source or drain electrodes for field effect devices for lateral devices with structured layout for source or drain region, i.e. the source or drain region having cellular, interdigitated or ring structure or being curved or angular
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Junction Field-Effect Transistors (AREA)
Description
第1実施形態にかかる半導体装置について、図1〜図8を参照して説明する。なお、図1は、本実施形態にかかる半導体装置に備えられる素子の1セル分を示した断面図であるが、このセルが複数備えられることで半導体装置が構成されている。
第2実施形態について説明する。本実施形態は、第1実施形態に対してゲート構造部を変更したものであり、その他については第1実施形態と同様であるため、第1実施形態と異なる部分についてのみ説明する。
第3実施形態について説明する。本実施形態は、第1実施形態に対してパッドレイアウトを変更したものであり、その他については第1実施形態と同様であるため、第1実施形態と異なる部分についてのみ説明する。
第4実施形態について説明する。本実施形態は、第3実施形態に対してパッドレイアウトを変更したものであり、その他については第3実施形態と同様であるため、第1実施形態と異なる部分についてのみ説明する。
第5実施形態について説明する。本実施形態は、第1実施形態に対してu−GaN層4のレイアウトを変更したものであり、その他については第1実施形態と同様であるため、第1実施形態と異なる部分についてのみ説明する。
第6実施形態について説明する。本実施形態は、第1〜第5実施形態に対してJG−S間抵抗値を規定したものであり、その他については第1〜第5実施形態と同様であるため、第1〜第5実施形態と異なる部分についてのみ説明する。なお、ここでは第1実施形態の構成の半導体装置を例に挙げて説明するが、第2〜第5実施形態の構成の半導体装置についても同様のことが言える。
Rjgs=Ru+Rp+Rpjg+Rm
そして、第1〜第5実施形態のように、JG電極11をソース電極8と連結した構造としており、これらが抵抗値の小さな金属で構成されていることから、電極抵抗Rmについては無視できる程度に小さい。したがって、数式1を簡略化すると、数式2のように表される。
Rjgs=Ru+Rp+Rpjg
また、ターンオフ時には、u−GaN層4やp−GaN層10に縦方向、つまり基板1の法線方向に電流が流れる。そして、p−GaN層10については厚みが例えば100nm以下と薄い上にMgなどの不純物密度が大きくなることから、p−GaN層10の内部抵抗Rpがp−GaN層10とJG電極11との接触抵抗Rpjgよりも十分に小さくなる。さらに、u−GaN層4については、厚みが薄いことに加えて、p−GaN層10と接しているためにp−GaN層10からのホールの拡散によって抵抗値が下がる。このため、u−GaN層4の内部抵抗Rpも、p−GaN層10とJG電極11との接触抵抗Rpjgよりも十分に小さくなる。したがって、数式2を更に簡略化すると、数式3のように表される。
Rjgs≒Rpjg
このため、JG−S間抵抗値は、基本的には数式1によって表される抵抗値のことを意味しているが、簡略化すると、数式3のようにp−GaN層10とJG電極11との接触抵抗Rpjgとして表される。
本発明は上記した実施形態に限定されるものではなく、特許請求の範囲に記載した範囲内において適宜変更が可能である。
3 AlGaN層
4 u−GaN層
7 MOSゲート電極
8 ソース電極
9 ドレイン電極
10 p−GaN層
11 JG電極
12 層間絶縁膜
13 電極層
Claims (8)
- 横型のスイッチングデバイスを有する半導体装置であって、
導電性材料で構成された基板上に形成され、ドリフト領域を構成する第1のGaN系半導体にて構成された第1半導体層(2)および前記第1のGaN系半導体よりもバンドギャップエネルギーが大きい第2のGaN系半導体にて構成された第2半導体層(3)にて構成されるヘテロジャンクション構造を有し、前記第2半導体層にリセス部(5)が形成されたチャネル形成層(2、3)と、
前記リセス部内に形成されたゲート絶縁膜(6)および該ゲート絶縁膜の上に形成されたMOS構造のゲート電極となるMOSゲート電極(7)を有するゲート構造部と、
前記第2半導体層の上において、前記ゲート構造部を挟んだ両側に配置されたソース電極(8)およびドレイン電極(9)と、
前記第2半導体層の上において、前記ゲート構造部と前記ドレイン電極との間における前記ドレイン電極から離れた位置に配置され、不純物がドープされていない第3のGaN系半導体にて構成された第3半導体層(4)と、
前記第3半導体層の上に形成されたp型の第4のGaN系半導体によって構成された第4半導体層(10)と、
前記第4半導体層に接触させられたジャンクションゲート電極(11)と、を備えるスイッチングデバイスを有し、
前記ソース電極と前記ジャンクションゲート電極は、前記MOSゲート電極を覆う層間絶縁膜(12)の上に形成される電極層(13)を介して連結されており、
前記第4半導体層における前記ドレイン電極側の端部に対して前記第3半導体層における前記ドレイン電極側の端部が前記ドレイン電極側へ突き出している距離(X)が1μm以上かつ5μm以下とされている半導体装置。 - 前記スイッチングデバイスが形成された領域をアクティブ領域(14)として、
前記電極層は、少なくとも前記アクティブ領域に形成されており、前記アクティブ領域において前記ソース電極と前記ジャンクションゲート電極とが前記電極層を介して連結されている請求項1に記載の半導体装置。 - 前記MOSゲート電極は、一方向を長手方向として延設されており、
前記電極層は、前記アクティブ領域内において前記MOSゲート電極の延設方向に沿って複数に分けて梯子状に配置され、
複数に分けて梯子状に配置された前記電極層の間において前記MOSゲート電極がゲートパッド(17)に接続されている請求項2に記載の半導体装置。 - 前記第3半導体層は、前記ゲート構造部に接しており、前記ゲート構造部よりも前記ドレイン電極側に配置されているのに加えて前記ソース電極側にも配置されている請求項1ないし3のいずれか1つに記載の半導体装置。
- 前記スイッチングデバイスのターンオフ時に、前記ジャンクションゲート電極および前記ソース電極を通じて流れる電流経路の抵抗成分による抵抗値をジャンクションゲート−ソース間抵抗値として、
前記ジャンクションゲート−ソース間抵抗値が200Ωmm以下とされている請求項1ないし4のいずれか1つに記載の半導体装置。 - 前記スイッチングデバイスのターンオフ時に、前記ジャンクションゲート電極および前記ソース電極を通じて流れる電流経路の抵抗成分による抵抗値をジャンクションゲート−ソース間抵抗値として、
前記ジャンクションゲート−ソース間抵抗値が100Ωmm以下とされている請求項1ないし4のいずれか1つに記載の半導体装置。 - 前記ジャンクションゲート−ソース間抵抗値は、前記第3半導体層の内部抵抗と、前記第4半導体層の内部抵抗と、前記第4半導体層と前記ジャンクションゲート電極との接触抵抗と、前記ジャンクションゲート電極から前記ソース電極に至る間の電極抵抗の合計抵抗値である請求項5または6に記載の半導体装置。
- 前記第4半導体層と前記ジャンクションゲート電極との接触抵抗が100Ωmm以下とされている請求項1ないし4のいずれか1つに記載の半導体装置。
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US16/092,492 US10629716B2 (en) | 2016-05-24 | 2017-04-06 | Semiconductor device including switching device having four-terminal structure |
CN201780031618.6A CN109155255B (zh) | 2016-05-24 | 2017-04-06 | 半导体装置 |
PCT/JP2017/014410 WO2017203849A1 (ja) | 2016-05-24 | 2017-04-06 | 半導体装置 |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2016103352 | 2016-05-24 | ||
JP2016103352 | 2016-05-24 |
Publications (3)
Publication Number | Publication Date |
---|---|
JP2017212425A JP2017212425A (ja) | 2017-11-30 |
JP2017212425A5 JP2017212425A5 (ja) | 2018-09-06 |
JP6614116B2 true JP6614116B2 (ja) | 2019-12-04 |
Family
ID=60476353
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2016237723A Active JP6614116B2 (ja) | 2016-05-24 | 2016-12-07 | 半導体装置 |
Country Status (3)
Country | Link |
---|---|
US (1) | US10629716B2 (ja) |
JP (1) | JP6614116B2 (ja) |
CN (1) | CN109155255B (ja) |
Families Citing this family (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2018230136A1 (ja) * | 2017-06-13 | 2018-12-20 | パナソニックIpマネジメント株式会社 | 窒化物半導体装置及びその製造方法 |
JP6769400B2 (ja) | 2017-06-26 | 2020-10-14 | 株式会社デンソー | 半導体装置 |
CN109728079A (zh) * | 2018-12-04 | 2019-05-07 | 北京大学深圳研究生院 | 一种晶体管及其制作方法 |
US11476359B2 (en) * | 2019-03-18 | 2022-10-18 | Wolfspeed, Inc. | Structures for reducing electron concentration and process for reducing electron concentration |
CN110634943B (zh) * | 2019-10-15 | 2021-01-01 | 南京大学 | 利用MBE再生长的横向结构GaN基JFET器件及其制备方法 |
JP6679036B1 (ja) * | 2019-11-29 | 2020-04-15 | 株式会社パウデック | ダイオード、ダイオードの製造方法および電気機器 |
US11380677B2 (en) * | 2020-04-28 | 2022-07-05 | Globalfoundries Singapore Pte. Ltd. | Transistor devices and methods of forming a transistor device |
JP6941904B1 (ja) * | 2021-03-11 | 2021-09-29 | 株式会社パウデック | ノーマリーオフ型分極超接合GaN系電界効果トランジスタおよび電気機器 |
WO2023136121A1 (ja) * | 2022-01-13 | 2023-07-20 | 住友電気工業株式会社 | 半導体装置 |
Family Cites Families (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2007150282A (ja) | 2005-11-02 | 2007-06-14 | Sharp Corp | 電界効果トランジスタ |
JP4712683B2 (ja) * | 2006-12-21 | 2011-06-29 | パナソニック株式会社 | トランジスタおよびその製造方法 |
KR101774933B1 (ko) * | 2010-03-02 | 2017-09-06 | 삼성전자 주식회사 | 듀얼 디플리션을 나타내는 고 전자 이동도 트랜지스터 및 그 제조방법 |
JP5666157B2 (ja) * | 2010-03-26 | 2015-02-12 | パナソニック株式会社 | 双方向スイッチ素子及びそれを用いた双方向スイッチ回路 |
JP5548909B2 (ja) * | 2010-04-23 | 2014-07-16 | 古河電気工業株式会社 | 窒化物系半導体装置 |
GB2482308A (en) | 2010-07-28 | 2012-02-01 | Univ Sheffield | Super junction silicon devices |
US8896131B2 (en) * | 2011-02-03 | 2014-11-25 | Alpha And Omega Semiconductor Incorporated | Cascode scheme for improved device switching behavior |
CN103314438A (zh) * | 2011-04-22 | 2013-09-18 | 先进动力设备技术研究协会 | 氮化物系半导体装置 |
JP2013074070A (ja) * | 2011-09-27 | 2013-04-22 | Fujitsu Ltd | 半導体装置及び半導体装置の製造方法 |
JP5669119B1 (ja) * | 2014-04-18 | 2015-02-12 | 株式会社パウデック | 半導体素子、電気機器、双方向電界効果トランジスタおよび実装構造体 |
JP2016021530A (ja) * | 2014-07-15 | 2016-02-04 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
JP5828435B1 (ja) * | 2015-02-03 | 2015-12-09 | 株式会社パウデック | 半導体素子、電気機器、双方向電界効果トランジスタおよび実装構造体 |
JP6701767B2 (ja) | 2015-09-22 | 2020-05-27 | 株式会社デンソー | 半導体装置 |
-
2016
- 2016-12-07 JP JP2016237723A patent/JP6614116B2/ja active Active
-
2017
- 2017-04-06 CN CN201780031618.6A patent/CN109155255B/zh active Active
- 2017-04-06 US US16/092,492 patent/US10629716B2/en active Active
Also Published As
Publication number | Publication date |
---|---|
CN109155255A (zh) | 2019-01-04 |
JP2017212425A (ja) | 2017-11-30 |
US10629716B2 (en) | 2020-04-21 |
US20190123187A1 (en) | 2019-04-25 |
CN109155255B (zh) | 2021-08-27 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP6614116B2 (ja) | 半導体装置 | |
US11056584B2 (en) | Semiconductor device | |
US8581301B2 (en) | Nitride semiconductor device | |
JP5548909B2 (ja) | 窒化物系半導体装置 | |
JP4645313B2 (ja) | 半導体装置 | |
JP5789967B2 (ja) | 半導体装置及びその製造方法、電源装置 | |
WO2015159450A1 (ja) | 半導体素子、電気機器、双方向電界効果トランジスタおよび実装構造体 | |
JP5653326B2 (ja) | 窒化物半導体装置 | |
US10134850B2 (en) | Semiconductor device | |
JP5214652B2 (ja) | 半導体装置 | |
US20120043588A1 (en) | Semiconductor device | |
KR20140042472A (ko) | 질화물 반도체 기반의 파워 변환 장치 | |
JP2015170821A (ja) | 窒化物半導体装置、電界効果トランジスタおよびカスコード接続回路 | |
US20170352753A1 (en) | Field-effect transistor | |
JPWO2016098390A1 (ja) | 電界効果トランジスタ | |
TW201535732A (zh) | 半導體裝置 | |
JP2019145703A (ja) | 半導体装置 | |
CN103681858A (zh) | 半导体装置 | |
JP5985162B2 (ja) | 窒化物系半導体装置 | |
CN106373996B (zh) | 半导体装置 | |
KR20140105056A (ko) | 반도체 소자 및 그 제조방법 | |
JP7176475B2 (ja) | 半導体装置 | |
WO2017203849A1 (ja) | 半導体装置 | |
JP2009044035A (ja) | 電界効果半導体装置 | |
JP2016062946A (ja) | 電界効果トランジスタ |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20180724 |
|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20180724 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20191008 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20191021 |
|
R151 | Written notification of patent or utility model registration |
Ref document number: 6614116 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R151 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |