JP6598151B2 - Semiconductor device and manufacturing method thereof - Google Patents

Semiconductor device and manufacturing method thereof Download PDF

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JP6598151B2
JP6598151B2 JP2015166104A JP2015166104A JP6598151B2 JP 6598151 B2 JP6598151 B2 JP 6598151B2 JP 2015166104 A JP2015166104 A JP 2015166104A JP 2015166104 A JP2015166104 A JP 2015166104A JP 6598151 B2 JP6598151 B2 JP 6598151B2
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semiconductor chip
semiconductor
semiconductor device
alloy layer
bonding material
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JP2017045804A (en
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基治 芳我
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Rohm Co Ltd
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Description

本発明は、半導体装置およびその製造方法に関する。   The present invention relates to a semiconductor device and a manufacturing method thereof.

特許文献1は、半導体チップと、半導体チップに接合されたダイパッドとを備える半導体装置を開示している。半導体チップの裏面には、Au,Ni,Ag等を含有する裏面メタルとAgめっき膜とがこの順に形成されている。この裏面メタルとダイパッドとが接合材を介して接続されることによって、半導体チップにダイパッドが接合されている。   Patent Document 1 discloses a semiconductor device including a semiconductor chip and a die pad bonded to the semiconductor chip. On the back surface of the semiconductor chip, a back metal containing Au, Ni, Ag and the like and an Ag plating film are formed in this order. The die pad is bonded to the semiconductor chip by connecting the back surface metal and the die pad via a bonding material.

特開2010−258231号公報JP 2010-258231 A

特許文献1では、半導体チップの裏面に裏面メタルやめっき膜を形成し、接合材に対する濡れ性を確保することにより、半導体チップを接続対象物に接続している。しかしながら、この構成では、裏面メタルやめっき膜を形成するための金属材料を別途用意し、しかも、それらの形成工程を追加しなければならず、必要とされる金属材料の増加および工数の増加に伴い半導体装置のコストが増大する。裏面メタルやめっき膜を形成しないことで、この問題を解決できるかもしれないが、この場合、接合材に対する半導体チップの濡れ性が不十分になる結果、半導体チップを接続対象物に接続させることができないという問題が生じる。   In Patent Document 1, a semiconductor chip is connected to an object to be connected by forming a back metal or plating film on the back surface of the semiconductor chip and ensuring wettability with respect to the bonding material. However, in this configuration, a metal material for forming the back surface metal and the plating film must be prepared separately, and the formation process thereof must be added, which increases the number of necessary metal materials and man-hours. As a result, the cost of the semiconductor device increases. This problem may be solved by not forming the back metal or plating film. In this case, however, the wettability of the semiconductor chip with respect to the bonding material becomes insufficient, so that the semiconductor chip can be connected to the connection object. The problem that it is not possible arises.

そこで、本発明は、半導体チップと接続対象物とを良好に接続できると共に、コスト削減に寄与できる半導体装置およびその製造方法を提供することを目的とする。   Therefore, an object of the present invention is to provide a semiconductor device that can satisfactorily connect a semiconductor chip and an object to be connected and can contribute to cost reduction, and a manufacturing method thereof.

本発明の一局面は金属製の接続対象物と、前記接続対象物上に配置された半導体チップとを含み、前記半導体チップは、前記半導体チップの裏面側から順に配置された合金層および金属製の接合材のみを介して前記接続対象物に接続されており、前記合金層は、前記接続対象物と同一の金属材料および前記半導体チップと同一の半導体材料を含む合金からなる、半導体装置を提供する。このような半導体装置は、たとえば、以下のような半導体装置の製造方法により製造される。 One station surface of the present invention includes a metallic object to be connected, and a semiconductor chip disposed on the connection object, the semiconductor chip, the alloy layer disposed in this order from the back side of the semiconductor chip and A semiconductor device connected to the connection object only through a metal bonding material, and wherein the alloy layer is made of an alloy containing the same metal material as the connection object and the same semiconductor material as the semiconductor chip. Provide . Such a semiconductor device is manufactured by, for example, the following semiconductor device manufacturing method.

すなわち、半導体装置の製造方法は、半導体チップを金属製の接合材を介して金属製の接続対象物上に接続する工程と、少なくとも前記接合材が溶融する温度で前記半導体チップを加熱することにより、前記半導体チップの裏面に、前記接続対象物の金属材料および前記半導体チップの半導体材料を含む合金層を成長させる工程とを含む。
この方法によれば、金属製の接合材の溶融によって接続対象物に含まれる金属材料が接合材中に拡散する。これにより、半導体チップの裏面に、接続対象物の金属材料と前記半導体チップの半導体材料とを含む合金層が形成される。この合金層により、接合材に対する半導体チップの濡れ性を向上させることができるから、半導体チップと接続対象物とを接合材を介して良好に接続できる。しかも、半導体チップの裏面の合金層は、接続対象物の金属材料と前記半導体チップの半導体材料とによって形成されるから、裏面メタルやめっき膜を形成するための金属材料を別途用意したり、それらの形成工程を追加したりする必要がない。その結果、比較的シンプルな構造であり、コスト削減に寄与できる半導体装置およびその製造方法を提供できる。
That is, a method for manufacturing a semiconductor device includes a step of connecting a semiconductor chip onto a metal connection object via a metal bonding material, and heating the semiconductor chip at a temperature at which the bonding material melts. And a step of growing an alloy layer containing the metal material of the connection object and the semiconductor material of the semiconductor chip on the back surface of the semiconductor chip.
According to this method, the metal material contained in the connection object diffuses into the bonding material due to the melting of the metal bonding material. Thereby, the alloy layer containing the metal material of the connection object and the semiconductor material of the semiconductor chip is formed on the back surface of the semiconductor chip. Since the alloy layer can improve the wettability of the semiconductor chip with respect to the bonding material, the semiconductor chip and the connection target can be favorably connected via the bonding material. Moreover, since the alloy layer on the back surface of the semiconductor chip is formed by the metal material of the connection object and the semiconductor material of the semiconductor chip, a metal material for forming the back surface metal or the plating film can be prepared separately, There is no need to add a forming step. As a result, it is possible to provide a semiconductor device that has a relatively simple structure and can contribute to cost reduction, and a manufacturing method thereof.

前記製造方法において、前記半導体チップと一体を成し、かつ、前記半導体チップの裏面全域を形成するように前記合金層を成長させてもよい。この方法によれば、半導体チップと接続対象物とをより一層良好に接続できる。
前記製造方法において、脱酸素雰囲気中で前記半導体チップを加熱し、前記合金層を成長させることが好ましい。この方法によれば、少なくとも接続対象物および半導体チップの酸化を回避できるから、合金層中に酸化物が介在(混入)するのを効果的に抑制できる。これにより、良好な合金層を形成できるから、半導体チップと接続対象物とをより一層良好に接続できる。前記製造方法において、窒素ガス雰囲気中で前記半導体チップを加熱し、前記合金層を成長させてもよい。
In the manufacturing method, the alloy layer may be grown so as to be integrated with the semiconductor chip and to form the entire back surface of the semiconductor chip. According to this method, it is possible to connect the semiconductor chip and the connection object even better.
In the manufacturing method, it is preferable that the semiconductor chip is heated in a deoxygenated atmosphere to grow the alloy layer. According to this method, since at least the oxidation of the connection object and the semiconductor chip can be avoided, it is possible to effectively suppress the oxide from interposing (mixing) in the alloy layer. Thereby, since a favorable alloy layer can be formed, a semiconductor chip and a connection object can be connected still more favorably. In the manufacturing method, the alloy chip may be grown by heating the semiconductor chip in a nitrogen gas atmosphere.

前記半導体装置において、前記合金層は、前記半導体チップと一体を成し、かつ、前記半導体チップの裏面全域を形成していることが好ましい。この構成によれば、半導体チップと接続対象物とをより一層良好に接続できる。
前記半導体装置において、前記接合材は、前記合金層の側部を被覆していることが好ましい。この構成によれば、接合材に対する半導体チップの接触面積が増大するから、半導体チップと接続対象物とをより一層良好に接続できる。
In the semiconductor device, it is preferable that the alloy layer is integrated with the semiconductor chip and forms the entire back surface of the semiconductor chip. According to this structure, a semiconductor chip and a connection target object can be connected still more favorably.
In the semiconductor device, it is preferable that the bonding material covers a side portion of the alloy layer. According to this configuration, since the contact area of the semiconductor chip with respect to the bonding material increases, the semiconductor chip and the connection object can be connected more satisfactorily.

前記半導体装置において、前記接続対象物における前記半導体チップが配置された部分には凹部が形成されており、前記接合材は、前記凹部に入り込んでいることが好ましい。また、前記凹部は、平面視において前記半導体チップの面積よりも大きい面積で形成されていることが好ましい。
前記半導体装置の製造方法において、接続対象物では、金属材料の拡散に伴って当該接続対象物を構成する金属材料の一部が失われる。そのため、拡散した金属材料の質量に対応する容積の凹部が半導体チップが配置された部分に形成される。接合材は、溶融によってこの凹部を埋めつつ、接続対象物と半導体チップとを接続させる。これにより、接続対象物に対する接合材のアンカー効果を向上できるので、半導体チップと接続対象物との接続強度を向上できる。また、この構成に加えて、前記接合材が前記合金層の側部を被覆する構成を採用することによって、接合材に対する半導体チップの接触面積を効果的に増大させることができる。これにより、半導体チップと接続対象物との接続強度をより一層向上できる。
In the semiconductor device, it is preferable that a concave portion is formed in a portion where the semiconductor chip is disposed in the connection object, and the bonding material enters the concave portion. Moreover, it is preferable that the said recessed part is formed in an area larger than the area of the said semiconductor chip in planar view.
In the method for manufacturing a semiconductor device, in the connection target, part of the metal material constituting the connection target is lost with the diffusion of the metal material. Therefore, a recess having a volume corresponding to the mass of the diffused metal material is formed in the portion where the semiconductor chip is disposed. The bonding material connects the connection object and the semiconductor chip while filling the concave portion by melting. Thereby, since the anchor effect of the joining material with respect to a connection target object can be improved, the connection strength of a semiconductor chip and a connection target object can be improved. In addition to this configuration, by adopting a configuration in which the bonding material covers the side portion of the alloy layer, the contact area of the semiconductor chip with respect to the bonding material can be effectively increased. Thereby, the connection strength between the semiconductor chip and the connection object can be further improved.

前記半導体装置は、前記半導体チップに接続されたワイヤをさらに含んでいてもよい。前記半導体装置は、前記接続対象物の表面を覆うAgめっき膜と、前記半導体チップに接続されたCuまたはAuを含むワイヤとをさらに含んでいてもよい。前記半導体装置は、前記接続対象物および前記半導体チップを封止する封止樹脂をさらに含んでいてもよい。
前記半導体装置において、前記接続対象物は、Cu系接続対象物であり、前記半導体チップは、Si系半導体チップであり、前記合金層は、SiCu合金層であってもよい。前記接合材は、Pb系接合材であってもよい。
The semiconductor device may further include a wire connected to the semiconductor chip. The semiconductor device may further include an Ag plating film that covers a surface of the connection object, and a wire containing Cu or Au connected to the semiconductor chip. The semiconductor device may further include a sealing resin that seals the connection object and the semiconductor chip.
In the semiconductor device, the connection target may be a Cu-based connection target, the semiconductor chip may be a Si-based semiconductor chip, and the alloy layer may be a SiCu alloy layer. The bonding material may be a Pb-based bonding material.

本発明の他の局面はCu系接続対象物と、前記Cu系接続対象物上に配置されたSi系半導体チップとを含み、前記半導体チップは、前記半導体チップの裏面側から順に配置されたSiCu合金層およびPb系接合材のみを介して前記Cu系接続対象物に接続されている、半導体装置を提供する。この構成によれば、前述のように、半導体チップと接続対象物と良好に接続できると共に、比較的シンプルな構造であり、コスト削減に寄与できる半導体装置を提供できる。 Other stations surface of the present invention includes a Cu-based connection object, and a Si-based semiconductor chip that is disposed on the Cu-based connection object, wherein the semiconductor chip is disposed in order from the back side of the semiconductor chip A semiconductor device is provided that is connected to the Cu-based connection object only through the SiCu alloy layer and the Pb-based bonding material . According to this configuration, as described above, it is possible to provide a semiconductor device that can satisfactorily connect the semiconductor chip and the connection target and has a relatively simple structure and contributes to cost reduction.

図1Aは、本発明の第1実施形態に係る半導体装置の斜視図である。FIG. 1A is a perspective view of the semiconductor device according to the first embodiment of the present invention. 図1Bは、図1Aに示す半導体装置の平面図である。1B is a plan view of the semiconductor device shown in FIG. 1A. 図2は、図1Aに示すII-II線に沿う断面図である。2 is a cross-sectional view taken along line II-II shown in FIG. 1A. 図3は、図2の一点鎖線で囲んだ領域の拡大断面図である。FIG. 3 is an enlarged cross-sectional view of a region surrounded by an alternate long and short dash line in FIG. 図4Aは、図1Aに示す半導体装置の製造工程の一部を示す断面図である。FIG. 4A is a cross-sectional view showing a part of the manufacturing process of the semiconductor device shown in FIG. 1A. 図4Bは、図4Aの次の工程を示す断面図である。FIG. 4B is a cross-sectional view showing a step subsequent to FIG. 4A. 図4Cは、図4Bの次の工程を示す断面図である。FIG. 4C is a cross-sectional view showing a step subsequent to FIG. 4B. 図5は、本発明の第2実施形態に係る半導体装置の斜視図である。FIG. 5 is a perspective view of a semiconductor device according to the second embodiment of the present invention. 図6は、図5に示すVI-VI線に沿う断面図である。6 is a cross-sectional view taken along the line VI-VI shown in FIG. 図7Aは、図5に示す半導体装置の製造工程の一部を示す断面図である。FIG. 7A is a cross-sectional view showing a part of the manufacturing process of the semiconductor device shown in FIG. 図7Bは、図7Aの次の工程を示す断面図である。FIG. 7B is a cross-sectional view showing a step subsequent to FIG. 7A. 図7Cは、図7Bの次の工程を示す断面図である。FIG. 7C is a cross-sectional view showing a step subsequent to FIG. 7B. 図7Dは、図7Cの次の工程を示す断面図である。FIG. 7D is a cross-sectional view showing a step subsequent to FIG. 7C. 図8は、第3実施形態に係る半導体装置の斜視図である。FIG. 8 is a perspective view of the semiconductor device according to the third embodiment. 図9は、第4実施形態に係る半導体装置の斜視図である。FIG. 9 is a perspective view of the semiconductor device according to the fourth embodiment. 図10は、一の例に係る半導体パッケージの断面図である。FIG. 10 is a cross-sectional view of a semiconductor package according to one example. 図11は、他の例に係る半導体パッケージの断面図である。FIG. 11 is a cross-sectional view of a semiconductor package according to another example. 図12は、さらに他の例に係る半導体パッケージの外観図である。FIG. 12 is an external view of a semiconductor package according to still another example.

以下では、本発明の実施形態を、添付図面を参照して詳細に説明する。
<第1実施形態>
図1Aは、本発明の第1実施形態に係る半導体装置1の斜視図である。図1Bは、図1Aに示す半導体装置1の平面図である。図2は、図1Aに示すII-II線に沿う断面図である。図3は、図2の一点鎖線で囲んだ領域Dの拡大断面図である。
Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
<First Embodiment>
FIG. 1A is a perspective view of the semiconductor device 1 according to the first embodiment of the present invention. FIG. 1B is a plan view of the semiconductor device 1 shown in FIG. 1A. 2 is a cross-sectional view taken along line II-II shown in FIG. 1A. FIG. 3 is an enlarged cross-sectional view of a region D surrounded by an alternate long and short dash line in FIG.

半導体装置1は、フレーム2を含む。フレーム2は、Cu系の金属薄板からなる。フレーム2は、たとえば、Cu−Fe系合金、Cu−Zr系合金のようにCuを主成分として含む金属の他、Fe等のCu以外の金属を主成分として含み、Cuを副成分として含む金属(たとえば、Cuが添加された42アロイ等)であってもよい。むろん、フレーム2は、純度95%以上の高純度銅、純度99.99%(4N)以上の高純度銅、純度99.9999%(6N)以上の高純度銅等であってもよい。フレーム2の厚さは、たとえば100μm以上600μm以下であってもよい。   The semiconductor device 1 includes a frame 2. The frame 2 is made of a Cu-based metal thin plate. The frame 2 includes, for example, a metal containing Cu as a main component, such as a Cu—Fe based alloy or a Cu—Zr based alloy, a metal other than Cu such as Fe as a main component, and a metal containing Cu as a subcomponent. (For example, 42 alloy to which Cu is added) may be used. Of course, the frame 2 may be high-purity copper having a purity of 95% or higher, high-purity copper having a purity of 99.99% (4N) or higher, high-purity copper having a purity of 99.9999% (6N) or higher, or the like. The thickness of the frame 2 may be, for example, 100 μm or more and 600 μm or less.

フレーム2は、金属製の接続対象物の一例としてのダイパッド3と、リード4とを含む。本実施形態では、リード4がダイパッド3の片側にしか配置されていない例を示しているが、リード4は、ダイパッド3の両側に配置されていてもよいし、ダイパッド3を取り囲むようにその周囲に配置されていてもよい。このダイパッド3上には、半導体チップ5が配置されている。   The frame 2 includes a die pad 3 as an example of a metal connection object and leads 4. In the present embodiment, an example is shown in which the lead 4 is disposed only on one side of the die pad 3, but the lead 4 may be disposed on both sides of the die pad 3, or the periphery thereof so as to surround the die pad 3. May be arranged. A semiconductor chip 5 is disposed on the die pad 3.

半導体チップ5は、本実施形態では、Si系の半導体チップである。半導体チップ5は、たとえばSi基板を含んでいてもよいし、SiC基板を含んでいてもよい。半導体チップ5は、扁平な直方体形状に形成されており、ダイパッド3に対向する裏面5aと、その反対の表面5bと、裏面5aおよび表面5bを接続する側面5cとを有している。半導体チップ5は、その表面5bに電極パッド6を有している。   The semiconductor chip 5 is a Si-based semiconductor chip in this embodiment. The semiconductor chip 5 may include, for example, a Si substrate or a SiC substrate. The semiconductor chip 5 is formed in a flat rectangular parallelepiped shape, and has a back surface 5a that faces the die pad 3, an opposite surface 5b, and a side surface 5c that connects the back surface 5a and the surface 5b. The semiconductor chip 5 has an electrode pad 6 on its surface 5b.

電極パッド6は、ボンディングワイヤ7を介してリード4に電気的に接続されている。ボンディングワイヤ7は、本実施形態では、Alを含むAlワイヤである。一方、半導体チップ5は、裏面5a側において、半導体チップ5側から順に配置された合金層8および金属製の接合材9を介してダイパッド3に接続されている。なお、ダイパッド3が外部端子を兼ねており通電する場合等は、半導体チップ5は、合金層8および金属製の接合材9を介してダイパッド3に電気的に接続されていてもよい。   The electrode pad 6 is electrically connected to the lead 4 via the bonding wire 7. In the present embodiment, the bonding wire 7 is an Al wire containing Al. On the other hand, the semiconductor chip 5 is connected to the die pad 3 on the back surface 5a side via an alloy layer 8 and a metal bonding material 9 arranged in order from the semiconductor chip 5 side. When the die pad 3 also serves as an external terminal and is energized, the semiconductor chip 5 may be electrically connected to the die pad 3 via the alloy layer 8 and the metal bonding material 9.

合金層8は、ダイパッド3の金属材料および半導体チップ5の半導体材料を含む。合金層8は、本実施形態では、SiCu合金層である。合金層8は、半導体チップ5と一体を成し、かつ、半導体チップ5の裏面5a全域を形成している。また、合金層8の側部10は、半導体チップ5の側面5cの一部を形成しており、半導体チップ5の側面5cに対して平坦に形成されている。合金層8の厚さは、たとえば、5μm以上50μm以下であってもよい。   The alloy layer 8 includes the metal material of the die pad 3 and the semiconductor material of the semiconductor chip 5. The alloy layer 8 is a SiCu alloy layer in this embodiment. The alloy layer 8 is integrated with the semiconductor chip 5 and forms the entire back surface 5 a of the semiconductor chip 5. The side portion 10 of the alloy layer 8 forms a part of the side surface 5 c of the semiconductor chip 5 and is formed flat with respect to the side surface 5 c of the semiconductor chip 5. The thickness of the alloy layer 8 may be, for example, 5 μm or more and 50 μm or less.

接合材9は、Pbを主成分に含むPb系半田からなり、たとえば242℃以上342℃以下の融点を有する高融点半田を含む。接合材9は、1wt%以上10wt%以下のSnを含んでいてもよい。接合材9は、Pb−10Sn,Pb−1Sn、Pb−3Sn−1Ag,Pb−Sn−1Ag等であってもよい。なお、接合材9に対する合金層8の濡れ性は、接合材9に対する半導体チップ5の濡れ性よりも大きい。接合材9の厚さは、たとえば、10μm以上50μm以下であってもよい。   The bonding material 9 is made of Pb-based solder containing Pb as a main component and includes, for example, high melting point solder having a melting point of 242 ° C. or higher and 342 ° C. or lower. The bonding material 9 may contain 1 wt% or more and 10 wt% or less of Sn. The bonding material 9 may be Pb-10Sn, Pb-1Sn, Pb-3Sn-1Ag, Pb-Sn-1Ag, or the like. The wettability of the alloy layer 8 with respect to the bonding material 9 is greater than the wettability of the semiconductor chip 5 with respect to the bonding material 9. The thickness of the bonding material 9 may be, for example, 10 μm or more and 50 μm or less.

図3を参照して、合金層8は、半導体チップ5の角部において、他の部分(より具体的には、半導体チップ5の内方部の合金層8)よりも厚く形成された厚膜部11を有している。厚膜部11は、半導体チップ5の側面5cに沿ってダイパッド3側および表面5b側に向けて延びるように形成(厚化)されている。ダイパッド3における半導体チップ5が配置された部分には凹部12が形成されている。この凹部12は、半導体チップ5の表面5bの法線方向から見た平面視において半導体チップ5の面積よりも大きい面積で形成されており、半導体チップ5の側面5cを取り囲んでいる。   Referring to FIG. 3, alloy layer 8 is a thick film formed thicker at the corner portion of semiconductor chip 5 than at other portions (more specifically, alloy layer 8 at the inner portion of semiconductor chip 5). Part 11. The thick film portion 11 is formed (thickened) so as to extend toward the die pad 3 side and the surface 5 b side along the side surface 5 c of the semiconductor chip 5. A recess 12 is formed in a portion of the die pad 3 where the semiconductor chip 5 is disposed. The recess 12 is formed in an area larger than the area of the semiconductor chip 5 in a plan view as viewed from the normal direction of the surface 5 b of the semiconductor chip 5, and surrounds the side surface 5 c of the semiconductor chip 5.

凹部12における半導体チップ5の角部に対向する部分には、凹部12の底部とダイパッド3の表面とを接続する滑らかな傾斜部12aが形成されている。傾斜部12aは、平面視において少なくとも一部が半導体チップ5外の領域に位置している。傾斜部12aは、たとえば半導体チップ5の角部を中心とする略円弧状の軌跡を描くように形成されている。接合材9は、凹部12に入り込むように形成されており、半導体チップ5の裏面5aの全域、つまり合金層8を被覆している。さらに、接合材9は、合金層8の側部10を被覆している。
図4A〜図4Cは、図1Aに示す半導体装置1の製造工程の一部を示す断面図である。なお、図4A〜図4Cは、図2に対応する断面図である。
A smooth inclined portion 12 a that connects the bottom of the recess 12 and the surface of the die pad 3 is formed in a portion of the recess 12 that faces the corner of the semiconductor chip 5. The inclined portion 12a is at least partially located in a region outside the semiconductor chip 5 in plan view. The inclined portion 12a is formed so as to draw a substantially arc-shaped locus centering on the corner portion of the semiconductor chip 5, for example. The bonding material 9 is formed so as to enter the recess 12, and covers the entire back surface 5 a of the semiconductor chip 5, that is, the alloy layer 8. Further, the bonding material 9 covers the side portion 10 of the alloy layer 8.
4A to 4C are cross-sectional views showing a part of the manufacturing process of the semiconductor device 1 shown in FIG. 1A. 4A to 4C are cross-sectional views corresponding to FIG.

半導体装置1を製造するには、まず、プレス加工により形成されたダイパッド3およびリード4を含むフレーム2が用意される。次に、図4Aに示すように、たとえば公知のダイボンダ15を用いて、Pb系半田からなる接合材9がダイパッド3上に塗布された後、半導体チップ5が配置される。次に、少なくとも接合材9が溶融する温度(たとえば、350℃以上400℃以下の温度)で数秒〜数十秒間、リフローが実行される。これにより、半導体チップ5が接合材9を介してダイパッド3上に接続される。半導体チップ5の裏面5aは、より具体的には、剥き出し面であり接合材9に対して直接接続される。   In order to manufacture the semiconductor device 1, first, a frame 2 including a die pad 3 and leads 4 formed by pressing is prepared. Next, as shown in FIG. 4A, for example, a known die bonder 15 is used to apply the bonding material 9 made of Pb-based solder onto the die pad 3, and then the semiconductor chip 5 is disposed. Next, reflow is performed for several seconds to several tens of seconds at least at a temperature at which the bonding material 9 melts (for example, a temperature of 350 ° C. or higher and 400 ° C. or lower). Thereby, the semiconductor chip 5 is connected to the die pad 3 through the bonding material 9. More specifically, the back surface 5 a of the semiconductor chip 5 is a bare surface and is directly connected to the bonding material 9.

次に、図4Bに示すように、たとえば公知の熱処理炉16を用いて、少なくとも接合材9が溶融する温度(たとえば、350℃以上400℃以下の温度)で半導体チップ5が加熱される。半導体チップ5は、脱酸素雰囲気中で、10分以上、より具体的には30分から60分の間、加熱される。脱酸素雰囲気とは、熱処理炉16中の酸素濃度が極めて低い雰囲気(たとえば、酸素濃度0.1%以下の雰囲気)のことを言う。本実施形態では、窒素ガス(窒素濃度95%程度)および水素ガス(水素濃度5%程度)の混合雰囲気中で、半導体チップ5が加熱される。   Next, as shown in FIG. 4B, the semiconductor chip 5 is heated at least at a temperature at which the bonding material 9 is melted (for example, a temperature of 350 ° C. or more and 400 ° C. or less) using a known heat treatment furnace 16. The semiconductor chip 5 is heated in a deoxygenated atmosphere for 10 minutes or more, more specifically, for 30 to 60 minutes. The deoxygenated atmosphere refers to an atmosphere in which the oxygen concentration in the heat treatment furnace 16 is extremely low (for example, an atmosphere having an oxygen concentration of 0.1% or less). In the present embodiment, the semiconductor chip 5 is heated in a mixed atmosphere of nitrogen gas (nitrogen concentration of about 95%) and hydrogen gas (hydrogen concentration of about 5%).

熱処理が開始されると、接合材9の溶融が始まる。接合材9が溶融すると、ダイパッド3のCuが接合材9中に拡散する。この拡散したCuが半導体チップ5のSiと反応することにより、ダイパッド3のCuと半導体チップ5のSiとを含むSiCu合金層8が、半導体チップ5の裏面5a全域に成長する。そして、ダイパッド3では、Cuの拡散に伴って当該ダイパッド3を形成するCuの一部が失われる。そのため、図4Cに示すように、拡散したCuの質量に対応する容積の凹部12が半導体チップ5が配置された部分に形成される。   When the heat treatment is started, the bonding material 9 starts to melt. When the bonding material 9 melts, Cu in the die pad 3 diffuses into the bonding material 9. The diffused Cu reacts with Si of the semiconductor chip 5, whereby a SiCu alloy layer 8 including Cu of the die pad 3 and Si of the semiconductor chip 5 grows over the entire back surface 5 a of the semiconductor chip 5. In the die pad 3, a part of Cu forming the die pad 3 is lost as Cu diffuses. Therefore, as shown in FIG. 4C, a recess 12 having a volume corresponding to the mass of the diffused Cu is formed in the portion where the semiconductor chip 5 is disposed.

この時、半導体チップ5の角部は、他の部分(たとえば半導体チップ5の内方部)に比してダイパッド3に対向する面積が大きい。したがって、半導体チップ5の角部では、他の部分に比して反応するCu量が多くなる結果、当該他の部分よりも厚い厚膜部11が形成される。一方、ダイパッド3における半導体チップ5の角部に対向する部分では、半導体チップ5の角部を中心とする略円弧状にCuが失われる。その結果、傾斜部12aを有し、平面視において半導体チップ5の面積よりも大きい面積の凹部12が形成される。接合材9は、溶融によってこの凹部12を埋めつつ、合金層8の側部10を被覆し、ダイパッド3と半導体チップ5とを接続させる。   At this time, the corner of the semiconductor chip 5 has a larger area facing the die pad 3 than other parts (for example, the inner part of the semiconductor chip 5). Therefore, at the corner portion of the semiconductor chip 5, the amount of Cu that reacts as compared with other portions increases, and as a result, a thicker film portion 11 than the other portions is formed. On the other hand, in the part facing the corner of the semiconductor chip 5 in the die pad 3, Cu is lost in a substantially arc shape centering on the corner of the semiconductor chip 5. As a result, the recess 12 having the inclined portion 12a and having an area larger than the area of the semiconductor chip 5 in plan view is formed. The bonding material 9 covers the side portion 10 of the alloy layer 8 while filling the concave portion 12 by melting, and connects the die pad 3 and the semiconductor chip 5.

なお、半導体チップ5の加熱時間は、合金層8の形成(成長)に十分な時間であればよく、上記時間に限定されるものではない。また、半導体チップ5は、連続的に加熱されてもよいし、所定時間(たとえば10分)毎に冷却時間を挟んで断続的に加熱されてもよい。また、本実施形態では、熱処理炉16で半導体チップ5を加熱した例について説明したが、ダイボンダ15内で同様の条件の下、半導体チップ5を加熱してもよい。   In addition, the heating time of the semiconductor chip 5 should just be sufficient time for formation (growth) of the alloy layer 8, and is not limited to the said time. Further, the semiconductor chip 5 may be continuously heated, or may be intermittently heated with a cooling time every predetermined time (for example, 10 minutes). In this embodiment, the example in which the semiconductor chip 5 is heated in the heat treatment furnace 16 has been described. However, the semiconductor chip 5 may be heated in the die bonder 15 under the same conditions.

その後、半導体チップ5の電極パッド6とリード4とを接続させるボンディングワイヤ7が取り付けられ、封止樹脂によりフレーム2、半導体チップ5、接合材9等が封止される。このようにして、半導体装置1が製造される。
以上、本実施形態では、半導体チップ5の裏面5aに、ダイパッド3のCuと半導体チップ5のSiとを含む合金層8が形成される。この合金層8により、接合材9に対する半導体チップ5の濡れ性を向上させることができるから、半導体チップ5とダイパッド3とを接合材9を介して良好に接続できる。しかも、この合金層8は、半導体チップ5と一体を成し、かつ、半導体チップ5の裏面5a全域を形成しているから、半導体チップ5とダイパッド3とをより一層良好に接続できる。
Thereafter, bonding wires 7 for connecting the electrode pads 6 of the semiconductor chip 5 and the leads 4 are attached, and the frame 2, the semiconductor chip 5, the bonding material 9 and the like are sealed with a sealing resin. In this way, the semiconductor device 1 is manufactured.
As described above, in this embodiment, the alloy layer 8 including Cu of the die pad 3 and Si of the semiconductor chip 5 is formed on the back surface 5 a of the semiconductor chip 5. Since the alloy layer 8 can improve the wettability of the semiconductor chip 5 with respect to the bonding material 9, the semiconductor chip 5 and the die pad 3 can be favorably connected via the bonding material 9. Moreover, since the alloy layer 8 is integrated with the semiconductor chip 5 and forms the entire back surface 5a of the semiconductor chip 5, the semiconductor chip 5 and the die pad 3 can be connected more satisfactorily.

また、半導体チップ5の裏面5aの合金層8は、ダイパッド3のCuと半導体チップ5のSiとによって形成されるから、裏面メタルやめっき膜を形成するための金属材料を別途用意したり、それらの形成工程を追加したりする必要がない。その結果、比較的シンプルな構造であり、コスト削減に寄与できる半導体装置1およびその製造方法を提供できる。   Further, since the alloy layer 8 on the back surface 5a of the semiconductor chip 5 is formed by Cu of the die pad 3 and Si of the semiconductor chip 5, a metal material for forming a back surface metal or a plating film is separately prepared, There is no need to add a forming step. As a result, it is possible to provide the semiconductor device 1 having a relatively simple structure and contributing to cost reduction, and a manufacturing method thereof.

また、本実施形態では、接合材9は、凹部12内でダイパッド3と半導体チップ5を接続し、かつ、半導体チップ5の側面5c側で合金層8の側部10を被覆している。これにより、ダイパッド3に対する接合材9のアンカー効果を向上できると共に、接合材9に対する半導体チップ5の接触面積を増大させることができる。その結果、半導体チップ5とダイパッド3との接続強度をより一層向上できる。   In the present embodiment, the bonding material 9 connects the die pad 3 and the semiconductor chip 5 in the recess 12, and covers the side portion 10 of the alloy layer 8 on the side surface 5 c side of the semiconductor chip 5. Thereby, the anchor effect of the bonding material 9 with respect to the die pad 3 can be improved, and the contact area of the semiconductor chip 5 with respect to the bonding material 9 can be increased. As a result, the connection strength between the semiconductor chip 5 and the die pad 3 can be further improved.

また、本実施形態の製造方法では、脱酸素雰囲気中、より具体的には、窒素ガスおよび水素ガスの混合雰囲気中で半導体チップ5を加熱し、合金層8を成長させている。この方法によれば、少なくともダイパッド3および半導体チップ5の酸化を回避できるから、合金層8中に酸化物が介在(混入)するのを効果的に抑制できる。これにより、良好な合金層8を形成できるから、半導体チップ5とダイパッド3とをより一層良好に接続できる。
<第2実施形態>
図5は、本発明の第2実施形態に係る半導体装置21の斜視図である。図6は、図5に示すVI-VI線に沿う断面図である。図5および図6において、前述の図1Aおよび図2等に示された部分に対応する部分については同一の参照符号を付して、説明を省略する。半導体装置21は、フレーム2の表面を覆うAgめっき膜22と、リード4および半導体チップ5に接続されたボンディングワイヤ23とをさらに含む。ボンディングワイヤ23は、本実施形態では、AuまたはCuを含むワイヤからなる。前述の凹部12は、Agめっき膜22を貫通するように形成されており、接合材9は、ダイパッド3およびAgめっき膜22に接している。その他の点は、前述の半導体装置1と同様である。
In the manufacturing method of the present embodiment, the semiconductor chip 5 is heated in a deoxygenated atmosphere, more specifically, in a mixed atmosphere of nitrogen gas and hydrogen gas, and the alloy layer 8 is grown. According to this method, at least the oxidation of the die pad 3 and the semiconductor chip 5 can be avoided, so that it is possible to effectively suppress the inclusion (mixing) of oxide in the alloy layer 8. Thereby, since the favorable alloy layer 8 can be formed, the semiconductor chip 5 and the die pad 3 can be connected even better.
Second Embodiment
FIG. 5 is a perspective view of a semiconductor device 21 according to the second embodiment of the present invention. 6 is a cross-sectional view taken along the line VI-VI shown in FIG. 5 and FIG. 6, parts corresponding to those shown in FIG. 1A and FIG. 2 described above are denoted by the same reference numerals and description thereof is omitted. The semiconductor device 21 further includes an Ag plating film 22 that covers the surface of the frame 2, and a bonding wire 23 connected to the lead 4 and the semiconductor chip 5. In the present embodiment, the bonding wire 23 is made of a wire containing Au or Cu. The aforementioned recess 12 is formed so as to penetrate the Ag plating film 22, and the bonding material 9 is in contact with the die pad 3 and the Ag plating film 22. Other points are the same as those of the semiconductor device 1 described above.

図7A〜図7Dは、図5に示す半導体装置21の製造工程の一部を示す断面図である。
半導体装置21を製造するには、まず、Agめっき処理が表面に施された金属薄板が用意される。Agめっき処理は、たとえばレジストマスクを用いた部分めっき処理であってもよい。次に、金属薄板がプレス加工されて、Agめっき膜22が表面に形成されたフレーム2が形成される。次に、図7Aに示すように、図4Aと同様の工程が実行されて、半導体チップ5が接合材9を介してダイパッド3上に接続される。
7A to 7D are cross-sectional views showing a part of the manufacturing process of the semiconductor device 21 shown in FIG.
In order to manufacture the semiconductor device 21, first, a metal thin plate having an Ag plating treatment on the surface is prepared. The Ag plating process may be a partial plating process using a resist mask, for example. Next, the metal thin plate is pressed to form the frame 2 on which the Ag plating film 22 is formed. Next, as shown in FIG. 7A, the same process as in FIG. 4A is performed, and the semiconductor chip 5 is connected to the die pad 3 through the bonding material 9.

次に、図7Bに示すように、前述の図4Bと同様の条件下で、半導体チップ5が熱処理炉16にて加熱される。熱処理が開始されると、接合材9の溶融が始まる。接合材9が溶融すると、接合材9は、Agめっき膜22内に溶け込み、進入する。そして、接合材9がAgめっき膜22内に進入すると、図7Cに示すように、ダイパッド3のCuが接合材9中に拡散する。この拡散したCuが半導体チップ5のSiと反応することにより、ダイパッド3のCuと半導体チップ5のSiとを含むSiCu合金層8が、半導体チップ5の裏面5a全域に成長する。   Next, as shown in FIG. 7B, the semiconductor chip 5 is heated in a heat treatment furnace 16 under the same conditions as in FIG. 4B described above. When the heat treatment is started, the bonding material 9 starts to melt. When the bonding material 9 is melted, the bonding material 9 melts into the Ag plating film 22 and enters. Then, when the bonding material 9 enters the Ag plating film 22, Cu in the die pad 3 diffuses into the bonding material 9 as shown in FIG. 7C. The diffused Cu reacts with Si of the semiconductor chip 5, whereby a SiCu alloy layer 8 including Cu of the die pad 3 and Si of the semiconductor chip 5 grows over the entire back surface 5 a of the semiconductor chip 5.

一方、ダイパッド3では、Cuの拡散に伴って当該ダイパッド3を形成するCuの一部が失われる。そのため、図7Dに示すように、拡散したCuの質量に対応する容積の凹部12が半導体チップ5が配置された部分に形成される。ここで形成される凹部12の具体的な構成は、前述の図4Cにおいて説明したものと略同様であるので、説明を省略する。以上、本実施形態によっても、前述の実施形態において述べた効果と同様の効果を奏することができる。
<第3実施形態>
図8は、第3実施形態に係る半導体装置31の斜視図である。半導体装置31が前述の半導体装置1(図1A等参照)と異なる点は、接合材9の全体が、凹部12内に配置されている点である。接合材9は、凹部12内で合金層8の側部10の一部を被覆していてもよい。半導体装置31のその他の構成は、前述の半導体装置1と略同様である。このような構成によっても、半導体チップ5とダイパッド3とを良好に接続できると共に、コスト削減に寄与できる半導体装置1およびその製造方法を提供できる。図8において、前述の半導体装置1に対応する部分については同一の参照符号を付して、説明を省略する。
<第4実施形態>
図9は、第4実施形態に係る半導体装置32の斜視図である。半導体装置32が前述の半導体装置21(図6等参照)と異なる点は、接合材9の全体が、凹部12内に配置されている点である。接合材9は、凹部12内で合金層8の側部10の一部を被覆していてもよい。半導体装置32のその他の構成は、前述の半導体装置21と略同様である。このような構成によっても、半導体チップ5とダイパッド3とを良好に接続できると共に、コスト削減に寄与できる半導体装置1およびその製造方法を提供できる。図9において、前述の半導体装置21に対応する部分については同一の参照符号を付して、説明を省略する。
On the other hand, in the die pad 3, a part of Cu forming the die pad 3 is lost with the diffusion of Cu. Therefore, as shown in FIG. 7D, a recess 12 having a volume corresponding to the mass of the diffused Cu is formed in the portion where the semiconductor chip 5 is disposed. The specific configuration of the recess 12 formed here is substantially the same as that described with reference to FIG. As described above, according to this embodiment, the same effect as that described in the above embodiment can be obtained.
<Third Embodiment>
FIG. 8 is a perspective view of the semiconductor device 31 according to the third embodiment. The semiconductor device 31 is different from the semiconductor device 1 described above (see FIG. 1A and the like) in that the entire bonding material 9 is disposed in the recess 12. The bonding material 9 may cover a part of the side portion 10 of the alloy layer 8 in the recess 12. Other configurations of the semiconductor device 31 are substantially the same as those of the semiconductor device 1 described above. Even with such a configuration, it is possible to provide a semiconductor device 1 and a method for manufacturing the same that can satisfactorily connect the semiconductor chip 5 and the die pad 3 and contribute to cost reduction. In FIG. 8, parts corresponding to those of the semiconductor device 1 described above are denoted by the same reference numerals and description thereof is omitted.
<Fourth embodiment>
FIG. 9 is a perspective view of the semiconductor device 32 according to the fourth embodiment. The semiconductor device 32 is different from the above-described semiconductor device 21 (see FIG. 6 and the like) in that the entire bonding material 9 is disposed in the recess 12. The bonding material 9 may cover a part of the side portion 10 of the alloy layer 8 in the recess 12. Other configurations of the semiconductor device 32 are substantially the same as those of the semiconductor device 21 described above. Even with such a configuration, it is possible to provide a semiconductor device 1 and a method for manufacturing the same that can satisfactorily connect the semiconductor chip 5 and the die pad 3 and contribute to cost reduction. 9, parts corresponding to those of the semiconductor device 21 described above are given the same reference numerals, and descriptions thereof are omitted.

以上、本発明の複数の実施形態について説明したが、本発明はさらに他の形態で実施することもできる。
たとえば、前述の各実施形態では、Cu系ダイパッド3、Si系半導体チップ5およびPb系接合材9を用いて、SiCu合金層8が形成された例について説明した。しかしながら、ダイパッド3の金属材料、半導体チップ5の半導体材料および接合材9の材料は、Cu系、Si系、Pb系に限定されるものではない。ダイパッド3、半導体チップ5および接合材9を用いて合金層8を形成し、ダイパッド3と半導体チップ5とを接続できるのであれば、種々の金属材料、半導体材料および接合材を使用できる。
Although a plurality of embodiments of the present invention have been described above, the present invention can also be implemented in other forms.
For example, in each of the above-described embodiments, the example in which the SiCu alloy layer 8 is formed using the Cu-based die pad 3, the Si-based semiconductor chip 5, and the Pb-based bonding material 9 has been described. However, the metal material of the die pad 3, the semiconductor material of the semiconductor chip 5, and the material of the bonding material 9 are not limited to Cu, Si, and Pb. As long as the alloy layer 8 is formed using the die pad 3, the semiconductor chip 5, and the bonding material 9 and the die pad 3 and the semiconductor chip 5 can be connected, various metal materials, semiconductor materials, and bonding materials can be used.

また、前述の各実施形態に適用される半導体チップ5は、表面5bから裏面5aに至る電流経路を有するいわゆる縦型の半導体素を含んでいてもよいし、表面5bに対して平行な電流経路を有するいわゆる横型の半導体素子を含んでいてもよい。半導体チップ5は、たとえば、抵抗、コンデンサ、ダイオード、バイポーラトランジスタ、MISFET、IGBT等の半導体素子を含んでいてもよい。また、半導体チップ5は、これら半導体素子の組み合わせにより、LSI等の集積回路を含んでいてもよい。   The semiconductor chip 5 applied to each of the above-described embodiments may include a so-called vertical semiconductor element having a current path from the front surface 5b to the back surface 5a, or a current path parallel to the front surface 5b. A so-called horizontal semiconductor element having the above may be included. The semiconductor chip 5 may include semiconductor elements such as resistors, capacitors, diodes, bipolar transistors, MISFETs, and IGBTs. In addition, the semiconductor chip 5 may include an integrated circuit such as an LSI by combining these semiconductor elements.

また、前述の各実施形態において、半導体装置1,21,31は、フレーム2、半導体チップ5、接合材9等がモールド樹脂で封止されることによって、図10〜図12に示すように半導体パッケージとして構成されていてもよい。
図10は、一の例に係る半導体パッケージ41の断面図である。
半導体パッケージ41は、SOP(Small Outline Package)タイプの半導体パッケージである。半導体パッケージ41は、前述のフレーム2と、前述の半導体チップ5と、これらを封止するモールド樹脂42とを含む。モールド樹脂42は、エポキシ樹脂であってもよい。フレーム2は、前述のダイパッド3および複数の前述のリード4を含む。フレーム2の表面には、Agめっき膜22が形成されていてもよい。半導体チップ5は、前述の第1〜第4実施形態で説明した通り、前述の合金層8および接合材9を介してダイパッド3上に接続されている。
Further, in each of the above-described embodiments, the semiconductor devices 1, 21, and 31 are configured such that the frame 2, the semiconductor chip 5, the bonding material 9, and the like are sealed with a mold resin, as shown in FIGS. It may be configured as a package.
FIG. 10 is a cross-sectional view of a semiconductor package 41 according to an example.
The semiconductor package 41 is a SOP (Small Outline Package) type semiconductor package. The semiconductor package 41 includes the above-described frame 2, the above-described semiconductor chip 5, and a mold resin 42 that seals them. The mold resin 42 may be an epoxy resin. The frame 2 includes the aforementioned die pad 3 and a plurality of the aforementioned leads 4. An Ag plating film 22 may be formed on the surface of the frame 2. The semiconductor chip 5 is connected on the die pad 3 through the alloy layer 8 and the bonding material 9 as described in the first to fourth embodiments.

複数のリード4は、ダイパッド3の両側に配置されていてもよいし、ダイパッド3を取り囲むようにその周囲に配置されていてもよい。複数のリード4の一部は、外部接続される外部端子としてモールド樹脂42から露出している。複数のリード4は、モールド樹脂42内において、ボンディングワイヤ7,23を介して半導体チップ5の電極パッド6に電気的に接続されている。複数のリード4の幾つかは、ダイパッド3を支持するようにダイパッド3と一体的に形成されていてもよい。   The plurality of leads 4 may be arranged on both sides of the die pad 3 or may be arranged around the die pad 3 so as to surround the die pad 3. Some of the plurality of leads 4 are exposed from the mold resin 42 as external terminals to be externally connected. The plurality of leads 4 are electrically connected to the electrode pads 6 of the semiconductor chip 5 through the bonding wires 7 and 23 in the mold resin 42. Some of the plurality of leads 4 may be formed integrally with the die pad 3 so as to support the die pad 3.

図11は、他の例に係る半導体パッケージ45の断面図である。
半導体パッケージ45は、QFN(Quad For Non Lead Package)タイプの半導体パッケージである。半導体パッケージ45は、前述のフレーム2と、前述の半導体チップ5と、これらを封止するモールド樹脂42とを含む。フレーム2は、前述のダイパッド3および複数の前述のリード4を含む。フレーム2の表面には、Agめっき膜22が形成されていてもよい。半導体チップ5は、前述の第1〜第4実施形態で説明した通り、前述の合金層8および接合材9を介してダイパッド3上に接続されている。
FIG. 11 is a cross-sectional view of a semiconductor package 45 according to another example.
The semiconductor package 45 is a QFN (Quad For Non Lead Package) type semiconductor package. The semiconductor package 45 includes the frame 2 described above, the semiconductor chip 5 described above, and a mold resin 42 for sealing them. The frame 2 includes the aforementioned die pad 3 and a plurality of the aforementioned leads 4. An Ag plating film 22 may be formed on the surface of the frame 2. The semiconductor chip 5 is connected on the die pad 3 through the alloy layer 8 and the bonding material 9 as described in the first to fourth embodiments.

ダイパッド3の下面は、モールド樹脂42から露出しており、ヒートシンクの機能を兼ねている。ダイパッド3は、外部接続される外部端子の機能を兼ねていてもよい。複数のリード4は、ダイパッド3の両側に配置されていてもよいし、ダイパッド3を取り囲むようにその周囲に配置されていてもよい。リード4の下面は、外部接続される外部端子としてモールド樹脂42から露出している。リード4の上面には、ボンディングワイヤ7,23が接続されている。ボンディングワイヤ7,23は、半導体チップ5の電極パッド6に電気的に接続されている。   The lower surface of the die pad 3 is exposed from the mold resin 42 and also serves as a heat sink. The die pad 3 may also function as an external terminal connected externally. The plurality of leads 4 may be arranged on both sides of the die pad 3 or may be arranged around the die pad 3 so as to surround the die pad 3. The lower surface of the lead 4 is exposed from the mold resin 42 as an external terminal connected externally. Bonding wires 7 and 23 are connected to the upper surface of the lead 4. The bonding wires 7 and 23 are electrically connected to the electrode pads 6 of the semiconductor chip 5.

図12は、さらに他の例に係る半導体パッケージ46の外観図である。
半導体パッケージ46は、TO−220等のいわゆるTO(Transistor Outline)系の半導体パッケージである。半導体パッケージ46は、前述のフレーム2と、前述の半導体チップ5と、これらを封止するモールド樹脂42とを含む。フレーム2は、前述のダイパッド3および複数の前述のリード4を含む。フレーム2の表面には、Agめっき膜22が形成されていてもよい。半導体チップ5は、前述の第1〜第4実施形態で説明した通り、前述の合金層8および接合材9を介してダイパッド3上に接続されている。
FIG. 12 is an external view of a semiconductor package 46 according to still another example.
The semiconductor package 46 is a so-called TO (Transistor Outline) type semiconductor package such as TO-220. The semiconductor package 46 includes the frame 2 described above, the semiconductor chip 5 described above, and a mold resin 42 for sealing them. The frame 2 includes the aforementioned die pad 3 and a plurality of the aforementioned leads 4. An Ag plating film 22 may be formed on the surface of the frame 2. The semiconductor chip 5 is connected on the die pad 3 through the alloy layer 8 and the bonding material 9 as described in the first to fourth embodiments.

複数のリード4には、3つの端子47,48,49が含まれる。3つの端子47,48,49は、ダイパッド3の方側に互いに間隔を空けて配置されている。3つの端子47,48,49のうち中央の端子48は、ダイパッド3と一体的に形成されている。3つの端子47,48,49のうち両側の端子47,49は、中央の端子48を両側から挟むように配置されている。両側の端子47,49は、それぞれボンディングワイヤ7,23によって半導体チップ5の電極パッド6に電気的に接続されている。3つの端子47,48,49の一部は、外部接続される外部端子としてモールド樹脂42から露出している。   The plurality of leads 4 include three terminals 47, 48 and 49. The three terminals 47, 48, and 49 are disposed on the die pad 3 side with a space therebetween. Of the three terminals 47, 48 and 49, the central terminal 48 is formed integrally with the die pad 3. Of the three terminals 47, 48, 49, the terminals 47, 49 on both sides are arranged so as to sandwich the center terminal 48 from both sides. The terminals 47 and 49 on both sides are electrically connected to the electrode pads 6 of the semiconductor chip 5 by bonding wires 7 and 23, respectively. Some of the three terminals 47, 48, and 49 are exposed from the mold resin 42 as external terminals that are externally connected.

なお、半導体パッケージの形式は、図10〜図12の形式に制限されない。したがって、DFP(Dual Flat Package)、DIP(Dual Inline Package)、QFP(Quad Flat Package)、SIP(Single Inline Package)、SOJ(Small Outline J-leaded Package)等の公知の半導体パッケージや、これらに類する種々の半導体パッケージが適用されてもよい。   The semiconductor package format is not limited to the formats shown in FIGS. Therefore, known semiconductor packages such as DFP (Dual Flat Package), DIP (Dual Inline Package), QFP (Quad Flat Package), SIP (Single Inline Package), SOJ (Small Outline J-leaded Package), and the like Various semiconductor packages may be applied.

その他、特許請求の範囲に記載された事項の範囲で種々の設計変更を施すことが可能である。   In addition, various design changes can be made within the scope of matters described in the claims.

1 半導体装置
3 ダイパッド(接続対象物)
5 半導体チップ
7 ボンディングワイヤ
8 合金層(SiCu合金層)
9 接合材
10 接合材の側部
12 凹部
21 半導体装置
22 Agめっき膜
23 ボンディングワイヤ
1 Semiconductor device 3 Die pad (object to be connected)
5 Semiconductor chip 7 Bonding wire 8 Alloy layer (SiCu alloy layer)
9 Bonding material 10 Bonding material side 12 Recess 21 Semiconductor device 22 Ag plating film 23 Bonding wire

Claims (15)

金属製の接続対象物と、
前記接続対象物上に配置された半導体チップとを含み
前記半導体チップは、前記半導体チップの裏面側から順に配置された合金層および金属製の接合材のみを介して前記接続対象物に接続されており、
前記合金層は、前記接続対象物と同一の金属材料および前記半導体チップと同一の半導体材料を含む合金からなる、半導体装置。
A metal connection object;
And a semiconductor chip disposed on the connection object,
The semiconductor chip is connected to the connection object only through an alloy layer and a metal bonding material arranged in order from the back side of the semiconductor chip ,
The alloy layer, ing from including alloy the connection object and the same metal material and the semiconductor chip identical to the semiconductor material, the semiconductor device.
前記合金層は、前記半導体チップの裏面と一体を成し、前記半導体チップの裏面全域を形成している、請求項1に記載の半導体装置。   2. The semiconductor device according to claim 1, wherein the alloy layer is integrated with a back surface of the semiconductor chip and forms an entire back surface of the semiconductor chip. 前記接合材は、前記合金層の側部を被覆している、請求項1または2に記載の半導体装置。   The semiconductor device according to claim 1, wherein the bonding material covers a side portion of the alloy layer. 前記接続対象物における前記半導体チップが配置された部分には凹部が形成されており、
前記接合材は、前記凹部に入り込んでいる、請求項1〜3のいずれか一項に記載の半導体装置。
A concave portion is formed in a portion where the semiconductor chip is arranged in the connection object,
The semiconductor device according to claim 1, wherein the bonding material enters the recess.
前記凹部は、平面視において前記半導体チップの面積よりも大きい面積で形成されている、請求項4に記載の半導体装置。   The semiconductor device according to claim 4, wherein the recess is formed with an area larger than an area of the semiconductor chip in a plan view. 前記半導体チップに接続されたワイヤをさらに含む、請求項1〜5のいずれか一項に記載の半導体装置。   The semiconductor device according to claim 1, further comprising a wire connected to the semiconductor chip. 前記接続対象物の表面を覆うAgめっき膜と、
前記半導体チップに接続されたCuまたはAuを含むワイヤとをさらに含む、請求項1〜5のいずれか一項に記載の半導体装置。
An Ag plating film covering the surface of the connection object;
The semiconductor device according to claim 1, further comprising a wire containing Cu or Au connected to the semiconductor chip.
前記接続対象物および前記半導体チップを封止する封止樹脂をさらに含む、請求項1〜7のいずれか一項に記載の半導体装置。   The semiconductor device as described in any one of Claims 1-7 which further contains sealing resin which seals the said connection target object and the said semiconductor chip. 前記接続対象物は、Cu系接続対象物であり、
前記半導体チップは、Si系半導体チップであり、
前記合金層は、SiCu合金層である、請求項1〜8のいずれか一項に記載の半導体装置。
The connection object is a Cu-based connection object,
The semiconductor chip is a Si-based semiconductor chip,
The semiconductor device according to claim 1, wherein the alloy layer is a SiCu alloy layer.
前記接合材は、Pb系接合材である、請求項1〜9のいずれか一項に記載の半導体装置。   The semiconductor device according to claim 1, wherein the bonding material is a Pb-based bonding material. Cu系接続対象物と、
前記Cu系接続対象物上に配置されたSi系半導体チップとを含み、
前記半導体チップは、前記半導体チップの裏面側から順に配置されたSiCu合金層およびPb系接合材のみを介して前記Cu系接続対象物に接続されている、半導体装置。
Cu-based connection object;
Si-based semiconductor chip disposed on the Cu-based connection object,
The semiconductor device, wherein the semiconductor chip is connected to the Cu-based connection object only through a SiCu alloy layer and a Pb-based bonding material arranged in order from the back side of the semiconductor chip.
半導体チップを金属製の接合材を介して金属製の接続対象物に接続する工程と、
少なくとも前記接合材が溶融する温度で前記半導体チップを加熱することにより、前記半導体チップの裏面に、前記接続対象物の金属材料および前記半導体チップの半導体材料を含む合金層を成長させる工程とを含む、半導体装置の製造方法。
Connecting a semiconductor chip to a metal connection object via a metal bonding material;
Growing the alloy layer containing the metal material of the connection object and the semiconductor material of the semiconductor chip on the back surface of the semiconductor chip by heating the semiconductor chip at a temperature at which the bonding material melts at least A method for manufacturing a semiconductor device.
前記半導体チップと一体を成し、かつ、前記半導体チップの裏面全域を形成するように前記合金層を成長させる、請求項12に記載の半導体装置の製造方法。   The method for manufacturing a semiconductor device according to claim 12, wherein the alloy layer is grown so as to be integrated with the semiconductor chip and to form the entire back surface of the semiconductor chip. 脱酸素雰囲気中で前記半導体チップを加熱し、前記合金層を成長させる、請求項12または13に記載の半導体装置の製造方法。   14. The method of manufacturing a semiconductor device according to claim 12, wherein the semiconductor chip is heated in a deoxygenated atmosphere to grow the alloy layer. 窒素ガス雰囲気中で前記半導体チップを加熱し、前記合金層を成長させる、請求項12〜14のいずれか一項に記載の半導体装置の製造方法。   The method for manufacturing a semiconductor device according to claim 12, wherein the semiconductor chip is heated in a nitrogen gas atmosphere to grow the alloy layer.
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