JP6495698B2 - 半導体装置、電子部品、及び電子機器 - Google Patents
半導体装置、電子部品、及び電子機器 Download PDFInfo
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- JP6495698B2 JP6495698B2 JP2015051677A JP2015051677A JP6495698B2 JP 6495698 B2 JP6495698 B2 JP 6495698B2 JP 2015051677 A JP2015051677 A JP 2015051677A JP 2015051677 A JP2015051677 A JP 2015051677A JP 6495698 B2 JP6495698 B2 JP 6495698B2
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Classifications
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- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
- G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
- G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
- G11C11/419—Read-write [R-W] circuits
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- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
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- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
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- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
- G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
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- G—PHYSICS
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- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
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- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
- G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
- G11C11/414—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the bipolar type
- G11C11/416—Read-write [R-W] circuits
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- G—PHYSICS
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- G11C14/00—Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down
- G11C14/0054—Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down in which the volatile element is a SRAM cell
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- G—PHYSICS
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- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
- G11C5/147—Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops
Landscapes
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Description
本実施の形態では、半導体装置のブロック図、及びパワーゲーティング(Power Gating:以下PGと略記する)時における各回路の動作について説明する。
図1は、半導体装置の構成の一例を示すブロック図である。
次いで、第1乃至第3のパワーゲーティング制御信号による第1乃至第3の状態の遷移について、図2を用いて説明する。また、図3乃至5では、第1乃至第3の状態におけるキャッシュ100の状態、及びバックアップ、及びリカバリー時において第1乃至第3のパワーゲーティング制御信号のシーケンスについて説明する。
本実施の形態では、図1で示したブロック図の構成について、より具体的な構成を示し説明する。また本実施の形態では、メモリセルの具体例、OSトランジスタについて説明する。
図6は、図1に示す半導体装置10の構成を、さらに具体例したブロック図である。なお本実施の形態では、上記実施の形態1での説明と重複する構成の説明は省略し、前述の説明を援用するものとする。
次いで図1で示したメモリセルの具体例について説明する。
メモリセルMCの構成で用いるOSトランジスタは、Siトランジスタよりも低いオフ電流が得られるトランジスタである。
本実施の形態では、上記実施の形態で説明したオフ電流の低いトランジスタの半導体層に用いることのできる酸化物半導体層について説明する。
本実施の形態では、開示する発明の一態様に係る半導体装置が有する記憶装置に用いられるトランジスタの断面構造の一例について、図8乃至10を参照して説明する。本実施の形態で示すトランジスタの断面構造では、上記実施の形態2で説明したメモリセルの回路が有するトランジスタM1乃至M6と、トランジスタOM1、OM2と、容量素子Cp1、Cp2と、各配線とについて図示する。
上記実施の形態で開示された、導電層や半導体層はスパッタ法により形成することができるが、他の方法、例えば、熱CVD法により形成してもよい。熱CVD法の例としてMOCVD(Metal Organic Chemical Vapor Deposition)法やALD(Atomic Layer Deposition)法を使っても良い。
本実施の形態では、上述の実施の形態で説明した記憶装置を電子部品に適用する例、及び該電子部品を具備する電子機器に適用する例について、図15、図16を用いて説明する。
C2 状態
C3 状態
C4 状態
C5 状態
Cp1 容量素子
Cp2 容量素子
M1 トランジスタ
M6 トランジスタ
OM1 トランジスタ
OM2 トランジスタ
Q1 ノード
SN1 ノード
SN2 ノード
SW1 パワースイッチ
SW2 パワースイッチ
SW3 パワースイッチ
Tr1 トランジスタ
Tr2 トランジスタ
10 半導体装置
10A 半導体装置
100 キャッシュ
110 メモリセルアレイ
111 SRAM
112 不揮発性記憶部
120 周辺回路
121 ローデコーダ
122 ロードライバー
123 カラムデコーダ
124 カラムドライバー
125 ドライバー制御論理回路
126 出力ドライバー
130 バックアップ/リカバリー駆動回路
150 パワーマネジメントユニット
160 CPU
170 入出力インターフェース
180 電源電圧供給回路
190 バスインターフェース
210 電子銃室
212 光学系
214 試料室
216 光学系
218 カメラ
220 観察室
222 フィルム室
224 電子
228 物質
229 蛍光板
311 層
312 層
313 層
314 層
400 半導体基板
402 素子分離用絶縁膜
410 ゲート絶縁層
412 ゲート電極
413 ゲート電極
414 ゲート電極
415 ゲート電極
416 層間絶縁層
418 配線層
420 配線層
422 導電層
423 配線層
424 層間絶縁層
426 導電層
427 配線層
428 層間絶縁層
429 配線層
430 配線層
431 配線層
432 配線層
433 導電層
434 配線層
436 配線層
438 配線層
440 配線層
442 層間絶縁層
444 導電層
446 配線層
448 層間絶縁層
450 ゲート絶縁層
452 半導体層
453 半導体層
454 配線層
456 ゲート電極
458 層間絶縁層
460 導電層
462 導電層
464 絶縁層
466 導電層
467 導電層
468 導電層
472 層間絶縁層
474 配線層
476 配線層
477 配線層
478 層間絶縁層
480 層間絶縁層
700 電子部品
701 リード
702 プリント基板
703 回路部
704 半導体装置
821 配線層
901 筐体
902 筐体
903a 表示部
903b 表示部
904 選択ボタン
905 キーボード
910 電子書籍
911 筐体
912 筐体
913 表示部
914 表示部
915 軸部
916 電源
917 操作キー
918 スピーカー
920 テレビジョン装置
921 筐体
922 表示部
923 スタンド
924 リモコン操作機
930 本体
931 表示部
932 スピーカー
933 マイク
934 操作ボタン
941 本体
942 表示部
943 操作スイッチ
Claims (6)
- メモリセルと、駆動制御回路と、データ制御回路と、第1乃至第3のパワースイッチと、を有する記憶装置と、電源電圧制御回路と、電源電圧生成回路と、を有する半導体装置であって、
前記メモリセルは、前記駆動制御回路の制御によって、データの書き込み及び読み出しが制御される機能を有し、
前記メモリセルは、前記データ制御回路の制御によって、書き込まれたデータを不揮発性の記憶部に退避及び復帰させる機能を有し、
前記電源電圧制御回路は、前記第1乃至第3のパワースイッチのオンまたはオフを制御することができる機能を有し、
前記電源電圧生成回路は、基準電圧を基に、第1乃至第3の電源電圧を生成することができる機能を有し、
前記第1のパワースイッチは、前記メモリセルに前記第1の電源電圧を与えることができる機能を有し、
前記第2のパワースイッチは、前記駆動制御回路に前記第2の電源電圧を与えることができる機能を有し、
前記第3のパワースイッチは、前記データ制御回路に前記第3の電源電圧を与えることができる機能を有し、
前記電源電圧制御回路は、前記第1のパワースイッチをオフにし、前記第2及び第3のパワースイッチをオンにする第1の状態と、前記第1乃至第3のパワースイッチをオフにする第2の状態と、前記第1乃至第3の電源電圧の生成を停止する第3の状態とが順に切り替えることができる機能を有し、
前記記憶装置へのアクセスがない第1の期間を超えると、前記第1の状態から前記第2の状態への切り替えが行われ、
前記記憶装置へのアクセスがない第2の期間を超えると、前記第2の状態から前記第3の状態への切り替えが行われ、
前記第2の期間は、前記第1の期間よりも長いことを特徴とする半導体装置。 - 請求項1において、
前記メモリセルは、SRAMと、チャネル領域に酸化物半導体を有する第1のトランジスタと、容量素子とを有し、
前記第1のトランジスタは、前記データ制御回路によって導通状態が制御される機能を有することを特徴とする半導体装置。 - 請求項2において、
前記SRAMは、チャネル領域にシリコンを有する第2のトランジスタを有することを特徴とする半導体装置。 - 請求項3において、
前記第1のトランジスタのチャネル領域と、前記第2のトランジスタのチャネル領域とは、互いに重なる領域を有することを特徴とする半導体装置。 - 請求項1乃至4のいずれか一に記載の前記記憶装置と、前記記憶装置に電気的に接続されたリードと、を有することを特徴とする電子部品。
- 請求項5に記載の電子部品と、表示装置と、を有することを特徴とする電子機器。
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US9852787B2 (en) | 2017-12-26 |
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US20150269977A1 (en) | 2015-09-24 |
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