JP6357231B2 - 化学的研磨平坦化の方法 - Google Patents
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31051—Planarisation of the insulating layers
- H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
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- H01L21/31056—Planarisation of the insulating layers involving a dielectric removal step the removal being a chemical etching step, e.g. dry etching the removal being a selective chemical etching step, e.g. selective dry etching through a mask
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- G03F7/004—Photosensitive materials
- G03F7/09—Photosensitive materials characterised by structural details, e.g. supports, auxiliary layers
- G03F7/094—Multilayer resist systems, e.g. planarising layers
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- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
- H01L21/0274—Photolithographic processes
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/30604—Chemical etching
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/32—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers using masks
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/32115—Planarisation
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Description
Claims (20)
- 基板を平坦化する方法であって、
第1の微細加工構造及び第2の微細加工構造を有する基板を受け取る工程であって、該第1の微細加工構造及び該第2の微細加工構造が前記基板の上部を横切る方向において平坦でない形状を規定するように、該第1の微細加工構造は該第2の微細加工構造に対して高さが異なる、受け取る工程と、
前記基板に平坦化膜を付着させ、該平坦化膜が前記基板の上部上に第一平坦面を生み出す工程であって、該平坦化膜は溶解性が可変な材料を含む工程と、
溶解性変更作用剤を前記平坦化膜の第一平坦面に付着させる工程と、
前記溶解性変更作用剤が前記平坦化膜の頂部の溶解性を変更するように、前記溶解性変更作用剤を活性化する工程であって、前記平坦化膜の頂部は、前記平坦化膜の第一平坦面から前記平坦化膜内の所定の深さにまで垂直方向に延びる厚さを有する工程と、
前記平坦化膜の頂部を除去して、目標平坦面を有する前記基板を生じさせる工程であって、該目標平坦面は前記基板の面と前記平坦化膜の面とを有する、生じさせる工程と、
前記頂部の除去の後、前記目標平坦面を通じて前記基板の第1の微細加工構造及び第2の微細加工構造の両方にフィーチャをエッチングする工程と、を含む方法。 - 前記溶解性変更作用剤を活性化する工程は、前記溶解性変更作用剤が前記所定の深さにまで前記平坦化膜に拡散し、前記平坦化膜の頂部の溶解性を変更するように、前記溶解性変更作用剤を加熱する工程を含む、請求項1に記載の方法。
- 前記溶解性変更作用剤を加熱する工程は、前記溶解性変更作用剤の拡散が、概ね前記深さのところで停止するように、加熱パラメータを制御する工程を含む、請求項2に記載の方法。
- 加熱する工程は、前記基板を約80℃と100℃との間の温度に加熱することを含む、請求項2に記載の方法。
- 前記平坦化膜を付着させる工程は、現像可能な反射防止コーティングを付着させる工程を含む、請求項1に記載の方法。
- 前記現像可能な反射防止コーティングは、シリコンを含む、請求項5に記載の方法。
- 前記溶解性変更作用剤を付着させる工程は、蒸発曝露付着を用いることを含む、請求項1に記載の方法。
- 前記溶解性変更作用剤を付着させる工程は、液体付着を含む、請求項1に記載の方法。
- 前記溶解性変更作用剤は酸である、請求項1に記載の方法。
- 前記溶解性変更作用剤を付着させる工程は、光酸発生剤を用いる、請求項9に記載の方法。
- 前記溶解性変更作用剤は、熱で活性化する酸発生剤である、請求項1に記載の方法。
- 前記溶解性変更作用剤はベースであり、前記平坦化膜はポジティブトーンレジストである、請求項1に記載の方法。
- 前記平坦化膜の頂部を除去する工程は、前記平坦化膜の頂部を溶解する化学デベロッパを用いることを含む、請求項1に記載の方法。
- 前記所定の深さは、前記第一平坦面から、前記基板の所与の構造であって、前記基板の他の構造よりも高い所与の構造までの距離と実質的に等しい、請求項1に記載の方法。
- 前記平坦化膜がこれ以上溶解性変更作用剤と反応しないように、前記基板を熱処理する工程をさらに含む、請求項1に記載の方法。
- フォトリソグラフィーを介して、前記目標平坦面にパターンが形成されたフォトレジストの層を形成する工程をさらに含む、請求項1に記載の方法。
- 前記フィーチャのエッチングは、前記パターンが形成されたフォトレジストの層をマスクとして用いる、請求項16に記載の方法。
- 基板を平坦化する方法であって、
第1の微細加工構造及び第2の微細加工構造を有する基板を受け取る工程であって、該第1の微細加工構造及び該第2の微細加工構造が前記基板の上部を横切る方向において平坦でない形状を規定するように、該第1の微細加工構造は該第2の微細加工構造に対して高さが異なる、受け取る工程と、
前記基板に平坦化膜を付着させ、該平坦化膜が前記基板の上部上に第一平坦面を生み出す工程であって、該平坦化膜は、溶解性が可変な材料を含む工程と、
溶解性変更作用剤を前記平坦化膜の第一平坦面に付着させる工程であって、該溶解性変更作用剤は所定の深さにまで前記平坦化膜の頂部に拡散し、前記平坦化膜の頂部の溶解性を変更し、前記平坦化膜の頂部は、前記平坦化膜の第一平坦面から前記平坦化膜内の該所定の深さにまで垂直方向に延びる厚さを有する工程と、
前記平坦化膜の頂部を除去して、目標平坦面を有する前記基板を生じさせる工程であって、該目標平坦面は前記基板の面と前記平坦化膜の面とを有する、生じさせる工程と、
前記頂部の除去の後、前記目標平坦面を通じて前記基板の第1の微細加工構造及び第2の微細加工構造の両方にフィーチャをエッチングする工程と、を含む方法。 - 前記溶解性変更作用剤は、前記第一平坦面に付着した前記溶解性変更作用剤の量に基づいた前記所定の深さにまで前記平坦化膜の頂部に拡散する、請求項18に記載の方法。
- 前記溶解性変更作用剤は、前記第一平坦面に前記溶解性変更作用剤が留まる時間に基づいた前記所定の深さにまで前記平坦化膜の頂部に拡散する、請求項19に記載の方法。
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US201361901768P | 2013-11-08 | 2013-11-08 | |
US61/901768 | 2013-11-08 | ||
PCT/US2014/063886 WO2015069646A1 (en) | 2013-11-08 | 2014-11-04 | Method for chemical polishing and planarization |
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JP (1) | JP6357231B2 (ja) |
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US9547743B2 (en) * | 2015-02-25 | 2017-01-17 | Kabushiki Kaisha Toshiba | Manufacturing method for a semiconductor device, pattern generating method and nontransitory computer readable medium storing a pattern generating program |
US10096528B2 (en) * | 2016-05-13 | 2018-10-09 | Tokyo Electron Limited | Critical dimension control by use of a photo agent |
KR20230074638A (ko) | 2018-04-16 | 2023-05-30 | 어플라이드 머티어리얼스, 인코포레이티드 | 임시 및 영구 접합을 사용하는 다중 적층 광학 요소들 |
US11393694B2 (en) * | 2018-11-13 | 2022-07-19 | Tokyo Electron Limited | Method for planarization of organic films |
JP7312645B2 (ja) * | 2019-08-26 | 2023-07-21 | 東京エレクトロン株式会社 | 基板処理方法、基板処理装置、及び記憶媒体 |
US20210294148A1 (en) * | 2020-03-17 | 2021-09-23 | Tokyo Electron Limited | Planarizing Organic Films |
JP2022099428A (ja) * | 2020-12-23 | 2022-07-05 | メルク パテント ゲゼルシャフト ミット ベシュレンクテル ハフツング | 犠牲層の上部を除去する方法、それに用いられる犠牲溶液および酸性水溶液 |
WO2023028236A1 (en) * | 2021-08-25 | 2023-03-02 | Geminatio, Inc. | In-resist process for high density contact formation |
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KR100319621B1 (ko) * | 1999-05-14 | 2002-01-05 | 김영환 | 혼성신호 반도체 소자의 제조방법 |
DE10240748B4 (de) | 2002-08-29 | 2010-04-01 | Qimonda Ag | Verfahren zur Planarisierung einer Halbleiterprobe |
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KR101668505B1 (ko) | 2009-02-19 | 2016-10-28 | 브레우어 사이언스 인코포레이션 | 산-민감성, 현상제-용해성 바닥부 반사방지 코팅 |
US8883407B2 (en) * | 2009-06-12 | 2014-11-11 | Rohm And Haas Electronic Materials Llc | Coating compositions suitable for use with an overcoated photoresist |
US8507191B2 (en) * | 2011-01-07 | 2013-08-13 | Micron Technology, Inc. | Methods of forming a patterned, silicon-enriched developable antireflective material and semiconductor device structures including the same |
KR20130015429A (ko) * | 2011-08-03 | 2013-02-14 | 삼성전자주식회사 | 에치-백 공정을 이용한 패턴 형성 방법 |
US8703004B2 (en) * | 2011-11-14 | 2014-04-22 | Kabushiki Kaisha Toshiba | Method for chemical planarization and chemical planarization apparatus |
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