JP6343455B2 - Semiconductor package structure - Google Patents

Semiconductor package structure Download PDF

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Publication number
JP6343455B2
JP6343455B2 JP2014020902A JP2014020902A JP6343455B2 JP 6343455 B2 JP6343455 B2 JP 6343455B2 JP 2014020902 A JP2014020902 A JP 2014020902A JP 2014020902 A JP2014020902 A JP 2014020902A JP 6343455 B2 JP6343455 B2 JP 6343455B2
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metal plate
semiconductor package
package structure
reinforcing member
circuit board
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JP2015149371A (en
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恵子 上之
恵子 上之
吉成　英人
英人 吉成
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Hitachi Astemo Ltd
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Hitachi Automotive Systems Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49111—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]

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Description

本発明は、はんだ等により回路基板に実装する表面実装用の金属板を供えた半導体パッケージの構造に関する。
The present invention relates to a structure of a semiconductor package provided with a metal plate for surface mounting mounted on a circuit board by solder or the like.

本技術分野の背景技術として、特開２０１３−１６８３７号公報（特許文献１）がある。この公報には、「シリコンチップ３はドレインリードを構成するリード４と一体に形成されたダイパッド４Ｄの上に搭載されており、その主面にはソースパッド７とゲートパッド８が形成されている。」と記載されている。
As background art of this technical field, there is JP 2013-16837 A (Patent Document 1). In this publication, “the silicon chip 3 is mounted on a die pad 4D formed integrally with a lead 4 constituting a drain lead, and a source pad 7 and a gate pad 8 are formed on the main surface thereof. . "

特開２０１３−１６８３７号公報JP 2013-16837 A

近年、回路基板に実装する電子部品の小型化が急速に進んでいる。しかし、電子部品を実装したコントロールユニットでは、電子部品の発熱や温度変化等の使用環境に起因した不良が生じることが懸念される。温度の変化が存在する環境では、実装部品同士の線膨張係数差に起因した電子装置の変形により基板と電子部品との間の接合不良や配線基板内の断線が生じやすくなる。このため、実装構造や材料の選定による電子部品および電子装置の変形の低減が重要である。
In recent years, electronic components mounted on circuit boards have been rapidly downsized. However, there is a concern that in the control unit on which the electronic component is mounted, a defect due to the usage environment such as heat generation or temperature change of the electronic component may occur. In an environment where there is a change in temperature, the deformation of the electronic device due to the difference in the linear expansion coefficient between the mounted components tends to cause poor bonding between the substrate and the electronic component and disconnection in the wiring substrate. For this reason, it is important to reduce deformation of electronic components and electronic devices by selecting a mounting structure and materials.

ダイオードやＭＯＳＦＥＴは代表的な電子部品であり、車載用コントロールユニットの回路基板にも搭載されている。   Diodes and MOSFETs are typical electronic components, and are also mounted on a circuit board of an in-vehicle control unit.

前記特許文献１は、パワーＭＯＳＦＥＴの構造に関する発明である。特許文献１をはじめ、従来技術では、大きさの異なる金属板を複数備え、それぞれの金属板にはんだ接合用の端子が形成され、樹脂封止されたパッケージとなっている。各金属板に形成された端子は、相対する辺に形成されている。大きさの異なる金属板および端子が相対する辺に形成されているため、パッケージ全体としては剛性に偏りが存在する。このため、回路基板にはんだ実装後、温度変化によってパッケージ全体に反りの変形が生じた場合、サイズが最も小さい金属板の端子のはんだ接合部に応力が集中し易い。この結果、サイズが最も小さい金属板の端子のはんだ接続信頼性が懸念される。特に車載用コントロールユニット等の高信頼が要求される電子装置においては、従来技術でははんだ接続寿命の要求値を満足できない場合が多く存在し、はんだ接続信頼性を向上させることが課題である。
Patent Document 1 is an invention relating to the structure of a power MOSFET. In the prior art including Patent Document 1, a plurality of metal plates having different sizes are provided, solder bonding terminals are formed on each metal plate, and the package is resin-sealed. Terminals formed on each metal plate are formed on opposite sides. Since the metal plates and terminals having different sizes are formed on opposite sides, the rigidity of the entire package is uneven. For this reason, after the solder is mounted on the circuit board, when warping deformation occurs in the entire package due to a temperature change, stress tends to concentrate on the solder joint portion of the terminal of the metal plate having the smallest size. As a result, there is a concern about the solder connection reliability of the terminal of the metal plate having the smallest size. Particularly in an electronic device such as an in-vehicle control unit that requires high reliability, there are many cases where the required value of the solder connection life cannot be satisfied by the conventional technology, and it is a problem to improve the solder connection reliability.

本願は上記課題を解決するための発明であり、その概要を説明する。
「辺１側に金属板１を備え、辺１に相対する辺２側に金属板２および金属板３を備え、該金属板１に半導体部品を搭載し、該金属板２および該金属板３は辺２に端子を備え、封止樹脂によりモールドされた半導体パッケージ構造において、
金属板１は前記辺２に補強部材を備え、
金属板１、金属板２および金属板３にて接合材料により回路基板に接合されることを特徴とする半導体パッケージ構造。」
The present application is an invention for solving the above problems, and an outline thereof will be described.
“A metal plate 1 is provided on the side 1 side, a metal plate 2 and a metal plate 3 are provided on the side 2 opposite to the side 1, a semiconductor component is mounted on the metal plate 1, and the metal plate 2 and the metal plate 3. Is a semiconductor package structure having a terminal on side 2 and molded with a sealing resin.
The metal plate 1 includes a reinforcing member on the side 2,
A semiconductor package structure, wherein the metal plate 1, the metal plate 2, and the metal plate 3 are bonded to a circuit board by a bonding material. "

本発明によれば、半導体パッケージ全体における剛性の偏りを低減することが可能である。この結果、回路基板にはんだ実装後、環境温度の変化に起因した変形が生じても、一部のはんだ接合部に応力が集中することを防ぎ、はんだ接続寿命の信頼性を向上することが可能となる。   According to the present invention, it is possible to reduce the stiffness deviation in the entire semiconductor package. As a result, even after deformation due to environmental temperature changes after solder mounting on the circuit board, it is possible to prevent stress from concentrating on some solder joints and improve the reliability of the solder connection life It becomes.

上記した以外の課題、構成及び効果は、以下の実施形態の説明により明らかにされる。
Problems, configurations, and effects other than those described above will be clarified by the following description of embodiments.

本発明の半導体パッケージ構造を表す構造１００の下面図である1 is a bottom view of a structure 100 representing a semiconductor package structure of the present invention. 本発明の半導体パッケージ構造を表す構造１００の内部構造である。3 is an internal structure of structure 100 representing the semiconductor package structure of the present invention. 本発明の半導体パッケージ構造を表す構造１００の正面図である。1 is a front view of a structure 100 representing a semiconductor package structure of the present invention. 本発明の半導体パッケージ構造を表す構造１００の断面図（図１のＸ−Ｘ’断面図）である。It is sectional drawing (X-X 'sectional drawing of FIG. 1) of the structure 100 showing the semiconductor package structure of this invention. 半導体パッケージ構造１００を実装する回路基板のはんだ付け部である。This is a soldering portion of a circuit board on which the semiconductor package structure 100 is mounted. 図５のはんだ付け部と半導体パッケージ構造１００の重ね合わせ図である。FIG. 6 is a superimposed view of the soldered portion of FIG. 5 and the semiconductor package structure 100. 半導体パッケージ構造１００を実装する回路基板のはんだ付け部である。This is a soldering portion of a circuit board on which the semiconductor package structure 100 is mounted. 図７のはんだ付け部と半導体パッケージ構造１００の重ね合わせ図である。FIG. 8 is a superimposed view of the soldered portion of FIG. 7 and the semiconductor package structure 100. 本発明の半導体パッケージ構造を表す構造２００の下面図である。It is a bottom view of the structure 200 showing the semiconductor package structure of this invention. 本発明の半導体パッケージ構造を表す構造２００の内部構造である。3 is an internal structure of structure 200 representing the semiconductor package structure of the present invention. 本発明の半導体パッケージ構造を表す構造２００の正面図である。It is a front view of the structure 200 showing the semiconductor package structure of this invention. 本発明の半導体パッケージ構造を表す構造２００の断面図（図９のＸ−Ｘ’断面図）である。It is sectional drawing (X-X 'sectional drawing of FIG. 9) of the structure 200 showing the semiconductor package structure of this invention. 本発明の半導体パッケージ構造を表す構造３００の下面図である。FIG. 6 is a bottom view of a structure 300 representing the semiconductor package structure of the present invention. 本発明の半導体パッケージ構造を表す構造３００の正面図である。1 is a front view of a structure 300 representing a semiconductor package structure of the present invention. FIG. 本発明の半導体パッケージ構造を表す構造４００の下面図である。6 is a bottom view of a structure 400 representing the semiconductor package structure of the present invention. FIG. 本発明の半導体パッケージ構造を表す構造４００の正面図である。1 is a front view of a structure 400 representing a semiconductor package structure of the present invention. FIG. 従来技術の半導体パッケージ構造を表す下面図である。It is a bottom view showing the semiconductor package structure of a prior art. 従来技術の半導体パッケージ構造を表す正面図である。It is a front view showing the semiconductor package structure of a prior art. 従来技術の半導体パッケージ構造を表す断面図（図１７のＸ−Ｘ’断面図）である。It is sectional drawing (X-X 'sectional drawing of FIG. 17) showing the semiconductor package structure of a prior art.

以下、実施例を図面を用いて説明する。   Hereinafter, examples will be described with reference to the drawings.

実施例１では、本発明を示す代表的な構造について説明する。

図１は、実施例１の半導体パッケージ構造を表す構造１００の下面図である。また、図２は構造１００の内部構造を表し、図３は構造１００の正面図、図４は構造１００の断面図であり図１のＸ−Ｘ’の断面を示す。
構造１００は、辺１側に金属板１０１、辺２側に金属板１０２および金属板１０３の３枚の金属板を有する。金属板１０１は辺１側に端子１０５を形成し、辺１と相対する辺２側に補強部材１０６を形成している。また、辺２側には補強部材１０６にはさまれる形で、金属板２の端子１０８および金属１０３の端子１０９が形成されている。金属板１０１には半導体チップ１１０が搭載され、端子１０８および１０９と金属ワイヤ１１１にて配線されている。これらのすべての部材は樹脂１１２により封止され、端子１０５,１０８,１０９および補強部材のそれぞれの一部は封止樹脂１１２の外部に露出している。本半導体パッケージ構造１００は、露出している端子および補強部材にてはんだ合金により外部基板（回路基板）と接続される。本半導体パッケージ１００は例えばＭＯＳＦＥＴ、あるいはダイオードのパッケージ構造であり、車載用コントロールユニットの回路基板に実装される。
In Example 1, a typical structure showing the present invention will be described.

FIG. 1 is a bottom view of a structure 100 representing the semiconductor package structure of the first embodiment. 2 shows the internal structure of the structure 100, FIG. 3 is a front view of the structure 100, and FIG. 4 is a cross-sectional view of the structure 100, showing a cross section taken along line XX ′ of FIG.
The structure 100 has three metal plates, a metal plate 101 on the side 1 side and a metal plate 102 and a metal plate 103 on the side 2 side. The metal plate 101 has a terminal 105 on the side 1 side and a reinforcing member 106 on the side 2 opposite to the side 1. On the side 2 side, a terminal 108 of the metal plate 2 and a terminal 109 of the metal 103 are formed so as to be sandwiched between the reinforcing members 106. A semiconductor chip 110 is mounted on the metal plate 101 and wired with terminals 108 and 109 and metal wires 111. All these members are sealed with the resin 112, and the terminals 105, 108, 109 and a part of the reinforcing member are exposed to the outside of the sealing resin 112. The semiconductor package structure 100 is connected to an external substrate (circuit board) by a solder alloy with exposed terminals and reinforcing members. The semiconductor package 100 has a package structure of, for example, a MOSFET or a diode, and is mounted on a circuit board of an in-vehicle control unit.

本実施例によれば、構造１００は、辺１側に設置された金属板１に、辺１と相対する辺２側に補強部材が形成され、さらにそれらの補強部材は端子１０８および１０９をはさみこむ形で形成されていることにより、構造全体における剛性の偏りが低減する。これにより使用環境温度の変化に伴い半導体パッケージに変形が生じた場合、構造全体の変形の偏りを防ぎ、端子１０８および１０９のはんだ接合部への応力集中を低減し、はんだ接続寿命を長寿命化することが可能となる。本実施例は、前記効果により、車載用コントロールユニット等の使用環境温度の変化にも耐え得るはんだ接続信頼性に優れた半導体パッケージ構造を実現する。
According to this embodiment, in the structure 100, the metal plate 1 installed on the side 1 side is formed with the reinforcing members on the side 2 opposite to the side 1, and these reinforcing members sandwich the terminals 108 and 109. By being formed in a shape, rigidity deviation in the entire structure is reduced. As a result, when the semiconductor package is deformed due to changes in the operating environment temperature, the deformation of the entire structure is prevented, stress concentration at the solder joints of the terminals 108 and 109 is reduced, and the solder connection life is extended. It becomes possible to do. The present embodiment realizes a semiconductor package structure with excellent solder connection reliability that can withstand changes in the operating environment temperature of an in-vehicle control unit or the like due to the above effects.

本実施例では、半導体パッケージ構造１００を車載用コントロールユニットの回路基板に実装する際のはんだ付け部の形状について説明する。
In the present embodiment, the shape of the soldering portion when the semiconductor package structure 100 is mounted on the circuit board of the in-vehicle control unit will be described.

図５は半導体パッケージ構造１００を実装する回路基板のはんだ付け部の形状を示す。回路基板には放熱用のスルーホール１１３およびはんだ付け部１１４を備える。スルーホール１１３の内壁およびはんだ付け部１１４は金属材料であり、例えば銅である。また、図６は回路基板はんだ付け部と構造１００との重ね合わせ図である。スルーホール１１３は半導体チップを搭載した金属板の下面に位置し、半導体チップからの発熱を放熱する役目を果たす。構造１００の端子および補強部材ははんだ付け部１１４においてはんだ合金によって回路基板と接合される。図７は図５同様、半導体パッケージ構造１００を実装する回路基板のはんだ付け部の形状を、図８は半導体パッケージ構造１００との重ね合わせ図を示す。
FIG. 5 shows the shape of the soldering portion of the circuit board on which the semiconductor package structure 100 is mounted. The circuit board includes a through hole 113 for heat dissipation and a soldering portion 114. The inner wall of the through-hole 113 and the soldering part 114 are metal materials, for example, copper. FIG. 6 is a superimposed view of the circuit board soldering portion and the structure 100. The through hole 113 is located on the lower surface of the metal plate on which the semiconductor chip is mounted, and serves to radiate heat generated from the semiconductor chip. The terminals and reinforcement members of structure 100 are joined to the circuit board by solder alloy at soldered portions 114. 7 shows the shape of the soldered portion of the circuit board on which the semiconductor package structure 100 is mounted, as in FIG. 5, and FIG.

本実施例によれば、半導体パッケージ構造１００を実装する回路基板において、半導体パッケージ構造１００の金属板１０１の下面に放熱用のスルーホール１１３を備えていることにより、半導体チップからの発熱を放熱することが可能となる。これにより、車載用の過酷な使用環境下でも使用可能な、はんだ接続信頼性に優れかつ放熱性に優れた半導体パッケージ構造およびコントロールユニットを実現する。
According to this embodiment, in the circuit board on which the semiconductor package structure 100 is mounted, the heat radiation from the semiconductor chip is radiated by providing the heat dissipation through hole 113 on the lower surface of the metal plate 101 of the semiconductor package structure 100. It becomes possible. As a result, a semiconductor package structure and a control unit that have excellent solder connection reliability and excellent heat dissipation, which can be used even in a harsh usage environment for vehicles, are realized.

本実施例では、使用環境温度の変化に伴うパッケージ構造全体の変形およびはんだ接合部への応力集中をさらに低減し、加えて封止樹脂とその他の部材との密着性を向上させる構造について説明する。

図９は本発明の半導体パッケージ構造２００の下面図である。また、図１０は構造２００の内部構造を表し、図１１は構造２００の正面図、図１２は構造２００の断面図であり図９のＸ−Ｘ’の断面を示す。
構造２００の基本構造は構造１００と同じであり、金属板１０１，１０２，１０３の３枚を有し、金属板１０１は辺１側に金属板１０２および１０３は辺２側に設置されている。金属板１０１は構造１００と同様に辺２側に端子１０８および１０９をはさみこむ形で補強部材１０７を有し、さらに本構造２００では、端子１０８と１０９の間にも補強部材１０７を有している。また、図１２に示すように、補強部材１０７は封止樹脂内で外部基板（回路基板）との接合面に対して垂直な方向に曲げられた形となっている。
In this example, a structure that further reduces the deformation of the entire package structure and the stress concentration on the solder joint accompanying changes in the operating environment temperature, and additionally improves the adhesion between the sealing resin and other members will be described. .

FIG. 9 is a bottom view of the semiconductor package structure 200 of the present invention. 10 shows the internal structure of the structure 200, FIG. 11 is a front view of the structure 200, and FIG. 12 is a cross-sectional view of the structure 200, showing a cross section taken along line XX ′ of FIG.
The basic structure of the structure 200 is the same as that of the structure 100, and has three metal plates 101, 102, and 103. The metal plate 101 is installed on the side 1 side and the metal plates 102 and 103 are installed on the side 2 side. Similar to the structure 100, the metal plate 101 has a reinforcing member 107 in such a manner that the terminals 108 and 109 are sandwiched between the sides 2, and the structure 200 also has a reinforcing member 107 between the terminals 108 and 109. . Further, as shown in FIG. 12, the reinforcing member 107 is bent in a direction perpendicular to the joint surface with the external substrate (circuit board) in the sealing resin.

本実施例によれば、補強部材１０７を端子１０８と１０９の間にも形成することにより、さらに半導体パッケージ全体における剛性の偏りを低減し、変形の偏りを防ぐことが可能となる。この結果、端子１０８および１０９への応力集中は構造１００以上に低減され、さらにはんだ接続信頼を向上させることが可能となる。また、封止樹脂内で補強部材１０７が曲げられていることにより、封止樹脂と金属板との密着性を向上させることが可能となる。このことは、例えば吸湿した半導体パッケージが高温下に置かれた場合に、部材から発生する水蒸気の圧力によって金属板と封止樹脂との間に剥離等の不具合が生じることを防ぐことを可能とする。
According to the present embodiment, by forming the reinforcing member 107 between the terminals 108 and 109, it is possible to further reduce the rigidity bias in the entire semiconductor package and prevent the deformation bias. As a result, the stress concentration on the terminals 108 and 109 is reduced to the structure 100 or more, and the solder connection reliability can be further improved. Further, since the reinforcing member 107 is bent in the sealing resin, the adhesion between the sealing resin and the metal plate can be improved. This makes it possible to prevent problems such as peeling between the metal plate and the sealing resin due to the pressure of water vapor generated from the member when the semiconductor package that has absorbed moisture is placed at a high temperature, for example. To do.

本実施例では、使用環境温度の変化に伴うパッケージ構造全体の変形およびはんだ接合部への応力集中をさらに低減し、また、放熱性を向上させた構造について説明する。
In the present embodiment, a description will be given of a structure in which the deformation of the entire package structure and the stress concentration on the solder joint portion due to the change in the use environment temperature are further reduced and the heat dissipation is improved.

図１３は本発明の半導体パッケージ構造３００の下面図、図１４は構造３００の正面図である。基本構造は構造１００と同じであるが、構造３００では金属板１０１の面積を、辺１，辺２と隣接する辺の方向へ封止樹脂の外部にまで拡げた構造としている。
FIG. 13 is a bottom view of the semiconductor package structure 300 of the present invention, and FIG. 14 is a front view of the structure 300. Although the basic structure is the same as that of the structure 100, the structure 300 has a structure in which the area of the metal plate 101 is extended to the outside of the sealing resin in the direction of the side adjacent to the sides 1 and 2.

本実施例によれば、金属板１０１の面積を図１３に示すように封止樹脂の外部にまで拡げることにより、半導体パッケージ構造３００の全体における剛性の偏りを低減し、かつ構造３００の全体の剛性を高めることになる。これにより、はんだ接続寿命をさらに長寿命化することが可能となる。
According to the present embodiment, by expanding the area of the metal plate 101 to the outside of the sealing resin as shown in FIG. 13, the rigidity deviation in the entire semiconductor package structure 300 can be reduced, and the entire structure 300 can be reduced. This will increase the rigidity. Thereby, it is possible to further extend the life of the solder connection.

本実施例では、金属板１０１を２枚搭載した半導体パッケージ構造について説明する。
In this embodiment, a semiconductor package structure in which two metal plates 101 are mounted will be described.

図１５は本発明の半導体パッケージ構造４００の下面図、図１６は構造４００の正面図である。本実施例では、半導体チップを搭載した金属板１０１を２枚供え、それぞれの金属板１０１に補強部材を供えた構造としている。
FIG. 15 is a bottom view of the semiconductor package structure 400 of the present invention, and FIG. 16 is a front view of the structure 400. In this embodiment, two metal plates 101 on which semiconductor chips are mounted are provided, and each metal plate 101 is provided with a reinforcing member.

本実施例によれば、半導体チップを複数搭載した構造においても、補強部材を形成することが可能であり、構造１００，２００および３００と同様にはんだ接続信頼性にすぐれた半導体パッケージ構造を実現することが可能となる。
According to the present embodiment, a reinforcing member can be formed even in a structure in which a plurality of semiconductor chips are mounted, and a semiconductor package structure with excellent solder connection reliability is realized as in the structures 100, 200, and 300. It becomes possible.

なお、本発明は上記した実施例に限定されるものではない。例えば、上記した実施例は本発明を分かりやすく説明するために挙げたものであり、必ずしも説明した全ての構成を備えるものではない。また、ある実施例の構成の一部を他の実施例の構成に置き換えることが可能であり、また、ある実施例の構成に他の実施例の構成を加えることも可能である。また、各実施例の構成の一部について、他の構成の追加・削除・置換をすることが可能である。
In addition, this invention is not limited to an above-described Example. For example, the above-described embodiments are given for easy understanding of the present invention, and do not necessarily include all the configurations described. Further, a part of the configuration of one embodiment can be replaced with the configuration of another embodiment, and the configuration of another embodiment can be added to the configuration of one embodiment. Further, it is possible to add, delete, and replace other configurations for a part of the configuration of each embodiment.

１００ 本発明の半導体パッケージ構造
１０１ 金属板１
１０２ 金属板２
１０３ 金属板３
１０４ 辺１
１０５ 金属板１に形成された端子
１０６ 辺２
１０７ 金属板１に形成された補強部材
１０８ 金属板２に形成された端子
１０９ 金属板３に形成された端子
１１０ 半導体チップ
１１１ 金属ワイヤ
１１２ 封止樹脂
１１３ 放熱用スルーホール
１１４ 回路基板のはんだ付け部
２００ 本発明の半導体パッケージ構造
３００ 本発明の半導体パッケージ構造
４００ 本発明の半導体パッケージ構造
５００ 従来技術の半導体パッケージ構造 100 Semiconductor Package Structure 101 of the Present Invention Metal Plate 1
102 Metal plate 2
103 Metal plate 3
104 side 1
105 Terminal 106 formed on metal plate 1 Side 2
107 Reinforcing Member 108 Formed on Metal Plate 1 Terminal 109 Formed on Metal Plate 2 Terminal 110 Formed on Metal Plate 3 Semiconductor Chip 111 Metal Wire 112 Sealing Resin 113 Heat Dissipation Through Hole 114 Circuit Board Soldering Portion 200 Semiconductor Package Structure 300 of the Present Invention Semiconductor Package Structure 400 of the Present Invention Semiconductor Package Structure 500 of the Present Invention Semiconductor Package Structure of the Prior Art

Claims (2)

辺１側に金属板１を備え、辺１に相対する辺２側に金属板２および金属板３を備え、
該金属板１に半導体部品を搭載し、該金属板２および該金属板３は辺２に端子を備え、封止樹脂によりモールドされた半導体パッケージにおいて、
前記金属板１は前記辺２に第一の補強部材及び第二の補強部材を備え、
前記金属板１、前記金属板２および前記金属板３は接合材料により回路基板に接合されるための端子であり、
前記辺２の一端側には前記第一の補強部材が配置され、
前記辺２の他端側には前記第二の補強部材が配置され、
前記第一の補強部材と前記第二の補強部材との間には金属板２および金属板３の端子が挟み込まれるかたちで配置され、前記辺２に形成された金属板１にはさらに第三の補強部材を備え、
前記第三の補強部材は、金属板２の端子と金属板３の端子との間に形成されることを特徴とする半導体パッケージ。 A metal plate 1 is provided on the side 1 side, a metal plate 2 and a metal plate 3 are provided on the side 2 side facing the side 1,
In a semiconductor package in which a semiconductor component is mounted on the metal plate 1, the metal plate 2 and the metal plate 3 are provided with terminals on the side 2 and molded with a sealing resin,
The metal plate 1 includes a first reinforcing member and a second reinforcing member on the side 2;
The metal plate 1, the metal plate 2, and the metal plate 3 are terminals for joining to a circuit board by a joining material,
The first reinforcing member is disposed on one end side of the side 2,
The second reinforcing member is disposed on the other end side of the side 2,
Between the first reinforcing member and the second reinforcing member, terminals of the metal plate 2 and the metal plate 3 are disposed, and the metal plate 1 formed on the side 2 further includes a third member. A reinforcing member
The semiconductor package according to claim 3, wherein the third reinforcing member is formed between a terminal of the metal plate 2 and a terminal of the metal plate 3. 請求項１に記載の前記半導体パッケージと回路基板を用いた車両コントロールユニットにおいて、
前記回路基板には、前記金属板１が相対する領域に１つ以上の放熱用ビアを有していることを特徴とした車載用コントロールユニット。 In the vehicle control unit using the semiconductor package and the circuit board according to claim 1 ,
The vehicle-mounted control unit, wherein the circuit board has one or more heat dissipation vias in a region where the metal plate 1 faces.
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