JP6236260B2 - バンド設計された半導体デバイスおよびその製造方法 - Google Patents
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- 238000004519 manufacturing process Methods 0.000 title claims description 14
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- 238000000034 method Methods 0.000 claims description 38
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- 239000003989 dielectric material Substances 0.000 claims description 12
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 claims description 6
- 230000003628 erosive effect Effects 0.000 claims description 5
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- 239000002243 precursor Substances 0.000 description 5
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Description
基板と、
基板内の凹部(recess)に形成され、かつ当該凹部の上方に延び、埋め込み部と延長部とを有するようにした突出構造とを備え、
少なくとも延長部は、半導体材料であって、前記構造の外縁部での第1の値から第1の値より大きい前記構造の中心部での第2の値に向けてバンドギャップの値が徐々に増加する、逆「V」字状のバンドギャッププロファイルを有する半導体材料を含む、半導体デバイスに関する。
誘電体領域と半導体領域とを含む、パターニングされた基板を設ける工程と、
半導体領域に、基板を露出させる下部領域と、誘電体材料を含む側壁とを有する凹部を形成する工程と、
凹部内で半導体材料をエピタキシャル成長させることにより、凹部に突出構造を形成し、これにより凹部を充填し、かつ過成長させる(overgrow)工程と、
誘電体領域で誘電体材料を浸食する(recess back)ことにより、突出構造の延長部を露出させる工程とを含み、
少なくとも突出構造の延長部は、半導体材料であって、構造外縁部での第1の値から第1の値より大きい構造中心部での第2の値に向けてバンドギャップの値が徐々に増加する、逆「V」字状のバンドギャッププロファイルを有する半導体材料を含む、半導体デバイスの製造方法に関する。
基板と、
基板の上の突出構造とを備え、
突出構造は、半導体材料であって、構造外縁部での第1の値から第1の値より大きい構造中心部での第2の値に向けてバンドギャップの値が徐々に増加する、逆「V」字状のバンドギャッププロファイルを有する半導体材料を含む、半導体デバイスについて開示している。
(a)誘電体領域と半導体領域とを含む、パターニングされた基板を設ける工程と、
(b)半導体領域に、基板を露出させる下部領域と、誘電体材料を含む側壁(サイドウォール)とを有する凹部を形成する工程と、
(c)以下の工程(d)〜(f)を実施することにより、半導体材料であって、構造外縁部での第1の値から第1の値より大きい構造中心部での第2の値に向けてバンドギャップの値が徐々に増加する、逆「V」字状のバンドギャッププロファイルを有する半導体材料を凹部に形成する工程とを含む、半導体装置を製造する方法を開示している。工程(d)〜(f)とは、
(d)凹部内で半導体材料をエピタキシャル成長させることにより、凹部を充填および過成長させる工程、次に、
(e)化学機械研磨を実施して、過成長半導体材料を幾らか除去する工程、
(f)誘電体領域で誘電体材料を浸食する(エッチバックする)ことにより、突出構造の延長部を露出させる工程である。
Claims (13)
- 基板と、
基板内の凹部に形成され、かつ該凹部の上方に延び、埋め込み部と延長部とを有するようにした突出構造とを備え、
少なくとも延長部は、半導体材料であって、突出構造の外縁部での第1の値から、第1の値より大きい突出構造の中心部での第2の値に向けてバンドギャップの値が徐々に増加する、逆V字状のバンドギャッププロファイルを有する半導体材料を含み、
突出構造は、垂直方向に積層された2つ以上の層を含み、
各層は、突出構造の外縁部での第1の値から、第1の値より大きい突出構造の中心部での第2の値に向けてバンドギャップの値が徐々に増加する、逆V字状のバンドギャッププロファイルを有する半導体材料を含む、半導体デバイス。 - 延長部と埋め込み部の両方が、逆V字状のバンドギャッププロファイルを有する半導体材料を含む、請求項1に記載の半導体デバイス。
- 凹部は、基板を露出させる下部領域と、誘電体材料を含む側壁とを有する、請求項1または2に記載の半導体デバイス。
- 突出構造の半導体材料は、シリコンゲルマニウム(SiGe)を含み、
バンドギャッププロファイルは、Geの濃度勾配によって作成され、突出構造の外縁部でGeの濃度が最大となるようにした、請求項1から3のいずれか1項に記載のデバイス。 - 外縁部でのGeの濃度は、60at%から100at%である、請求項4に記載のデバイス。
- 中心部でのGeの濃度は、40at%から60at%である、請求項4または5に記載のデバイス。
- 突出構造は、フィンを形成する、請求項1〜6のいずれか1項に記載のデバイス。
- フィンは、突出構造の延長部の周囲にコンフォーマルに形成されたキャップ層をさらに有する、請求項7に記載のデバイス。
- キャップ層は、SiGeまたはGeからなり、
SiGeの場合、Geの濃度は60at%より大きいようにした、請求項8に記載のデバイス。 - 誘電体領域と半導体領域とを含む、パターニングされた基板を設ける工程と、
半導体領域に、基板を露出させる下部領域と、誘電体材料を含む側壁とを有する凹部を形成する工程と、
凹部内で半導体材料をエピタキシャル成長させることにより、凹部に突出構造を形成する工程と、
誘電体領域で誘電体材料を浸食することにより、突出構造の延長部を露出させる工程とを含み、
半導体材料は、シリコンゲルマニウム(SiGe)であり、
少なくとも突出構造の延長部は、突出構造の外縁部での第1の値から、第1の値より大きい突出構造の中心部での第2の値に向けてバンドギャップの値が徐々に増加する、逆V字状のバンドギャッププロファイルを有する半導体材料を含み、
SiGeのエピタキシャル成長中の圧力と成長温度は、(111)面に対して垂直な成長フロントが優先され、これにより凹部の下部領域に複数のファセットが形成され、該複数のファセットは進展するが完全には結合されず、エピタキシャル成長中に上面(100)を維持してGeの濃度勾配が達成されるように選択される、半導体デバイスの製造方法。 - バンドギャッププロファイルは、Geの濃度勾配によって作成され、突出構造の外縁部でGeの濃度が最大となるようにした、請求項10に記載の方法。
- 成長温度は、450℃から700℃であり、
圧力は、5Torrから1atmである、請求項11に記載の方法。 - 突出構造の延長部の周囲にコンフォーマルなキャップ層を形成する工程をさらに含む、請求項10〜12のいずれか1項に記載の方法。
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US10707331B2 (en) * | 2017-04-28 | 2020-07-07 | Taiwan Semiconductor Manufacturing Company, Ltd. | FinFET device with a reduced width |
US10515954B2 (en) | 2018-03-18 | 2019-12-24 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device having fin structures of varying dimensions |
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FR2936095B1 (fr) | 2008-09-18 | 2011-04-01 | Commissariat Energie Atomique | Procede de fabrication d'un dispositif microelectronique dote de zones semi-conductrices sur isolant a gradient horizontal de concentration en ge. |
US9768305B2 (en) * | 2009-05-29 | 2017-09-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | Gradient ternary or quaternary multiple-gate transistor |
SG169921A1 (en) * | 2009-09-18 | 2011-04-29 | Taiwan Semiconductor Mfg | Improved fabrication and structures of crystalline material |
US8269209B2 (en) * | 2009-12-18 | 2012-09-18 | Intel Corporation | Isolation for nanowire devices |
US8211772B2 (en) * | 2009-12-23 | 2012-07-03 | Intel Corporation | Two-dimensional condensation for uniaxially strained semiconductor fins |
US8395195B2 (en) * | 2010-02-09 | 2013-03-12 | Taiwan Semiconductor Manufacturing Company, Ltd. | Bottom-notched SiGe FinFET formation using condensation |
US8957476B2 (en) * | 2012-12-20 | 2015-02-17 | Intel Corporation | Conversion of thin transistor elements from silicon to silicon germanium |
-
2013
- 2013-09-02 EP EP20130182639 patent/EP2709156A3/en not_active Ceased
- 2013-09-09 JP JP2013185814A patent/JP6236260B2/ja active Active
- 2013-09-12 US US14/024,820 patent/US8963225B2/en active Active
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US20140077332A1 (en) | 2014-03-20 |
EP2709156A2 (en) | 2014-03-19 |
US9029217B1 (en) | 2015-05-12 |
EP2709156A3 (en) | 2014-04-23 |
US20150126010A1 (en) | 2015-05-07 |
US8963225B2 (en) | 2015-02-24 |
JP2014068008A (ja) | 2014-04-17 |
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