JP6195155B2 - Conductive bridge memory device and method of manufacturing the same - Google Patents
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本発明は、導電性ブリッジメモリ装置及び同装置の製造方法に関する。 The present invention relates to a conductive bridge memory device and a method of manufacturing the same.
導電性メモリ装置の一例であるCB-RAM (Conducting Bridge Random Access Memory)は、電気化学的に活性な金属(Ag、Cu等)で構成される電極Aと不活性な金属 (Pt)で構成される電極Bとの間にGeSe、Ag2S等の固体電解質材料を挟んだ、電極A/固体電解質層(メモリ層)/電極Bなる単純構造をとる。電極Aに(電極Bに対して)正電圧を印加することで、電極Aを構成する原子がイオン化して固体電解質層中に侵入し、電界から受けるクーロン力により電極Bに向かって移動する。電極Bに到達したイオンは電子を受け取って中性化し、金属として析出する。この結果、固体電解質層内部に電極A構成金属より成るフィラメント状の導電パスが形成され、電極Aと電極Bが接続されることによって、低抵抗状態が実現される。 CB-RAM (Conducting Bridge Random Access Memory), which is an example of a conductive memory device, consists of an electrode A made of electrochemically active metal (Ag, Cu, etc.) and an inert metal (Pt). A simple structure of electrode A / solid electrolyte layer (memory layer) / electrode B in which a solid electrolyte material such as GeSe or Ag 2 S is sandwiched between the electrode B and the electrode B. By applying a positive voltage to the electrode A (relative to the electrode B), the atoms constituting the electrode A are ionized and enter the solid electrolyte layer, and move toward the electrode B by the Coulomb force received from the electric field. The ions that reach the electrode B receive electrons and are neutralized to be deposited as a metal. As a result, a filament-shaped conductive path made of the metal constituting the electrode A is formed in the solid electrolyte layer, and the low resistance state is realized by connecting the electrode A and the electrode B.
一方、電極Aに(電極Bに対して)負電圧を印加することで、フィラメントの一部がジュール熱により切断され、切断部を起点にフィラメントを構成する電極A構成原子がイオン化される。電界の向きは前記フィラメント形成時と逆向きのため、フィラメント構成原子は電極Aに回収され、高抵抗状態が実現される。CB-RAMは高速、高集積、低消費電力等の優れた特徴を有することから、近い将来微細化限界に直面するフラッシュメモリの代替として、更には、高速性と不揮発性を兼ね備えたユニバーサルメモリとして期待されている。 On the other hand, by applying a negative voltage to the electrode A (with respect to the electrode B), a part of the filament is cut by Joule heat, and the electrode A constituting atoms constituting the filament are ionized from the cut portion as a starting point. Since the direction of the electric field is opposite to that at the time of filament formation, the filament constituent atoms are collected by the electrode A, and a high resistance state is realized. CB-RAM has excellent features such as high speed, high integration, and low power consumption. As a replacement for flash memory that is facing the limit of miniaturization in the near future, and as a universal memory that combines high speed and non-volatility. Expected.
また、原子トランジスタや、導電パスが金属で構成されることから電流輸送特性に優れ、FPGA (Field Programmable Gate Array)用の回路切り替えスイッチへの応用にも期待がかかる。 In addition, it has excellent current transport characteristics due to atomic transistors and conductive paths made of metal, and is expected to be applied to circuit changeover switches for FPGAs (Field Programmable Gate Arrays).
CB-RAMの欠点として、従来のCMOSプロセスに馴染みの薄いカルコゲナイド(S、Se、Te系材料)が使用されていることが挙げられる。近年、固体電解質層、即ちメモリ層をHfO2やTa2O5等の酸化物で置き換えた素子においても、電圧の印加による電極構成原子の拡散が生じ、これに伴う(固体電解質を用いたCB-RAMと類似の)抵抗スイッチングが確認されたことから、実用化に向けた研究開発に拍車がかかっている。固体電解質層に酸化物を用いたCB-RAMを、以降、酸化物CB-RAMと記載する。また、酸化物CB-RAMにおいても、拡散原子(拡散イオン)を供給する側の電極を電極A、もう一方の安定な電極を電極Bと呼ぶことにする。 A disadvantage of CB-RAM is the use of thin chalcogenides (S, Se, Te-based materials) familiar to conventional CMOS processes. In recent years, even in a device in which the solid electrolyte layer, that is, the memory layer is replaced with an oxide such as HfO 2 or Ta 2 O 5 , diffusion of electrode constituent atoms due to application of voltage has occurred, and this is accompanied by (CB using a solid electrolyte) -Resistant switching (similar to RAM) has been confirmed, which has spurred research and development for practical use. Hereinafter, CB-RAM using an oxide for the solid electrolyte layer is referred to as oxide CB-RAM. Also in the oxide CB-RAM, the electrode on the side that supplies diffusion atoms (diffusion ions) is referred to as electrode A, and the other stable electrode is referred to as electrode B.
図１(a)にCu/HfO2/Pt構造の断面図を示す。Cu/HfO2/PtのCB-RAM構造で観測された電流-電圧特性を図１(ｂ)に示す。ここで、図１(a)に示したように、Pt電極(電極B)を接地し、Cu電極(電極A)に電圧を印加している。Cu 電極に正バイアスを印加することでset (低抵抗から高抵抗への抵抗スイッチング)、負バイアスを印加することでreset (高抵抗から低抵抗への抵抗スイッチング)が生じるバイポーラ動作が確認された。 FIG. 1 (a) shows a cross-sectional view of a Cu / HfO 2 / Pt structure. The current-voltage characteristics observed in the Cu / HfO 2 / Pt CB-RAM structure are shown in FIG. Here, as shown in FIG. 1A, the Pt electrode (electrode B) is grounded, and a voltage is applied to the Cu electrode (electrode A). Bipolar operation has been confirmed in which a positive bias is applied to the Cu electrode to cause set (resistance switching from low resistance to high resistance), and a negative bias to cause reset (resistance switching from high resistance to low resistance). .
なお、CB-RAMがset - resetの抵抗スイッチングを繰り返す機能は、抵抗スイッチング現象発現の前処理であるformingと呼ばれるフィラメント形成過程を経て発現する。図１(ｂ)の四角にformingの電流-電圧特性を示す。formingの電流-電圧特性はsetの電流-電圧特性と類似しているが、formingが生じる電圧(Vf)はsetが生じる電圧(Vset)に比べて一般的に高い。 The function of the CB-RAM repeating set-reset resistance switching is manifested through a filament forming process called forming, which is a pretreatment for the appearance of the resistance switching phenomenon. The forming current-voltage characteristics are shown in the squares of FIG. The current-voltage characteristic of forming is similar to the current-voltage characteristic of set, but the voltage (Vf) at which forming occurs is generally higher than the voltage (Vset) at which set occurs.
上記図１の説明にもあるように、電極構成原子(例えば、Cu、Ag)に対する高イオン導電体には分類し難いような酸化物（例えば、HfO2）をメモリ層に用いた場合にも、上記現象と類似の電圧印加による抵抗スイッチングが確認されており、そのフィラメント形成及び抵抗スイッチングの機構は明らかにされていない。故に、酸化物CB-RAMの開発は、従来の電子材料の知識に基づき、酸化物層及び電極の材料選択や結晶性に重きをおくことで行われて来た。 As described in FIG. 1 above, even when an oxide (for example, HfO 2 ) that is difficult to classify as a high ion conductor for electrode constituent atoms (for example, Cu, Ag) is used for the memory layer. Resistance switching by voltage application similar to the above phenomenon has been confirmed, and the mechanism of filament formation and resistance switching has not been clarified. Therefore, the development of the oxide CB-RAM has been carried out based on the knowledge of the conventional electronic materials, focusing on the material selection and crystallinity of the oxide layer and electrode.
本発明の主目的は、これまで、言わば闇雲に前記パラメータ、即ち電極の材料選択等を振ることで行われて来た酸化物CB-RAMのスイッチング特性制御に明確な設計指針を与え、所望のスイッチング特性を実現するための素子構成を提供することにある。 The main object of the present invention is to provide a clear design guideline for controlling the switching characteristics of the oxide CB-RAM, which has been performed by swaying the above-mentioned parameters, that is, the selection of the material of the electrode, in a dark cloud. An object of the present invention is to provide an element configuration for realizing switching characteristics.
発明者らは、Cu/HfO2/PtのCB-RAM構造において、微量の水の添加が抵抗スイッチングに必要な電圧や電流を下げることを見いだした。このことはHfO2の柱状結晶間のメゾ細孔内に毛管凝縮した水がCuイオンの電気化学的拡散を通じてスイッチングを生じさせることを意味する。この結果は、CB-RAMにおける抵抗スイッチングを発生させる上で、酸化物多結晶膜成膜時或いは成膜後に意図せずして多結晶粒界に吸収された水分の存在が重要であることを示唆している。よって、従来のCB-RAMのように、メモリ層自体を拡散媒質と捉えるのではなく、水を吸収、保持するための多孔質体としてメモリ層を捉え直す必要があることが分かってきた。よって、上記目的は、メゾ細孔或いはナノ細孔を有する酸化物層或いは酸化物以外の多孔質膜をメモリ層に用い、溶媒として従来の水分に加え、非極性性から強極性の有機溶媒、酸・塩基・塩類の水溶液を加えることで、金属イオンの電気化学的形成や移動に影響しうる液中の環境を制御することによって果たされる。なお、細孔の形とサイズ、壁の表面の酸塩基性を考慮し、細孔空間内の電気化学的特性を制御することにより、高性能なCB-RAMを設計することが可能となる。 The inventors have found that in a Cu / HfO 2 / Pt CB-RAM structure, the addition of a small amount of water reduces the voltage and current required for resistance switching. This means that water condensed in the mesopores between the columnar crystals of HfO 2 causes switching through electrochemical diffusion of Cu ions. This result shows that the presence of moisture absorbed in the polycrystalline grain boundary unintentionally during or after the formation of the oxide polycrystalline film is important in generating resistance switching in the CB-RAM. Suggests. Therefore, it has been found that it is necessary to re-recognize the memory layer as a porous body for absorbing and retaining water, instead of perceiving the memory layer itself as a diffusion medium as in the conventional CB-RAM. Therefore, the object is to use an oxide layer having mesopores or nanopores or a porous film other than an oxide for the memory layer, in addition to conventional moisture as a solvent, nonpolar to strong polar organic solvents, This is accomplished by adding an aqueous solution of acids, bases and salts to control the environment in the liquid that can affect the electrochemical formation and migration of metal ions. It is possible to design a high-performance CB-RAM by controlling the electrochemical characteristics in the pore space in consideration of the shape and size of the pores and the acid basicity of the wall surface.
また、本発明の抵抗スイッチング発現に水が不可欠であったが、水は揮発しやすいという問題があった。イオン液体は常温で液体の塩であり、不揮発性、難燃性、様々な無機、有機化合物を溶解する機能を持つ液体である。また塩であるために導電性を示す。そこで、Cu/HfO2/Ptで構成される素子に水に替えてイオン液体を添加すると同様に抵抗スイッチング現象が起こることがわかった。イオン液体は構成イオンの分子設計でその性質を自在に変化させることができる。そこで、イオン液体を使用することで，安定で高性能なCB-RAMの設計が可能となる。 Moreover, although water was indispensable for the resistance switching expression of the present invention, there was a problem that water easily volatilizes. An ionic liquid is a salt that is liquid at room temperature, and is a liquid that is non-volatile, flame retardant, and has a function of dissolving various inorganic and organic compounds. Moreover, since it is a salt, it shows electroconductivity. Therefore, it was found that the resistance switching phenomenon occurs in the same manner when an ionic liquid is added instead of water to an element composed of Cu / HfO 2 / Pt. The properties of ionic liquids can be freely changed by molecular design of constituent ions. Therefore, the use of ionic liquids enables the design of stable and high-performance CB-RAM.
イオン液体としては、化学式 As ionic liquid, chemical formula
で記載されるイオン液体が利用できる。 Can be used.
式中、Ｒ１、Ｒ2、Ｒ3は、同じでも違っていてもよく、Ｒ1は炭素数１〜６のアルキル基、炭素数２〜６のアルケニル基を表し、Ｒ2は、水素原子、炭素数１〜16のアルキル基、炭素数２〜６のアルケニル基、アルコキシ基を表す。アルキル基の中にはエーテル官能基，チオエーテル官能基が含まれていても構わない。Ｒ3は水素原子、フェニル基、メチル基、イソプロピル基を示す。化学式5のｎはメチレン数を示し、n=1もしくは2である。化学式8においてＲ1とＲ2は炭素鎖が連結していても良く、この場合はシクロペンタン環、シクロヘキサン環、シクロヘプタン環である。化学式12におけるｎはメチレンオキシ基の数を表している。イオン液体のアニオン（Ｘ）としてＡｌＣｌ4 -、ＢＦ4 -、ＰＦ6 -、N(SO2CF3)2 -、N(SO2F)2 -、MeSO3 -、ＮＯ3 -、ＲＣＯＯ-、ＲＳＯ3 -、ＮＨ2ＣＨＲＣＯＯ-、ＳＯ4 2-（ここでＲはＨ、アルキル基、アルキルオキシ基を示す）が挙げられる。 In the formula, R 1 , R 2 and R 3 may be the same or different, R 1 represents an alkyl group having 1 to 6 carbon atoms or an alkenyl group having 2 to 6 carbon atoms, and R 2 represents a hydrogen atom Represents an alkyl group having 1 to 16 carbon atoms, an alkenyl group having 2 to 6 carbon atoms, and an alkoxy group. The alkyl group may contain an ether functional group or a thioether functional group. R 3 represents a hydrogen atom, a phenyl group, a methyl group or an isopropyl group. In the chemical formula 5, n represents the number of methylene, and n = 1 or 2. In the chemical formula 8, R 1 and R 2 may be linked with a carbon chain, and in this case, they are a cyclopentane ring, a cyclohexane ring, and a cycloheptane ring. N in the chemical formula 12 represents the number of methyleneoxy groups. As the anion (X) of the ionic liquid, AlCl 4 − , BF 4 − , PF 6 − , N (SO 2 CF 3 ) 2 − , N (SO 2 F) 2 − , MeSO 3 − , NO 3 − , RCOO − , RSO 3 − , NH 2 CHRCOO − , SO 4 2− (where R represents H, an alkyl group, or an alkyloxy group).
本発明の基本的な構成は、電気化学的に活性でイオン化し易い第１の金属と電気化学的に安定な第２の金属との間にメモリ層となる多孔質膜体を介在させると共に、前記多孔質膜体の細孔中に非極性性から強極性の有機溶媒もしくは酸・塩基・塩類の水溶液またはイオン液体を留保させたことにある。 The basic configuration of the present invention is to interpose a porous film body serving as a memory layer between a first metal that is electrochemically active and easily ionized and a second metal that is electrochemically stable, A nonpolar to strong polar organic solvent or an aqueous solution of an acid / base / salt or an ionic liquid is retained in the pores of the porous membrane.
ここで、前記第１の金属としては、Ｃｕ、Ａｇ、Ｔｉ、Ｚｎ、Ｖ等又はこれら金属の合
金が、前記第２の金属としては、Ｐｔ、Ａｕ、Ｉｒ、Ｒｕ、Ｒｈ、Ｐｄ等又はこれら金属の合金がそれぞれ利用可能である。
Here, the first metal is Cu, Ag, Ti, Zn, V or the like or an alloy of these metals, and the second metal is Pt, Au, Ir, Ru, Rh, Pd or the like or these. Metal alloys are available for each.
なお、CB-RAMの高抵抗状態は電流が流れにくいことから「オフ」状態、低抵抗状態は電流が流れやすいことから「オン」状態とみなすことが出来、メモリ素子としてではなく、スイッチ素子として用いることも可能である。 The high resistance state of CB-RAM can be regarded as an “off” state because it is difficult for current to flow, and the low resistance state can be regarded as an “on” state because current is likely to flow. It is also possible to use it.
本発明によれば、電極A構成原子の拡散を媒介する溶媒の調整により、抵抗スイッチング特性、特に、抵抗スイッチングが生じる電圧や電流の制御が可能となり、抵抗スイッチングを発生させるために必要な電力とスイッチング電圧のばらつきを低減することができる。また、蒸発及び電気分解し難い溶媒を酸化物多結晶膜粒界或いは多孔質体中の水と置換することにより、劣化に強く安定した導電性ブリッジメモリ装置またはスイッチ素子の作製が可能となる利点がある。 According to the present invention, by adjusting the solvent that mediates the diffusion of the atoms constituting the electrode A, it is possible to control the resistance switching characteristics, in particular, the voltage and current at which the resistance switching occurs, and the power required to generate the resistance switching. Variations in switching voltage can be reduced. Further, by replacing a solvent that is difficult to evaporate and electrolyze with water in the oxide polycrystalline film grain boundary or the porous body, it is possible to produce a conductive bridge memory device or a switch element that is resistant to deterioration and stable. There is.
［第１実施形態］
本発明の第１実施形態による導電性ブリッジメモリ装置について図２乃至図９を用いて説明する。
[First Embodiment]
A conductive bridge memory device according to a first embodiment of the present invention will be described with reference to FIGS.
図２に本発明のメモリセル構成を示す。メモリセル１は電気抵抗の変化により情報を記憶する可変抵抗素子である、CB-RAM素子２の一端とN型MOSトランジスタで形成される選択トランジスタ３のソースを接続した構成から成り、選択トランジスタ３のドレインをビット線BL１、CB-RAM素子２のもう一端をソース線SL１、選択トランジスタ３のゲートがワード線WLに、それぞれ接続されている。 FIG. 2 shows a memory cell configuration of the present invention. The memory cell 1 has a configuration in which one end of a CB-RAM element 2, which is a variable resistance element that stores information by a change in electrical resistance, and a source of a selection transistor 3 formed of an N-type MOS transistor are connected. Are connected to the bit line BL1, the other end of the CB-RAM element 2 is connected to the source line SL1, and the gate of the selection transistor 3 is connected to the word line WL.
ここで、CB-RAM素子２は電気的ストレス、例えば、直流又はパルス電圧の印加により、可逆的な電気抵抗の変化を示し、電源を切ってもその抵抗が保持されることより、その抵抗に対応させて情報の記憶が可能な不揮発性の記憶素子で、例えば、CB-RAM素子としては、活性電極(電極A)と不活性電極(電極B)の間にゾルゲル、スパッタ、MOCVD法等で成膜されたNiOy (y 〜 1)、TiOz、HfOz (z 〜 2)等を挟み込んだ構造を作製する。 Here, the CB-RAM element 2 shows a reversible change in electrical resistance due to electrical stress, for example, application of direct current or pulse voltage, and the resistance is retained even when the power is turned off. Non-volatile storage element that can store information in correspondence.For example, as a CB-RAM element, a sol-gel, sputtering, MOCVD method, etc. is used between an active electrode (electrode A) and an inactive electrode (electrode B). A structure in which the deposited NiO y (y ˜1), TiO z , HfO z (z ˜2), etc. are sandwiched is fabricated.
図３は、図２のメモリセルを適用した本発明のメモリセル構成を示す。図２及び図３で示される本発明のメモリセル及びメモリセルアレイの構成は特許第4684297号、 特許第4662990号両公報に示された構成と回路構成的には類似であるが、本発明ではCB-RAM素子のメモリ層に、メゾ細孔或いはナノ細孔を有する酸化物層或いは酸化物以外の多孔質膜をメ
モリ層に用い、そこに非極性性から強極性の有機溶媒、酸・塩基・塩類の水溶液、イオン液体等、金属イオンの電気化学的形成や移動に影響しうる溶媒を吸収、保持させる点が従来構造と異なる。
FIG. 3 shows a memory cell configuration of the present invention to which the memory cell of FIG. 2 is applied. The configuration of the memory cell and the memory cell array of the present invention shown in FIGS. 2 and 3 is similar in circuit configuration to that shown in both Japanese Patent Nos. 4684297 and 4662990, but in the present invention, CB -For the memory layer of the RAM element, an oxide layer having mesopores or nanopores or a porous film other than oxide is used for the memory layer, and there is a nonpolar to strong organic solvent, acid / base, It differs from the conventional structure in that it absorbs and retains a solvent that can affect the electrochemical formation and movement of metal ions, such as an aqueous solution of salt and an ionic liquid.
図４にメモリセルアレイの断面図、図５に同メモリセルアレイ作製工程断面図、図６に同メモリセルアレイの平面図を示す。ここで、本発明における特徴的なプロセスフローである図５(ｅ)及び(ｆ)の詳細な手順について述べる。図５(ｅ)では、反応性RFマグネトロンスパッタリング法により電極B(例えばPt)上にHfO2を、例えば５０ nm形成する。この時、HfO2薄膜が多結晶成長し、薄膜中に結晶粒界が導入されることが重要である。 4 is a sectional view of the memory cell array, FIG. 5 is a sectional view of the memory cell array manufacturing process, and FIG. 6 is a plan view of the memory cell array. Here, a detailed procedure of FIGS. 5E and 5F, which is a characteristic process flow in the present invention, will be described. In FIG. 5E, HfO 2 is formed to 50 nm, for example, on the electrode B (for example, Pt) by the reactive RF magnetron sputtering method. At this time, it is important that the HfO 2 thin film grows in polycrystal and a grain boundary is introduced into the thin film.
図７に、表１に記載の条件でSiO2(Si熱酸化膜)上にPt(電極B)、続いてHfO2薄膜、Cu(電極A)を成膜することで作製されたCu/ HfO2/Pt構造の断面図を示す。HfO2が柱状成長し、柱状結晶間にナノサイズの間隙(粒界)が存在することが分かる。図５(ｆ)では、例えば、イオン液体である[bmim]、[TFSA]を図５(ｅ)で堆積されたHfO2薄膜上にスピンコーティング法によって均一に塗布し、大気中或いは低圧力下にて、メゾ細孔或いはナノ細孔として機能するHfO2薄膜粒界晶粒に吸収させる。特に、低圧力下では、結晶粒界に毛細管凝縮している水分とイオン液体との置換が効率的に行われる。 FIG. 7 shows a Cu / HfO film produced by depositing Pt (electrode B), followed by an HfO 2 thin film and Cu (electrode A) on SiO 2 (Si thermal oxide film) under the conditions shown in Table 1. 2 A cross-sectional view of the / Pt structure is shown. It can be seen that HfO 2 grows in a columnar shape and nano-sized gaps (grain boundaries) exist between the columnar crystals. In FIG. 5F, for example, [bmim] and [TFSA] which are ionic liquids are uniformly applied on the HfO 2 thin film deposited in FIG. Then, the HfO 2 thin film grain boundary crystal grains functioning as mesopores or nanopores are absorbed. In particular, under low pressure, the replacement of the water condensed in the capillary at the grain boundaries with the ionic liquid is performed efficiently.
以下に、図３のメモリセルアレイのset時の動作について説明する。前記のように、setは高抵抗から低抵抗への書き換え行程である。まず、選択メモリセルに接続されたビット線選択トランジスタ４をオンにする。続いて(或いはこれと同時に)、CB-RAM素子２に接続されたセル選択トランジスタ３のゲートに接続されているワード線に電圧を印加し、セル選択トランジスタ３をオンにする。選択ビット線に印加するバイアス電圧はソース線に対して正の値となるよう設定し(上部電極が電極Bの場合には負となるよう設定)、その絶対値はsetに要する電圧の絶対値と同じかやや大きい程度とする。選択メモリセルに接続されたソース線を基準電位、例えば接地電位０ｖにすることで、ビット線のバイアス電圧からビット線選択トランジスタ４、セル選択トランジスタ３、及びCB-RAM素子２を経由する接地電位への電流経路が出来、バイアス電圧はCB-RAM素子２の高抵抗状態における抵抗Rとセル選択トランジスタ３のチャネル抵抗r、ビット線選択トランジスタ４のチャネル抵抗の比に応じて、CB-RAM素子２とビット線選択トランジスタ４のチャネル抵抗ｒ’に配分される。rとｒ’の和は、Rに比べて小さく、CB-RAM素子２の低抵抗状態における抵抗R’に比べて大きくなるようrとｒ’を設定する。即ち、R’< r + ｒ’< Rが満たされるようにする。setの瞬間にCB-RAM素子２の抵抗はRからR’に減少することから、setの直後にCB-RAM素子２を流れる電流はr + ｒ’によって制御される。その後、バイアス電圧を０Ｖに戻せば、setが完了する。 The operation at the time of setting the memory cell array of FIG. 3 will be described below. As described above, set is a rewriting process from high resistance to low resistance. First, the bit line selection transistor 4 connected to the selected memory cell is turned on. Subsequently (or simultaneously), a voltage is applied to the word line connected to the gate of the cell selection transistor 3 connected to the CB-RAM element 2 to turn on the cell selection transistor 3. The bias voltage applied to the selected bit line is set to be positive with respect to the source line (set to be negative when the upper electrode is electrode B), and its absolute value is the absolute value of the voltage required for set Same as or slightly larger than By setting the source line connected to the selected memory cell to the reference potential, for example, the ground potential 0v, the ground potential via the bit line selection transistor 4, the cell selection transistor 3, and the CB-RAM element 2 from the bias voltage of the bit line. The bias voltage depends on the ratio of the resistance R of the CB-RAM element 2 in the high resistance state, the channel resistance r of the cell selection transistor 3, and the channel resistance of the bit line selection transistor 4 2 and the channel resistance r ′ of the bit line selection transistor 4. r and r 'are set so that the sum of r and r' is smaller than R and larger than the resistance R 'of the CB-RAM element 2 in the low resistance state. That is, R ′ <r + r ′ <R is satisfied. Since the resistance of the CB-RAM element 2 decreases from R to R 'at the moment of set, the current flowing through the CB-RAM element 2 immediately after set is controlled by r + r'. Thereafter, the set is completed when the bias voltage is returned to 0V.
一方、低抵抗から高抵抗への切り換え過程であるresetも、前記set過程と同様の手順で
行なうが、注意すべき点は、選択ビット線に印加する(ソース線に対する)バイアス電圧はsetの場合と正負が逆になる。即ち、上部電極が電極Aの場合、選択ビット線に印加するバイアス電圧はソース線に対して負の値となるよう設定する。例えば、選択ビット線を接地電位０Ｖ、ソース線を正の値となるよう設定する。その後、バイアス電圧を０Ｖに戻せばresetが完了する。
On the other hand, reset, which is a process of switching from low resistance to high resistance, is performed in the same procedure as the set process, but it should be noted that the bias voltage applied to the selected bit line (relative to the source line) is set. And the sign is reversed. That is, when the upper electrode is the electrode A, the bias voltage applied to the selected bit line is set to a negative value with respect to the source line. For example, the selected bit line is set to a ground potential of 0 V and the source line is set to a positive value. Thereafter, resetting is completed by returning the bias voltage to 0V.
読み出しには、セル選択トランジスタ３、及びビット線選択トランジスタ４のチャネル抵抗が、両方ともCB-RAM素子２の低抵抗の値ｒより十分小さくなるよう、ゲート電圧を調整し、既定の電圧を印加した際に流れる電流を検出することでCB-RAM素子２の抵抗を判別する。 For reading, the gate voltage is adjusted and a predetermined voltage is applied so that the channel resistances of the cell selection transistor 3 and the bit line selection transistor 4 are both sufficiently smaller than the low resistance value r of the CB-RAM element 2. The resistance of the CB-RAM element 2 is determined by detecting the current that flows.
図８(a)と図８(b)にHfO2薄膜に意図的に溶媒を吸収させることなく作製されたCu/ HfO2/Pt構造とHfO2薄膜にイオン液体である [PIME]、[TFSA]を吸収させたCu/HfO2/Pt構造の電流-電圧特性をそれぞれ示す。HfO2層にイオン液体を吸収させることで、Vf、Vset、更に、Iresetが低減されることが分かる。図９にHfO2薄膜にイオン液体である[bmim][TFSA]或いは[PIME][TFSA]を吸収させたCu/ HfO2/Pt構造のVf、Vset及びVreset分布を示す。 It is fabricated Cu / HfO 2 / Pt structure and an ionic liquid to the HfO 2 thin film without absorbing intentionally solvent HfO 2 thin film in FIG. 8 (b) 8 and (a) [PIME], [ TFSA ] Shows the current-voltage characteristics of the Cu / HfO 2 / Pt structure in which the metal is absorbed. It can be seen that Vf, Vset, and Ireset are reduced by absorbing the ionic liquid in the HfO 2 layer. FIG. 9 shows Vf, Vset, and Vreset distributions of a Cu / HfO 2 / Pt structure in which an ionic liquid [bmim] [TFSA] or [PIME] [TFSA] is absorbed in an HfO 2 thin film.
ここで、[bmim]、[TFSA]、[PIME]の表記は以下の化合物を意味する。
[bmim]： ヘキサフルオロリン酸1-ブチル-3-メチルイミダゾリウム(BMIM-PF6) 1-buthyl-3methtlimidazolium
[TFSA]： 1-エチル-3-メチルイミダゾリウムビス(トリ フルオロメタンスルホニル)イミド bis(trifkuoromethane sulfonyl)imide。[TFSI]とも表記される。
[PIME]： N-diethyl-Nmethul-N(-2-methoxyethyl)ammonium。[DEME]とも表記される。
Here, the notations [bmim], [TFSA], and [PIME] mean the following compounds.
[bmim]: 1-buthyl-3methtlimidazolium 1-butyl-3-methylimidazolium hexafluorophosphate (BMIM-PF6)
[TFSA]: 1-ethyl-3-methylimidazolium bis (trifluoromethanesulfonyl) imide bis (trifkuoromethane sulfonyl) imide. Also written as [TFSI].
[PIME]: N-diethyl-Nmethul-N (-2-methoxyethyl) ammonium. Also written as [DEME].
同図にHfO2薄膜に意図的に溶媒を吸収させていないCu/HfO2/Pt構造を真空中及び大気中で動作させた際に得られたVf、Vset及びVreset分布を示す。図９は同一条件で作製された複数のCu/HfO2/Pt構造について電流-電圧特性を評価し、Vf、Vset及びVresetの累積確率を示したものである。例えば、Cu/HfO2/Pt構造のHfO2層に[PIME][TFSA]を吸収させた場合(四角)と、HfO2層に溶媒を吸収させることなく作製されたCu/HfO2/Pt構造を真空中で動作させた場合(三角)では、前者がVf = 6.6 Vで累積確率が100%に達するのに対し、後者では11.8 Vで累積確率が100%に達しており、且つ、同一のVfで比較した場合、前者の累積確率は後者のそれよりも常に大きい。これは、前者におけるVfの平均及びVfのばらつきが後者に比べて小さいことを意味しており、HfO2層へのイオン液体の供給によって、Vfの平均値とばらつきが共に小さくなることを意味する。Vsetについても、Vfと類似の傾向が確認され、イオン液体の供給によって、Vsetの平均値及びそのばらつきが共に低下することが分かる。 The figure shows the Vf, Vset and Vreset distributions obtained when the Cu / HfO 2 / Pt structure in which the solvent is not intentionally absorbed in the HfO 2 thin film is operated in vacuum and in the atmosphere. FIG. 9 shows current-voltage characteristics of a plurality of Cu / HfO 2 / Pt structures fabricated under the same conditions, and shows cumulative probabilities of Vf, Vset, and Vreset. For example, [PIME] the HfO 2 layer of Cu / HfO 2 / Pt structure when imbibed with [TFSA] (rectangles), fabricated Cu / HfO 2 / Pt structure without absorbing the solvent HfO 2 layer When operating in a vacuum (triangle), the former reaches 100% cumulative probability at Vf = 6.6 V, while the latter reaches 100% cumulative probability at 11.8 V, and the same When compared with Vf, the cumulative probability of the former is always greater than that of the latter. This means that the average of Vf and the variation in Vf in the former are smaller than the latter, and the average value of Vf and the variation are both reduced by supplying the ionic liquid to the HfO 2 layer. . A tendency similar to Vf is also confirmed for Vset, and it can be seen that the average value of Vset and its variation both decrease with the supply of ionic liquid.
［変形実施形態］
本発明は上記実施形態に限らず種々の変形が可能である。
[Modified Embodiment]
The present invention is not limited to the above embodiment, and various modifications can be made.
例えば、上記実施形態に記載した酸化物膜の材料、成膜条件、用いられる溶媒等は、一例を示したものにすぎず、当業者の技術常識等に応じて適宜修正や変更が可能である。 For example, the material of the oxide film, the film formation conditions, the solvent used, and the like described in the above embodiment are merely examples, and can be appropriately modified or changed according to the common general knowledge of those skilled in the art. .
また、上記第1実施形態では、CB-RAM、即ちメモリデバイスとして応用した例を示したが、本発明は電極A構成原子の多孔質膜内における拡散を制御する一般的手法を提供するものであり、その応用はメモリに限定されるものではなく、種々のデバイスに適用することが可能である。 Further, in the first embodiment, an example of application as a CB-RAM, that is, a memory device has been shown. However, the present invention provides a general method for controlling the diffusion of the constituent atoms of the electrode A in the porous film. The application is not limited to the memory, but can be applied to various devices.
１： メモリセル
２： 可変抵抗素子（＝CB-RAM素子）
３： セル選択トランジスタ
４： ビット線選択トランジスタ
WL、WL１、WL２： ワード線
BL、BL１〜BL２： ビット線
SL、SL１、SL２： ソース線
1: Memory cell 2: Variable resistance element (= CB-RAM element)
3: Cell selection transistor 4: Bit line selection transistor
WL, WL1, WL2: Word line
BL, BL1 to BL2: Bit lines
SL, SL1, SL2: Source line
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