JP6176826B2 - 起動回路を有する完全相補型自己バイアス差動受信機 - Google Patents
起動回路を有する完全相補型自己バイアス差動受信機 Download PDFInfo
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- JP6176826B2 JP6176826B2 JP2013039970A JP2013039970A JP6176826B2 JP 6176826 B2 JP6176826 B2 JP 6176826B2 JP 2013039970 A JP2013039970 A JP 2013039970A JP 2013039970 A JP2013039970 A JP 2013039970A JP 6176826 B2 JP6176826 B2 JP 6176826B2
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/45—Differential amplifiers
- H03F3/45071—Differential amplifiers with semiconductor devices only
- H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
- H03F3/45179—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using MOSFET transistors as the active amplifying circuit
- H03F3/4521—Complementary long tailed pairs having parallel inputs and being supplied in parallel
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/45—Differential amplifiers
- H03F3/45071—Differential amplifiers with semiconductor devices only
- H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
- H03F3/45376—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using junction FET transistors as the active amplifying circuit
- H03F3/45381—Long tailed pairs
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/72—Gated amplifiers, i.e. amplifiers which are rendered operative or inoperative by means of a control signal
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
- H03F2203/45—Indexing scheme relating to differential amplifiers
- H03F2203/45466—Indexing scheme relating to differential amplifiers the CSC being controlled, e.g. by a signal derived from a non specified place in the dif amp circuit
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
- H03F2203/45—Indexing scheme relating to differential amplifiers
- H03F2203/45674—Indexing scheme relating to differential amplifiers the LC comprising one current mirror
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
- H03F2203/72—Indexing scheme relating to gated amplifiers, i.e. amplifiers which are rendered operative or inoperative by means of a control signal
- H03F2203/7227—Indexing scheme relating to gated amplifiers, i.e. amplifiers which are rendered operative or inoperative by means of a control signal the gated amplifier being switched on or off by a switch in the supply circuit of the amplifier
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Amplifiers (AREA)
- Logic Circuits (AREA)
- Dc Digital Transmission (AREA)
Description
異なる図面において同じ参照符号が使用されている場合、これは、類似または同一の項目であることを示す。
Claims (4)
- 起動回路に接続された、正ドライバ部分および負ドライバ部分であって、前記正ドライバ部分および負ドライバ部分のそれぞれに正入力信号および負入力信号を入力し、かつ前記正ドライバ部分および負ドライバ部分から出力信号を出力する、前記正ドライバ部分および前記負ドライバ部分を含んでなり、および、前記起動回路には第1の導電型のテール電流トランジスタおよび第2の導電型のテール電流トランジスタが結合し、前記第1の導電型のテール電流トランジスタに正電圧が結合し、前記第2の導電型のテール電流トランジスタに負電圧が結合している、差動受信機の動作方法において、
前記第1の導電型のテール電流トランジスタを、前記第2の導電型のテール電流トランジスタが与える仮想負電圧によって変調する工程であって、前記第1の導電型のテール電流トランジスタは前記正電圧と仮想正電圧との間に置かれる、第1の導電型のテール電流トランジスタを変調する工程と、
前記第2の導電型のテール電流トランジスタを、前記第1の導電型のテール電流トランジスタが与える仮想正電圧によって変調する工程であって、前記第2の導電型の前記テール電流トランジスタは前記仮想負電圧と前記負電圧との間に置かれる、第2の導電型のテール電流トランジスタを変調する工程とを備え、
前記第1および第2の導電型のテール電流トランジスタを変調する結果、前記差動受信機を製造する時に生じる欠陥の結果生じる欠陥電流を前記起動回路が補償する、方法。 - 第1のイネーブル入力において第1のイネーブル信号を受信する工程であって、前記第1のイネーブル入力は第1のテール電流源イネーブルトランジスタに結合され、前記第1のテール電流源イネーブルトランジスタは、テール電流の総量の第1の部分が流れることを可能にし、前記第1のテール電流源イネーブルトランジスタは、前記第1の導電型の前記テール電流トランジスタおよび前記第2の導電型の前記テール電流トランジスタから成る群から選択される要素に結合される、第1のイネーブル入力において第1のイネーブル信号を受信する工程と、
第2のイネーブル入力において第2のイネーブル信号を受信する工程であって、前記第2のイネーブル入力は第2のテール電流源イネーブルトランジスタに結合され、前記第2のテール電流源イネーブルトランジスタは、前記テール電流の総量の第2の部分が流れることを可能にする、第2のイネーブル入力において第2のイネーブル信号を受信する工程とをさらに備える、請求項1に記載の方法。 - 前記正ドライバ部分は前記仮想正電圧に結合し、および前記負ドライバ部分は前記仮想負電圧に結合する、請求項1に記載の方法。
- 請求項1に記載の差動受信機の動作方法において、
前記第1の導電型のテール電流トランジスタのソース、ドレイン、ゲート、およびボディから成る群から選択される第1の端子を前記仮想正電圧に結合する工程と、
前記第1の導電型のテール電流トランジスタの前記ソース、前記ドレイン、前記ゲート、および前記ボディから成る群から選択される第2の端子を前記仮想負電圧に結合する工程と、
前記第1の導電型のテール電流トランジスタのソース、前記ドレイン、前記ゲート、および前記ボディから成る群から選択される第3の端子を正電圧に結合する工程と、
前記第1の導電型のテール電流トランジスタの前記ソース、前記ドレイン、前記ゲート、前記および前記ボディから成る群から選択される第4の端子を負電圧に結合する工程と、
正テール電流源の基準を、負テール電流源に関連付けられる仮想負電圧に置く工程と、
前記負テール電流源の基準を、前記正テール電流源に関連付けられる仮想正電圧に置く工程とを備える、方法。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US13/435,981 US8823454B2 (en) | 2012-03-30 | 2012-03-30 | Fully complementary self-biased differential receiver with startup circuit |
US13/435,981 | 2012-03-30 |
Publications (3)
Publication Number | Publication Date |
---|---|
JP2013214957A JP2013214957A (ja) | 2013-10-17 |
JP2013214957A5 JP2013214957A5 (ja) | 2016-04-14 |
JP6176826B2 true JP6176826B2 (ja) | 2017-08-09 |
Family
ID=49234102
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2013039970A Expired - Fee Related JP6176826B2 (ja) | 2012-03-30 | 2013-02-28 | 起動回路を有する完全相補型自己バイアス差動受信機 |
Country Status (3)
Country | Link |
---|---|
US (1) | US8823454B2 (ja) |
JP (1) | JP6176826B2 (ja) |
CN (1) | CN103368510B (ja) |
Families Citing this family (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9294095B2 (en) * | 2013-09-19 | 2016-03-22 | Micron Technology, Inc. | Apparatuses and methods for input buffer having combined output |
US9130563B1 (en) * | 2014-05-22 | 2015-09-08 | Xilinx, Inc. | Programmable receivers and methods of implementing a programmable receiver in an integrated circuit |
US9251875B1 (en) * | 2014-09-26 | 2016-02-02 | Qualcomm Incorporated | Register file circuit and method for improving the minimum operating supply voltage |
US10187229B2 (en) * | 2016-03-07 | 2019-01-22 | Texas Instruments Incorporated | Bi-directional, full-duplex differential communication over a single conductor pair |
CN108008933B (zh) * | 2016-11-02 | 2022-02-08 | 中芯国际集成电路制造(上海)有限公司 | 一种用于产生芯片的随机序列号的电路及包括该电路的芯片 |
KR102450299B1 (ko) * | 2018-05-15 | 2022-10-05 | 에스케이하이닉스 주식회사 | 증폭기, 이를 이용하는 수신 회로, 반도체 장치 및 시스템 |
WO2021081787A1 (zh) * | 2019-10-30 | 2021-05-06 | 华为技术有限公司 | 运算放大器及运算放大器的启动电路 |
CN112152606B (zh) * | 2020-09-28 | 2023-12-26 | 中国电子科技集团公司第二十四研究所 | 接口电路及电子装置 |
Family Cites Families (19)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4336615A (en) * | 1980-10-02 | 1982-06-22 | Rca Corporation | Linear loading for PWM filter |
US4937476A (en) | 1988-06-16 | 1990-06-26 | Intel Corporation | Self-biased, high-gain differential amplifier with feedback |
US4958133A (en) | 1989-11-13 | 1990-09-18 | Intel Corporation | CMOS complementary self-biased differential amplifier with rail-to-rail common-mode input-voltage range |
US5703532A (en) | 1995-12-13 | 1997-12-30 | International Business Machines Corporation | Fully differential self-biased signal receiver |
US6046638A (en) * | 1998-03-04 | 2000-04-04 | Nortel Networks Corporation | Receive amplifier for reception of high-speed data signals |
US6169424B1 (en) | 1998-11-03 | 2001-01-02 | Intel Corporation | Self-biasing sense amplifier |
JP2000306382A (ja) * | 1999-02-17 | 2000-11-02 | Hitachi Ltd | 半導体集積回路装置 |
KR100366616B1 (ko) | 1999-05-19 | 2003-01-09 | 삼성전자 주식회사 | 저전압 인터페이스용 고속 입력버퍼 회로 |
US6304141B1 (en) | 2000-06-30 | 2001-10-16 | Intel Corporation | Complementary input self-biased differential amplifier with gain compensation |
US6804305B1 (en) | 2000-08-09 | 2004-10-12 | International Business Machines Corporation | Wide common mode range differential receiver |
US6738432B2 (en) * | 2001-03-21 | 2004-05-18 | Ericsson Inc. | System and method for RF signal amplification |
US6696894B1 (en) * | 2002-06-12 | 2004-02-24 | Analog Devices, Inc. | Operational amplifier with independent input offset trim for high and low common mode input voltages |
US6864725B2 (en) | 2002-06-05 | 2005-03-08 | Micron Technology, Inc. | Low current wide VREF range input buffer |
US6924702B2 (en) | 2003-06-17 | 2005-08-02 | Taiwan Semiconductor Manufacturing Co., Ltd. | Low supply voltage and self-biased high speed receiver |
JP2005063026A (ja) * | 2003-08-08 | 2005-03-10 | Nec Micro Systems Ltd | 基準電圧発生回路 |
JP3936952B2 (ja) * | 2004-11-26 | 2007-06-27 | 株式会社半導体理工学研究センター | Ab級cmos出力回路 |
US7863981B2 (en) * | 2008-04-02 | 2011-01-04 | Spectra Linear, Inc. | Rail-to-rail operational amplifier |
CN101943613B (zh) * | 2009-07-03 | 2014-07-23 | 飞思卡尔半导体公司 | 亚阈值cmos温度检测器 |
CN201663584U (zh) * | 2010-04-06 | 2010-12-01 | 四川和芯微电子股份有限公司 | 前置均衡放大电路 |
-
2012
- 2012-03-30 US US13/435,981 patent/US8823454B2/en active Active
-
2013
- 2013-02-28 JP JP2013039970A patent/JP6176826B2/ja not_active Expired - Fee Related
- 2013-03-28 CN CN201310102611.2A patent/CN103368510B/zh not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
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US20130257513A1 (en) | 2013-10-03 |
CN103368510B (zh) | 2017-10-13 |
CN103368510A (zh) | 2013-10-23 |
US8823454B2 (en) | 2014-09-02 |
JP2013214957A (ja) | 2013-10-17 |
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