JP6164228B2 - Module and manufacturing method thereof - Google Patents

Module and manufacturing method thereof Download PDF

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JP6164228B2
JP6164228B2 JP2014558424A JP2014558424A JP6164228B2 JP 6164228 B2 JP6164228 B2 JP 6164228B2 JP 2014558424 A JP2014558424 A JP 2014558424A JP 2014558424 A JP2014558424 A JP 2014558424A JP 6164228 B2 JP6164228 B2 JP 6164228B2
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wiring board
module
wiring
land electrode
electrode
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JPWO2014115358A1 (en
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喜人 大坪
喜人 大坪
酒井　範夫
範夫 酒井
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Murata Manufacturing Co Ltd
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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3457—Solder materials or compositions; Methods of application thereof
    • H05K3/3473—Plating of solder
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341—Surface mounted components
    • H05K3/3431—Leadless components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13111—Tin [Sn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10954—Other details of electrical connections
    • H05K2201/10984—Component carrying a connection agent, e.g. solder, adhesive
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341—Surface mounted components
    • H05K3/3431—Leadless components
    • H05K3/3442—Leadless components having edge contacts, e.g. leadless chip capacitors, chip carriers
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Manufacturing Of Printed Wiring (AREA)

Description

この発明は、配線基板を含むモジュールおよびその製造方法に関し、特に、その配線基板の表面にランド電極および配線導体が配置されるモジュールおよびその製造方法に関する。   The present invention relates to a module including a wiring board and a manufacturing method thereof, and more particularly to a module in which land electrodes and wiring conductors are arranged on the surface of the wiring board and a manufacturing method thereof.

ＬＴＣＣ（低温同時焼成セラミックス：Ｌｏｗ Ｔｅｍｐｅｒａｔｕｒｅ Ｃｏ− ｆｉｒｅｄ Ｃｅｒａｍｉｃｓ）による配線基板の表面に表面実装部品が実装される場合、通常、ランド電極を介して表面実装部品のみが実装され、ＬＴＣＣによる配線基板の表面に配線導体が形成されることはない。   When surface-mounted components are mounted on the surface of a wiring board by LTCC (Low Temperature Co-fired Ceramics), usually only the surface-mounted components are mounted via land electrodes, and the surface of the wiring board by LTCC No wiring conductor is formed on the wire.

たとえば、特許文献１には、表面実装部品が、配線基板の表面に形成されたランド電極にはんだ実装され、そのランド電極に接続されるビア導体を介して配線基板の内部に形成されている配線導体に接続されたモジュールの構成が開示されている。特許文献１の記載において、表面実装部品は、はんだにより実装されるため、はんだの広がりによるショートを抑制するために、配線基板の表面にランド電極以外の配線導体は形成されず、多層基板の内部に形成される配線導体により配線が行われている。   For example, in Patent Document 1, a surface-mounted component is solder-mounted on a land electrode formed on the surface of a wiring board, and the wiring formed inside the wiring board via via conductors connected to the land electrode A configuration of a module connected to a conductor is disclosed. In the description of Patent Document 1, since the surface-mounted component is mounted by solder, no wiring conductor other than the land electrode is formed on the surface of the wiring board in order to suppress a short circuit due to spreading of the solder. Wiring is performed by wiring conductors formed on the substrate.

特開２００６−３２４４２号公報JP 2006-32442 A

上述した理由により、配線基板の表面にはランド電極しか配置されず、そのランド電極からビア導体で一層下に形成される配線導体に引き回されていることから、配線基板の表面には配線導体が形成されていない。そのため、表面実装部品の配線を配線基板の内部に引き込むと、そのビア導体の分だけ余計な絶縁層が必要になり、モジュールの小型化、低背化を困難にするという問題があった。加えて、このような配線基板では、配線基板の表面に配線導体の形成が困難であるため、配線基板の表層における高密度化への障害ともなっていた。   For the reason described above, only the land electrode is arranged on the surface of the wiring board, and the wiring conductor is drawn from the land electrode to the wiring conductor formed below by the via conductor. Is not formed. Therefore, if the wiring of the surface mount component is drawn into the wiring board, an extra insulating layer is required for the via conductor, which makes it difficult to reduce the size and height of the module. In addition, in such a wiring board, it is difficult to form a wiring conductor on the surface of the wiring board, which has been an obstacle to increasing the density of the surface layer of the wiring board.

それゆえに、この発明の主たる目的は、配線基板を含むモジュールにおいて、その配線基板の表面に配置されたランド電極および配線導体が、はんだを介することなく表面実装部品と接合可能とすることで、小型化、低背化を可能にしたモジュールを提供することである。   Therefore, a main object of the present invention is to reduce the size of a module including a wiring board by allowing land electrodes and wiring conductors arranged on the surface of the wiring board to be joined to a surface mount component without using a solder. It is to provide a module that makes it possible to reduce the height and height.

この発明にかかるモジュールは、配線基板と、配線基板の一方主面に配置されるランド電極と、配線基板の一方主面に配置される配線導体と、ランド電極と接合するための外部電極を備える表面実装部品と、を含むモジュールであって、配線基板のランド電極の最表面および表面実装部品の外部電極の最表面にＳｎめっき層をそれぞれ備え、前記ランド電極の表面および前記配線導体の表面には、Ｓｎめっき層がそれぞれ形成されており、表面実装部品の外部電極は、ランド電極とＳｎを介してはんだなしで接合されることを特徴とする、モジュールである。
また、この発明にかかるモジュールでは、配線導体は、ランド電極と接続されていることが好ましい。
さらに、この発明にかかるモジュールでは、配線導体は、表面実装部品の下部に配置されており、かつ、表面実装部品と接することが好ましい。
さらにまた、この発明にかかるモジュールでは、配線基板の一方主面には、レジストが配置されないことが好ましい。
また、この発明にかかるモジュールの製造方法は、配線基板を準備する工程であって、配線基板の一方主面には、ランド電極および配線導体が配置される、配線基板を準備する工程と、外部電極を備える表面実装部品を準備する工程と、を備えるモジュールの製造方法であって、配線基板のランド電極の最表面および表面実装部品の外部電極の最表面にＳｎめっき層をそれぞれ備え、ランド電極の表面および配線導体の表面には、Ｓｎめっき層がそれぞれ形成されており、配線基板のランド電極と表面実装部品の外部電極とをＳｎを介してはんだなしで接合する工程を含む、モジュールの製造方法である。
また、この発明にかかるモジュールの製造方法では、配線基板を準備する工程は、ランド電極および配線導体のそれぞれにＳｎめっき処理を施す工程を含むことが好ましい。 A module according to the present invention includes a wiring board, a land electrode arranged on one main surface of the wiring board, a wiring conductor arranged on one main surface of the wiring board, and an external electrode for joining the land electrode. A surface-mounting component, comprising an Sn plating layer on the outermost surface of the land electrode of the wiring board and the outermost surface of the external electrode of the surface-mounting component, respectively, on the surface of the land electrode and the surface of the wiring conductor Is a module in which an Sn plating layer is formed, and an external electrode of the surface mount component is joined to the land electrode without solder via the Sn.
In the module according to the present invention, the wiring conductor is preferably connected to the land electrode.
Furthermore, in the module according to the present invention, it is preferable that the wiring conductor is disposed at a lower portion of the surface mount component and is in contact with the surface mount component .
Also of al, the module according to the present invention, on one main surface of the wiring substrate, it is preferable that the resist is not placed.
The module manufacturing method according to the present invention is a step of preparing a wiring board, wherein a land electrode and a wiring conductor are arranged on one main surface of the wiring board, and a step of preparing the wiring board. comprising the steps of preparing a surface mount component comprising an electrode, a manufacturing method of a module comprising a, Sn plating layer on the outermost surface of the outermost surface and the surface mounting component of the external electrodes of the land electrodes of the wiring board, respectively, land electrodes Of a module including a step of bonding a land electrode of a wiring board and an external electrode of a surface mount component without soldering via Sn, respectively, on the surface of the wiring and the surface of the wiring conductor. Is the method .
Also, in the manufacturing method of the module according to the present invention, the step of preparing a wiring board preferably includes a step of performing Sn plating on each of the land electrodes and the wiring conductors.

この発明にかかるモジュールによれば、配線基板の一方主面に表面実装部品を実装して接合する際に、はんだなどの接合剤を用いることなくＳｎを介して接合されているので、Ｓｎの融点が低いことから、低温で接合させることができるモジュールを得ることができる。また、配線基板に表面実装部品を実装して接合する際に、Ｓｎを介して接合されているので、はんだを用いて接合する場合に懸念される、はんだの広がりやはんだが広がることによって配線基板の一方主面に配置される配線導体間においてショートが発生する危険がなく、所望の分だけ接合することができるモジュールが得られる。
また、この発明にかかるモジュールは、配線基板の一方主面に配置されるランド電極と配線導体とが接続されているので、配線基板の内部に形成されていた配線導体のパターンを配線基板の一方主面に形成できることから、配線基板を構成する層を減少させることができ、その結果、配線基板やモジュール全体として低背化することができる。
さらに、この発明にかかるモジュールでは、配線導体が、表面実装部品の下部に配置されており、かつ、表面実装部品と接するように配置されていることから、この配線導体を放熱回路として利用することができる。
また、この発明にかかるモジュールでは、ランド電極および配線導体の表面に、Ｓｎめっき層が形成されていることから、ランド電極や配線導体において酸化やキズが生じにくいモジュールを得ることができる。
さらに、この発明にかかるモジュールでは、配線基板の表面にレジストを配置しないことから、レジスト分の厚みが不要となり、その結果、配線基板を低背化できるとともに、放熱効果も有するモジュールを得ることができる。
この発明にかかるモジュールの製造方法では、配線基板に表面実装部品を実装して接合する際に、はんだなどの接合剤を用いることなく、融点の低いＳｎを介して接合するので、低温で接合させることができるモジュールを得ることができる。
また、この発明にかかるモジュールの製造方法では、配線基板を準備する工程において、ランド電極および配線導体のそれぞれにＳｎめっき処理を施すことから、ランド電極や配線導体に対して酸化等やキズが生じにくいモジュールを得ることができる。According to the module of the present invention, when a surface mount component is mounted on and joined to one main surface of the wiring board, it is joined via Sn without using a bonding agent such as solder. Therefore, the melting point of Sn Therefore, a module that can be bonded at a low temperature can be obtained. In addition, when surface-mounted components are mounted on and bonded to the wiring board, they are bonded via Sn, so there is a concern when soldering is used to bond the wiring board due to the spread of solder and the spread of solder. Thus, there is no risk of short circuit between the wiring conductors arranged on one main surface, and a module that can be joined by a desired amount is obtained.
In the module according to the present invention, since the land electrode arranged on one main surface of the wiring board and the wiring conductor are connected, the pattern of the wiring conductor formed inside the wiring board is connected to one side of the wiring board. Since it can be formed on the main surface, the layers constituting the wiring board can be reduced, and as a result, the overall height of the wiring board and module can be reduced.
Furthermore, in the module according to the present invention, since the wiring conductor is arranged at the lower part of the surface mounting component and is arranged so as to be in contact with the surface mounting component, the wiring conductor is used as a heat dissipation circuit. Can do.
Further, in the module according to the present invention, since the Sn plating layer is formed on the surface of the land electrode and the wiring conductor, it is possible to obtain a module that is unlikely to be oxidized or scratched on the land electrode or the wiring conductor.
Furthermore, in the module according to the present invention, since no resist is disposed on the surface of the wiring board, the thickness of the resist becomes unnecessary, and as a result, the wiring board can be reduced in height and a module having a heat dissipation effect can be obtained. it can.
In the module manufacturing method according to the present invention, when surface-mounted components are mounted and bonded to a wiring board, bonding is performed via Sn having a low melting point without using a bonding agent such as solder. Module that can be obtained.
Further, in the module manufacturing method according to the present invention, in the step of preparing the wiring board, the land electrode and the wiring conductor are each subjected to Sn plating, so that the land electrode and the wiring conductor are oxidized or scratched. A difficult module can be obtained.

この発明によれば、配線基板を含むモジュールにおいて、その配線基板の表面に配置されたランド電極および配線導体が、はんだを介することなく表面実装部品と接合可能とすることで、小型化、低背化を可能にしたモジュールが得られる。   According to the present invention, in a module including a wiring board, land electrodes and wiring conductors arranged on the surface of the wiring board can be joined to a surface-mounted component without using solder, thereby reducing the size and height of the module. A module that can be realized is obtained.

この発明の上述の目的、その他の目的、特徴および利点は、図面を参照して行う以下の発明を実施するための形態の説明から一層明らかとなろう。   The above-described object, other objects, features, and advantages of the present invention will become more apparent from the following description of embodiments for carrying out the invention with reference to the drawings.

本発明にかかるモジュールの一実施の形態の平面図である。It is a top view of one embodiment of a module concerning the present invention. （ａ）は、図１に記載のモジュールのＡ−Ａの断面図解図である。また、（ｂ）は、（ａ）に記載のモジュールの要部を拡大して示す要部拡大図である。(A) is a cross-sectional solution figure of AA of the module described in FIG. Moreover, (b) is a principal part enlarged view which expands and shows the principal part of the module as described in (a). 図１に記載のモジュールにおいて、表面実装部品を取り除き、ランド電極部および配線導体部が配置された配線基板の一方主面の状態を示す平面図である。2 is a plan view showing a state of one main surface of a wiring board on which a land electrode part and a wiring conductor part are arranged in a module shown in FIG.

本発明にかかるモジュールの一実施の形態について説明する。図１は、本発明にかかるモジュールの一実施の形態の平面図である。また、図２（ａ）は、図１に記載のモジュールの断面図解図であり、図２（ｂ）は、図２（ａ）に記載のモジュールの要部を拡大して示す要部拡大図である。また、図３は、図１に記載のモジュールにおいて、表面実装部品を取り除き、ランド電極部および配線導体部が配置された配線基板の一方主面の状態を示す平面図である。   An embodiment of a module according to the present invention will be described. FIG. 1 is a plan view of an embodiment of a module according to the present invention. 2A is a cross-sectional view of the module shown in FIG. 1, and FIG. 2B is an enlarged view of the main part showing the main part of the module shown in FIG. It is. FIG. 3 is a plan view showing a state of one main surface of the wiring board in which the land electrode portion and the wiring conductor portion are arranged in the module shown in FIG.

この実施の形態にかかるモジュール１０は、配線基板１２を含む。配線基板１２は、絶縁層として多数のセラミック層１４を含み、多層に形成されている。配線基板１２の一方主面１２ａには、ランド電極部１６および配線導体部１８が配置される。また、配線基板１２の他方主面１２ｂには、配線導体部１８が配置される。   The module 10 according to this embodiment includes a wiring board 12. The wiring board 12 includes a large number of ceramic layers 14 as insulating layers, and is formed in multiple layers. A land electrode portion 16 and a wiring conductor portion 18 are disposed on one main surface 12 a of the wiring substrate 12. A wiring conductor portion 18 is disposed on the other main surface 12 b of the wiring board 12.

セラミック層１４の材料は、たとえば、低温焼結セラミック材料を用いることが好ましい。低温焼結セラミック材料とは、たとえば、１０００℃以下の焼成温度で焼結可能な材料であり、Ａｕ、Ａｇ及びＣｕ等の低融点金属と共焼結可能なセラミック材料のことをいう。低温焼結セラミック材料としては、たとえば、アルミナ、フォルステライト等のセラミック粉末にホウ珪酸系ガラスを混合してなるガラス複合系材料、ＺｎＯ−ＭｇＯ−Ａｌ2Ｏ3−ＳｉＯ2系の結晶化ガラスを用いた結晶化ガラス系材料、ＢａＯ−Ａｌ2Ｏ3−ＳｉＯ2系セラミック粉末やＡｌ2Ｏ3−ＣａＯ−ＳｉＯ2−ＭｇＯ−Ｂ2Ｏ3系セラミック粉末等を用いた非ガラス系材料等を挙げることができる。The material of the ceramic layer 14 is preferably a low-temperature sintered ceramic material, for example. The low temperature sintered ceramic material is, for example, a material that can be sintered at a firing temperature of 1000 ° C. or less, and refers to a ceramic material that can be co-sintered with a low melting point metal such as Au, Ag, and Cu. Low-temperature sintered ceramic materials include, for example, glass composite materials obtained by mixing borosilicate glass with ceramic powder such as alumina and forsterite, and ZnO—MgO—Al 2 O 3 —SiO 2 crystallized glass. Crystallized glass materials used, non-glass materials using BaO—Al 2 O 3 —SiO 2 ceramic powder, Al 2 O 3 —CaO—SiO 2 —MgO—B 2 O 3 ceramic powder, etc. Can be mentioned.

また、図２（ｂ）に示すように、配線基板１２の一方主面１２ａに配置されるランド電極部１６は、配線基板１２に実装される表面実装部品２０ａ，２０ｂと電気的に接続するために設けられる。ランド電極部１６は、ランド電極１６ａ、Ｎｉめっき層１６ｂおよびＳｎめっき層１６ｃを含む。配線基板１２の一方主面１２ａにランド電極１６ａが形成される。ランド電極１６ａの材料は、比抵抗の小さい導電性材料を用いることができる。導電性材料としては、たとえば、低温焼結セラミック材料と共焼結可能なＣｕやＡｇを主成分とする導電性材料を用いることができる。ランド電極１６ａの表面には、Ｎｉを含むＮｉめっき層１６ｂが形成される。さらに、Ｎｉめっき層１６ｂの表面には、Ｓｎめっき層１６ｃが形成される。すなわち、ランド電極部１６の最表面には、Ｓｎめっき層１６ｃが形成される。   Further, as shown in FIG. 2B, the land electrode portion 16 disposed on the one main surface 12a of the wiring board 12 is electrically connected to the surface mount components 20a and 20b mounted on the wiring board 12. Is provided. The land electrode portion 16 includes a land electrode 16a, a Ni plating layer 16b, and a Sn plating layer 16c. Land electrode 16 a is formed on one main surface 12 a of wiring substrate 12. As the material of the land electrode 16a, a conductive material having a small specific resistance can be used. As the conductive material, for example, a conductive material mainly composed of Cu or Ag that can be co-sintered with the low-temperature sintered ceramic material can be used. A Ni plating layer 16b containing Ni is formed on the surface of the land electrode 16a. Further, an Sn plating layer 16c is formed on the surface of the Ni plating layer 16b. That is, the Sn plating layer 16 c is formed on the outermost surface of the land electrode portion 16.

また、配線基板１２の一方主面１２ａおよび他方主面１２ｂに配置される配線導体部１８は、ランド電極部１６あるいは後述するビア導体２２と電気的に接続されるように配置されている。なお、たとえば、図２（ａ）に示すように、表面実装部品２０ｂの下部側に配置される配線導体部１８は、表面実装部品２０ｂに接するように配置してもよい。配線導体部１８は、配線導体１８ａ、Ｎｉめっき層１８ｂおよびＳｎめっき層１８ｃを含む。配線基板１２の一方主面１２ａおよび他方主面１２ｂに配線導体１８ａが形成される。配線導体１８ａの材料は、比抵抗の小さい導電性材料を用いることができる。導電性材料としては、たとえば、低温焼結セラミック材料と共焼結可能なＣｕやＡｇを主成分とする導電性材料を用いることができる。配線導体１８ａの表面には、Ｎｉを含むＮｉめっき層１８ｂが形成される。さらに、Ｎｉめっき層１８ｂの表面には、Ｓｎめっき層１８ｃが形成される。   Further, the wiring conductor portion 18 disposed on the one main surface 12a and the other main surface 12b of the wiring substrate 12 is disposed so as to be electrically connected to the land electrode portion 16 or a via conductor 22 described later. For example, as shown in FIG. 2A, the wiring conductor portion 18 disposed on the lower side of the surface mount component 20b may be disposed so as to contact the surface mount component 20b. The wiring conductor portion 18 includes a wiring conductor 18a, a Ni plating layer 18b, and a Sn plating layer 18c. A wiring conductor 18 a is formed on the one main surface 12 a and the other main surface 12 b of the wiring substrate 12. As the material of the wiring conductor 18a, a conductive material having a small specific resistance can be used. As the conductive material, for example, a conductive material mainly composed of Cu or Ag that can be co-sintered with the low-temperature sintered ceramic material can be used. A Ni plating layer 18b containing Ni is formed on the surface of the wiring conductor 18a. Further, an Sn plating layer 18c is formed on the surface of the Ni plating layer 18b.

そして、配線基板１２における各セラミック層１４を貫通するように、多数のビア導体２２が設けられており、各ビア導体２２は、ランド電極部１６および配線導体部１８と電気的に接続されている。また、配線基板１２の内部に位置する各セラミック層１４の表面には、内部配線導体２４が設けられており、各ビア導体２２は、各セラミック層１４に設けられた内部配線導体２４と電気的に接続されている。   A large number of via conductors 22 are provided so as to penetrate each ceramic layer 14 in the wiring board 12, and each via conductor 22 is electrically connected to the land electrode portion 16 and the wiring conductor portion 18. . An internal wiring conductor 24 is provided on the surface of each ceramic layer 14 located inside the wiring board 12, and each via conductor 22 is electrically connected to the internal wiring conductor 24 provided in each ceramic layer 14. It is connected to the.

表面実装部品２０ａ，２０ｂとしては、たとえば、能動素子あるいは受動素子等が挙げられる。図２（ｂ）には、配線基板１２に実装される表面実装部品２０ａの一例として積層セラミックコンデンサを断面図解図で示している。図２（ｂ）に示す積層セラミックコンデンサは、直方体状のセラミック素子２６を含む。セラミック素子２６は、誘電体としてたとえばチタン酸バリウム系の誘電体セラミックからなる多数のセラミック層２８を含む。これらのセラミック層２８は積層され、セラミック層２８間には、たとえばＮｉからなる内部電極３０および３２が交互に形成される。この場合、内部電極３０は他端部がセラミック素子２６の一端部に延びて形成され、内部電極３２は他端部がセラミック素子２６の一端部に延びて形成される。また、内部電極３０および３２は、中間部および他端部がセラミック層２８を介して重なり合うように形成される。したがって、このセラミック素子２６は、内部にセラミック層２６を介して複数の内部電極３０および３２が設けられた積層構造を有する。   Examples of the surface mount components 20a and 20b include active elements and passive elements. FIG. 2B shows a sectional ceramic capacitor as an example of a surface mount component 20a mounted on the wiring board 12 in a cross-sectional view. The multilayer ceramic capacitor shown in FIG. 2B includes a rectangular parallelepiped ceramic element 26. The ceramic element 26 includes a number of ceramic layers 28 made of, for example, a barium titanate dielectric ceramic as a dielectric. These ceramic layers 28 are laminated, and internal electrodes 30 and 32 made of, for example, Ni are alternately formed between the ceramic layers 28. In this case, the internal electrode 30 is formed with the other end extending to one end of the ceramic element 26, and the internal electrode 32 is formed with the other end extending to one end of the ceramic element 26. The internal electrodes 30 and 32 are formed so that the intermediate portion and the other end portion overlap with each other with the ceramic layer 28 interposed therebetween. Therefore, the ceramic element 26 has a laminated structure in which a plurality of internal electrodes 30 and 32 are provided via the ceramic layer 26.

セラミック素子２６の一端面には、外部電極部３４が設けられる。また、セラミック素子２６の他端面には、外部電極部３６が設けられる。外部電極部３４は、外部電極３４ａ、Ｎｉめっき層３４ｂおよびＳｎめっき層３４ｃを含む。また、外部電極部３６は、外部電極３６ａ、Ｎｉめっき層３６ｂおよびＳｎめっき層３６ｃを含む。   An external electrode portion 34 is provided on one end surface of the ceramic element 26. An external electrode portion 36 is provided on the other end surface of the ceramic element 26. The external electrode portion 34 includes an external electrode 34a, a Ni plating layer 34b, and a Sn plating layer 34c. The external electrode part 36 includes an external electrode 36a, a Ni plating layer 36b, and a Sn plating layer 36c.

セラミック素子２６の一端面には、たとえばＣｕからなる外部電極３４ａが内部電極３０に電気的に接続されるように形成される。同様に、セラミック素子２６の他端面には、たとえばＣｕからなる外部電極３６ａが内部電極３２に電気的に接続されるように形成される。   An external electrode 34 a made of, for example, Cu is formed on one end face of the ceramic element 26 so as to be electrically connected to the internal electrode 30. Similarly, an external electrode 36 a made of, for example, Cu is formed on the other end surface of the ceramic element 26 so as to be electrically connected to the internal electrode 32.

また、外部電極３４ａおよび３６ａの表面には、Ｎｉを含むＮｉめっき層３４ｂおよび３６ｂがそれぞれ形成される。さらに、Ｎｉめっき層３４ｂおよび３６ｂの表面には、酸化防止のために、Ｓｎめっき層３４ｃおよび３６ｃがそれぞれ形成される。すなわち、外部電極部３４の最表面にはＳｎめっき層３４ｃが形成され、外部電極部３６の最表面にはＳｎめっき層３６ｃが形成される。   Further, Ni plating layers 34b and 36b containing Ni are formed on the surfaces of the external electrodes 34a and 36a, respectively. Further, Sn plating layers 34c and 36c are formed on the surfaces of the Ni plating layers 34b and 36b, respectively, to prevent oxidation. That is, the Sn plating layer 34 c is formed on the outermost surface of the external electrode portion 34, and the Sn plating layer 36 c is formed on the outermost surface of the external electrode portion 36.

そして、配線基板１２の一方主面１２ａには、ランド電極部１６を介して表面実装部品２０ａの外部電極部３４，３６が電気的に接続されて実装される。ランド電極部１６と表面実装部品２０ａの外部電極部３４，３６とは、Ｓｎを介して接続される。すなわち、図２（ｂ）に示すように、このモジュールにおいて、配線基板１２の一方主面１２ａに配置されるランド電極部１６のＳｎめっき層１６ｃと表面実装部品２０ａの外部電極部３４，３６のＳｎめっき層３４ｃ，３６ｃとがＳｎを介して接合に必要な部分のみが接合される。各Ｓｎめっき層１６ｃ，３４ｃ，３６ｃはＳｎ単体からなるのが好ましい。なお、ランド電極部１６と表面実装部品２０ａの外部電極部３４，３６がＳｎを介して接続されていればよく、本実施の形態のように、ランド電極１６ａとＳｎめっき層１６ｃとの間に他の部材、たとえばＮｉめっき層１６ｂが配置されていてもよいし、外部電極３４ａ，３６ａと、Ｓｎめっき層３４ｃ，３６ｃとの間に他の部材、たとえばＮｉめっき層３４ｂ，３６ｂが配置されていてもよい。   Then, the external electrode portions 34 and 36 of the surface mount component 20a are electrically connected and mounted on the one main surface 12a of the wiring board 12 via the land electrode portion 16. The land electrode portion 16 and the external electrode portions 34 and 36 of the surface mount component 20a are connected via Sn. That is, as shown in FIG. 2B, in this module, the Sn plating layer 16c of the land electrode portion 16 disposed on the one main surface 12a of the wiring board 12 and the external electrode portions 34 and 36 of the surface mount component 20a are arranged. Only the portions necessary for the joining of the Sn plating layers 34c and 36c are joined via Sn. Each Sn plating layer 16c, 34c, 36c is preferably made of Sn alone. Note that the land electrode portion 16 and the external electrode portions 34 and 36 of the surface mount component 20a only have to be connected via Sn, and between the land electrode 16a and the Sn plating layer 16c as in the present embodiment. Other members, such as Ni plating layers 16b, may be disposed, and other members, such as Ni plating layers 34b, 36b, are disposed between the external electrodes 34a, 36a and the Sn plating layers 34c, 36c. May be.

また、表面実装部品２０ｂは、外部端子部３８，４０を含む。外部端子部３８，４０の最表面には、外部電極部３４，３６と同様にＳｎめっき層（図示せず）が形成されている。そして、表面実装部品２０ｂが配線基板１２の一方主面１２ａに実装されると、表面実装部品２０ｂの外部端子部３８，４０のＳｎめっき層とランド電極部１６のＳｎめっき層１６ｃとがＳｎを介して接合に必要な部分のみが接合される。   The surface mount component 20b includes external terminal portions 38 and 40. An Sn plating layer (not shown) is formed on the outermost surfaces of the external terminal portions 38 and 40 in the same manner as the external electrode portions 34 and 36. When the surface mounting component 20b is mounted on the one main surface 12a of the wiring board 12, the Sn plating layers of the external terminal portions 38 and 40 of the surface mounting component 20b and the Sn plating layer 16c of the land electrode portion 16 are Sn. Only parts necessary for joining are joined.

この実施の形態にかかるモジュール１０によれば、配線基板１２に表面実装部品２０ａ，２０ｂを実装して接合する際に、はんだなどの接合剤を用いることなく、Ｓｎを介して接合されているので、Ｓｎの融点の低いことから、低温で接合させることができる。また、配線基板１２に表面実装部品２０ａ，２０ｂを実装して接合する際に、はんだを用いて接合する場合に懸念される、はんだの広がりやはんだが広がることによって配線導体１８ａ間においてショートが発生する危険がなく、所望の分だけ接合することができる。   According to the module 10 according to this embodiment, when the surface mount components 20a and 20b are mounted and joined to the wiring board 12, they are joined via Sn without using a bonding agent such as solder. Since Sn has a low melting point, it can be bonded at a low temperature. Further, when mounting the surface-mounted components 20a and 20b on the wiring board 12 and joining them, a short circuit occurs between the wiring conductors 18a due to the spread of solder or the spread of solder, which is a concern when joining using solder. There is no danger of this, and it is possible to join as much as desired.

また、この実施の形態にかかるモジュール１０によれば、配線基板１２と表面実装部品２０ａ，２０ｂとの接合がはんだなどの接合剤を用いないので、配線基板１２の一方主面１２ａに配線導体部１８を配置させることができることから、その分、セラミック層１４を減らすことができる。加えて、配線基板１２の一方主面１２ａ上に配線導体部１８間を接近して配置させることができ、配線導体部１８の密度を向上させることができることから、その結果、配線基板１２の小型化、低背化を可能にしたモジュールを得ることができる。   Further, according to the module 10 according to this embodiment, since the bonding between the wiring board 12 and the surface mount components 20a and 20b does not use a bonding agent such as solder, the wiring conductor portion is formed on the one main surface 12a of the wiring board 12. Since 18 can be arranged, the ceramic layer 14 can be reduced correspondingly. In addition, the wiring conductor portions 18 can be arranged close to each other on the one main surface 12a of the wiring substrate 12 and the density of the wiring conductor portions 18 can be improved. As a result, the size of the wiring substrate 12 can be reduced. A module that can be reduced in height and height can be obtained.

また、この実施の形態にかかるモジュール１０によれば、配線基板１２の一方主面１２ａにランド電極部１６および配線導体部１８が形成されている場合であっても、ランド電極部１６においてはＳｎめっき層１６ｃが形成されており、配線導体部１８においてはＳｎめっき層１８ｃが形成されていることから、ランド電極部１６および配線導体部１８において酸化等が生ずることを回避することができるとともに、キズがつくことを防ぐことができる。   Further, according to the module 10 according to the present embodiment, even if the land electrode portion 16 and the wiring conductor portion 18 are formed on the one main surface 12a of the wiring substrate 12, the Sn in the land electrode portion 16 is Sn. Since the plating layer 16c is formed and the Sn plating layer 18c is formed in the wiring conductor portion 18, it is possible to avoid the occurrence of oxidation or the like in the land electrode portion 16 and the wiring conductor portion 18, and Can prevent scratches.

また、この実施の形態にかかるモジュール１０によれば、配線基板１２の一方主面１２ａに配置される配線導体部１８が、表面実装部品２０ａの底面と接するように配置されている場合には、配線導体部１８を放熱回路として利用することができる。   Further, according to the module 10 according to this embodiment, when the wiring conductor portion 18 disposed on the one main surface 12a of the wiring substrate 12 is disposed so as to contact the bottom surface of the surface mount component 20a, The wiring conductor portion 18 can be used as a heat dissipation circuit.

次に、本発明にかかるモジュールの製造方法の一実施の形態について説明する。   Next, an embodiment of a module manufacturing method according to the present invention will be described.

まず、低温焼結セラミック材料をビニルアルコール系バインダ中に分散させてスラリーを調製した後、このスラリーをドクターブレード法等によってキャリアフィルム上に塗布して低温焼結用のセラミックグリーンシートを作製する。その後、セラミックグリーンシートを所定の大きさに切断する。得られたセラミックグリーンシートに対して、レーザ加工することによって貫通孔を形成し、形成された貫通孔内にビア充填用導電性ペーストを充填する。   First, a low-temperature sintered ceramic material is dispersed in a vinyl alcohol binder to prepare a slurry, and then this slurry is applied onto a carrier film by a doctor blade method or the like to produce a ceramic green sheet for low-temperature sintering. Thereafter, the ceramic green sheet is cut into a predetermined size. Through holes are formed in the obtained ceramic green sheet by laser processing, and a conductive paste for via filling is filled in the formed through holes.

次いで、ランド電極１６ａとなるランド電極用導電性ペーストおよび配線導体１８ａとなる配線導体用導電性ペーストが、たとえば、スクリーン印刷法にて、上層に積層されるセラミックグリーンシートの表面に所定の形状にて印刷し、乾燥することにより、ランド電極１６ａおよび配線導体１８ａが形成される。また、２層目以降に積層されるセラミックグリーンシートの表面には、内部配線導体用導電性ペーストが、たとえば、スクリーン印刷法にて所定の形状に印刷し、乾燥することにより、内部配線導体２４が形成される。そして、ランド電極１６ａおよび配線導体１８ａが形成されたセラミックグリーンシートが上層となるように、所定の様式、方法にて、積層、圧着することにより、未焼成のセラミック積層体が得られる。   Next, the conductive paste for land electrode to be the land electrode 16a and the conductive paste for wiring conductor to be the wiring conductor 18a are formed into a predetermined shape on the surface of the ceramic green sheet laminated on the upper layer by, for example, screen printing. The land electrode 16a and the wiring conductor 18a are formed by printing and drying. In addition, the conductive paste for internal wiring conductor is printed on the surface of the ceramic green sheet laminated on the second and subsequent layers in a predetermined shape by, for example, a screen printing method, and dried, so that the internal wiring conductor 24 is dried. Is formed. And an unsintered ceramic laminated body is obtained by carrying out lamination | stacking and crimping | bonding by a predetermined style and method so that the ceramic green sheet in which the land electrode 16a and the wiring conductor 18a were formed becomes an upper layer.

その後、得られた未焼成のセラミック積層体を、たとえば１０５０℃以下の低温で焼成することにより、焼結体を得ることができる。そして、この焼結体の表面に形成されるランド電極１６ａおよび配線導体１８ａに対して、Ｎｉめっき処理およびＳｎめっき処理が施され、所望の配線基板１２を得ることで、配線基板１２が準備される。   Then, a sintered body can be obtained by firing the obtained unfired ceramic laminate at a low temperature of, for example, 1050 ° C. or lower. The land electrode 16a and the wiring conductor 18a formed on the surface of the sintered body are subjected to Ni plating treatment and Sn plating treatment to obtain a desired wiring substrate 12, whereby the wiring substrate 12 is prepared. The

続いて、準備された配線基板１２に実装される表面実装部品２０ａ，２０ｂが準備される。準備される表面実装部品２０ａは、外部電極部３４，３６を有し、表面実装部品２０ｂは、外部端子部３８，４０を有する。外部電極部３４，３６は、外部電極３４ａ，３６ａを含み、外部電極３４ａ，３６ａには、それぞれ予めＮｉめっき層３４ｂ，３６ｂおよびＳｎめっき層３４ｃ，３６ｃが形成されている。同様に、外部端子部３８，４０の最表面には、Ｓｎめっき層が形成されている。   Subsequently, surface mount components 20a and 20b to be mounted on the prepared wiring board 12 are prepared. The surface-mounted component 20a to be prepared has external electrode portions 34 and 36, and the surface-mounted component 20b has external terminal portions 38 and 40. The external electrode portions 34 and 36 include external electrodes 34a and 36a, and Ni plating layers 34b and 36b and Sn plating layers 34c and 36c are formed in advance on the external electrodes 34a and 36a, respectively. Similarly, an Sn plating layer is formed on the outermost surfaces of the external terminal portions 38 and 40.

準備された表面実装部品２０ａ，２０ｂの実装方法としては、リフロー工法が用いられる。すなわち、表面実装部品２０ａ，２０ｂは、その表面実装部品２０ａの外部電極部３４，３６あるいは表面実装部品２０ｂの外部端子部３８，４０が、配線基板１２におけるランド電極部１６に接するように実装され、リフロー処理される。そうすると、表面実装部品２０ａにおける外部電極部３４，３６のＳｎめっき層３４ｃ，３６ｃとランド電極部１６のＳｎめっき層１６ｃとがそれぞれ溶融することで、Ｓｎを介して配線基板１２と表面実装部品２０ａとが接合され、同様に、表面実装部品２０ｂにおける外部端子部３８，４０のＳｎめっき層とランド電極部１６のＳｎめっき層１６ｃとがそれぞれ溶融することで、Ｓｎを介して配線基板１２と表面実装部品２０ｂとが接合される。そして、所望のモジュール１０を得ることができる。   A reflow method is used as a method for mounting the prepared surface mount components 20a and 20b. That is, the surface mount components 20a and 20b are mounted such that the external electrode portions 34 and 36 of the surface mount component 20a or the external terminal portions 38 and 40 of the surface mount component 20b are in contact with the land electrode portion 16 on the wiring board 12. The reflow process is performed. Then, the Sn plating layers 34c and 36c of the external electrode portions 34 and 36 and the Sn plating layer 16c of the land electrode portion 16 in the surface mount component 20a are melted, so that the wiring board 12 and the surface mount component 20a are connected via Sn. In the same manner, the Sn plating layer of the external terminal portions 38 and 40 and the Sn plating layer 16c of the land electrode portion 16 in the surface mount component 20b are respectively melted, so that the wiring substrate 12 and the surface are connected via Sn. The mounting component 20b is joined. And the desired module 10 can be obtained.

この実施の形態にかかるモジュールの製造方法によれば、リフロー工法によって配線基板１２と表面実装部品２０ａ，２０ｂとが、融点が２３２℃と低いＳｎを介して接合しているので、はんだを介することなく低温で接合させることができる。   According to the manufacturing method of the module concerning this embodiment, since wiring board 12 and surface mount parts 20a and 20b are joined via Sn with a low melting point of 232 ° C. by reflow, a solder is used. And can be bonded at a low temperature.

また、この実施の形態にかかるモジュールの製造方法によれば、配線基板１２と表面実装部品２０ａ，２０ｂとの接合に際して、Ｓｎを介して接合されるので、表面実装部品２０ａ，２０ｂを配線基板１２の一方主面１２ａに実装する場合、はんだなどの接合剤を用いることがないことから、はんだの広がりやはんだが広がることによって、配線基板１２の一方主面に配置される配線導体間においてショートが発生する危険がなく、所望の分だけ接合させることができる。   In addition, according to the module manufacturing method of this embodiment, when the wiring board 12 and the surface mount components 20a and 20b are joined, they are joined via Sn, so that the surface mount components 20a and 20b are joined to the wiring board 12. In the case of mounting on one main surface 12a, a bonding agent such as solder is not used, so that the spread of the solder or the spread of the solder causes a short circuit between the wiring conductors arranged on the one main surface of the wiring board 12. There is no risk of occurrence, and the desired amount can be joined.

さらに、この実施の形態にかかるモジュールの製造方法によれば、ランド電極１６ａおよび配線導体１８ａに対してＳｎめっき処理が施される工程を含んでおり、ランド電極１６ａにＳｎめっき層１６ｃが形成され、配線導体１８ａにＳｎめっき層１８ｃが形成されることから、ランド電極部１６や配線導体部１８に対して酸化やキズが生じにくいモジュールを得ることができる。   Furthermore, the module manufacturing method according to this embodiment includes a step of performing Sn plating on the land electrode 16a and the wiring conductor 18a, and the Sn plating layer 16c is formed on the land electrode 16a. Since the Sn plating layer 18c is formed on the wiring conductor 18a, it is possible to obtain a module in which the land electrode portion 16 and the wiring conductor portion 18 are not easily oxidized or scratched.

なお、この発明は、上述した実施の形態に限定されるものではなく、その要旨の範囲内で種々に変形される。   The present invention is not limited to the above-described embodiment, and can be variously modified within the scope of the gist.

たとえば、本実施の形態にかかるモジュールでは、配線基板の一方主面において、レジストが配置されていても、配置されていなくてもよい。配線基板の一方主面にレジストが配置されていない場合は、レジスト分の厚みが不要となり、配線基板をさらに低背化することができ、加えて、放熱効果も有したモジュールを得ることができる。   For example, in the module according to the present embodiment, a resist may or may not be disposed on one main surface of the wiring board. When no resist is disposed on one main surface of the wiring board, the thickness of the resist becomes unnecessary, the wiring board can be further reduced in height, and in addition, a module having a heat dissipation effect can be obtained. .

また、本実施の形態にかかるモジュールでは、配線基板の一方主面に配置されるランド電極の最表面にＳｎめっき層が形成され、表面実装部品の外部電極部等の最表面にＳｎめっき層が形成され、それぞれのＳｎめっき層が接合されることによって、配線基板の一方主面に表面実装部品がＳｎを介して実装されているが、これに限るものではなく、ランド電極部および表面実装部品の外部電極部等のうち少なくともいずれか一方の最表面にＳｎめっき層が形成されることで、配線基板の一方主面に表面実装部品がＳｎを介して実装されてもよい。
また、Ｓｎめっき層としてＳｎ層は、湿式めっきや蒸着やスパッタなどの乾式めっき等のめっき法により形成されるものに限られず、Ｓｎペーストを塗布したり、印刷法、インクジェット法によって形成してもよい。In the module according to the present embodiment, the Sn plating layer is formed on the outermost surface of the land electrode arranged on one main surface of the wiring board, and the Sn plating layer is formed on the outermost surface of the external electrode portion of the surface mount component. By forming and bonding the respective Sn plating layers, the surface mount component is mounted on one main surface of the wiring board via Sn. However, the present invention is not limited to this, and the land electrode portion and the surface mount component are not limited thereto. A surface-mounted component may be mounted on one main surface of the wiring board via Sn by forming a Sn plating layer on the outermost surface of at least one of the external electrode portions and the like.
Further, the Sn layer as the Sn plating layer is not limited to the one formed by a plating method such as wet plating, dry plating such as vapor deposition or sputtering, but may be formed by applying Sn paste, printing method or ink jet method. Good.

また、本実施の形態にかかるモジュールでは、配線基板は多層に形成されているが、これに限るものではなく、単層の配線基板でもよい。   In the module according to the present embodiment, the wiring board is formed in multiple layers. However, the invention is not limited to this, and a single-layer wiring board may be used.

本発明は、小型化、低背化が求められる電子機器等に用いられるモジュールとして好適に利用することができる。   The present invention can be suitably used as a module used in an electronic device or the like that is required to be reduced in size and height.

１０ モジュール
１２ 配線基板
１２ａ 一方主面
１２ｂ 他方主面
１４ セラミック層
１６ ランド電極部
１６ａ ランド電極
１６ｂ Ｎｉめっき層
１６ｃ Ｓｎめっき層
１８ 配線導体部
１８ａ 配線導体
１８ｂ Ｎｉめっき層
１８ｃ Ｓｎめっき層
２０ａ、２０ｂ 表面実装部品
２２ ビア導体
２４ 内部配線導体
２６ セラミック素子
２８ セラミック層
３０、３２ 内部電極
３４、３６ 外部電極部
３４ａ、３６ａ 外部電極
３４ｂ、３６ｂ Ｎｉめっき層
３４ｃ、３４ｃ Ｓｎめっき層
３８、４０ 外部端子部DESCRIPTION OF SYMBOLS 10 Module 12 Wiring board 12a One main surface 12b The other main surface 14 Ceramic layer 16 Land electrode part 16a Land electrode 16b Ni plating layer 16c Sn plating layer 18 Wiring conductor part 18a Wiring conductor 18b Ni plating layer 18c Sn plating layer 20a, 20b Surface Mounted parts 22 Via conductor 24 Internal wiring conductor 26 Ceramic element 28 Ceramic layer 30, 32 Internal electrode 34, 36 External electrode part 34a, 36a External electrode 34b, 36b Ni plating layer 34c, 34c Sn plating layer 38, 40 External terminal part

Claims (6)

配線基板と、
前記配線基板の一方主面に配置されるランド電極と、
前記配線基板の一方主面に配置される配線導体と、
前記ランド電極と接合するための外部電極を備える表面実装部品と、
を含むモジュールであって、
前記配線基板の前記ランド電極の最表面および前記表面実装部品の前記外部電極の最表面にＳｎめっき層をそれぞれ備え、
前記ランド電極の表面および前記配線導体の表面には、Ｓｎめっき層がそれぞれ形成されており、
前記表面実装部品の前記外部電極は、前記ランド電極とＳｎを介してはんだなしで接合されることを特徴とする、モジュール。 A wiring board;
A land electrode disposed on one main surface of the wiring board;
A wiring conductor disposed on one main surface of the wiring board;
A surface-mount component including an external electrode for joining with the land electrode;
A module including
Each has an Sn plating layer on the outermost surface of the land electrode of the wiring board and the outermost surface of the external electrode of the surface mount component,
Sn plating layers are respectively formed on the surface of the land electrode and the surface of the wiring conductor,
The module, wherein the external electrode of the surface mount component is joined to the land electrode without solder via Sn. 前記配線導体は、前記ランド電極と接続されていることを特徴とする、請求項１に記載のモジュール。   The module according to claim 1, wherein the wiring conductor is connected to the land electrode. 前記配線導体は、前記表面実装部品の下部に配置されており、かつ、前記表面実装部品と接することを特徴とする、請求項１または請求項２に記載のモジュール。 The wiring conductor is disposed under the surface mount component, and is characterized in that contact with the surface mount component, module of claim 1 or claim 2. 前記配線基板の一方主面には、レジストが配置されないことを特徴とする、請求項１ないし請求項３のいずれかに記載のモジュール。 On one main surface of the wiring board, wherein the resist is not arranged, the module according to any one of claims 1 to 3. 配線基板を準備する工程であって、前記配線基板の一方主面には、ランド電極および配線導体が配置される、前記配線基板を準備する工程と、
外部電極を備える表面実装部品を準備する工程と、
を備えるモジュールの製造方法であって、
前記配線基板の前記ランド電極の最表面および前記表面実装部品の前記外部電極の最表面にＳｎめっき層をそれぞれ備え、
前記ランド電極の表面および前記配線導体の表面には、Ｓｎめっき層がそれぞれ形成されており、
前記配線基板の前記ランド電極と前記表面実装部品の前記外部電極とをＳｎを介してはんだなしで接合する工程を含む、モジュールの製造方法。 A step of preparing a wiring board, wherein a land electrode and a wiring conductor are arranged on one main surface of the wiring board;
Preparing a surface mount component with external electrodes;
A method of manufacturing a module comprising:
Each has an Sn plating layer on the outermost surface of the land electrode of the wiring board and the outermost surface of the external electrode of the surface mount component,
Sn plating layers are respectively formed on the surface of the land electrode and the surface of the wiring conductor,
A method for manufacturing a module, comprising the step of joining the land electrode of the wiring board and the external electrode of the surface-mounted component without solder via Sn. 前記配線基板を準備する工程は、
前記ランド電極および前記配線導体のそれぞれにＳｎめっき処理を施す工程を含む、請求項５に記載のモジュールの製造方法。 The step of preparing the wiring board includes:
The manufacturing method of the module of Claim 5 including the process of performing Sn plating process to each of the said land electrode and the said wiring conductor.
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