JP6117788B2 - 空間効率的な封じ込めデバイスおよびこれを作成する方法 - Google Patents
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Description
本出願は、2011年8月25に出願された米国仮特許出願第61/527,482号明細書の利益を主張する。本出願はその全体を参照によって本願明細書に組み込む。
Claims (23)
- 電気的に作動して開くことができる封じ込めリザーバを含む第1のマイクロチップ素子と、
生体適合性基板を含む第1の電子プリント回路基板(PCB)であって、前記第1のPCBが1つまたは複数の電子部品が固定された第1の側と、前記第1の側に対向する第2の側であって前記第1のマイクロチップ素子が固定された前記第2の側と、を有する第1の電子プリント回路基板(PCB)とを含み、
前記マイクロチップ素子は、前記1つまたは複数の電子部品に電気接続され、
前記第1のPCBの前記生体適合性基板は、前記1つまたは複数の電子部品を含む気密的に密閉されたエンクロージャの部分を規定する、封じ込めデバイス。 - 前記第1のPCBの前記生体適合性基板がセラミックである、請求項1に記載の封じ込めデバイス。
- 前記セラミックがアルミナである、請求項2に記載の封じ込めデバイス。
- 前記第1のPCBが、前記1つまたは複数の電子部品の少なくとも1つを前記第1のマイクロチップ素子に電気的に接続する少なくとも1つのビアを含む、請求項1に記載の封じ込めデバイス。
- 前記少なくとも1つのビアが前記第1のPCBの前記第2の側の金属化導電性表面に電気的に接続されており、前記金属化導電性表面が前記第1のマイクロチップ素子にワイヤボンド接合されている、請求項4に記載の封じ込めデバイス。
- 前記封じ込めリザーバが製剤またはセンサ素子を含むマイクロリザーバである、請求項1〜5のいずれか一項に記載の封じ込めデバイス。
- 生体適合性基板を含む第2の電子プリント回路基板(PCB)であって、前記第2のPCBが、1つまたは複数の電子部品が固定された第1の側と、前記第1の側に対向する第2の側とを有する第2の電子プリント回路基板(PCB)と、
前記第1のPCBを前記第2のPCBと共に固定するハウジングリングと、をさらに含み、
前記第1のPCBの前記第1の側が前記第2のPCBの前記第1の側の方に面した関係で配向される、請求項1に記載の封じ込めデバイス。 - 前記第1のPCBの前記生体適合性基板および前記第2のPCBの前記生体適合性基板が前記第1のPCBおよび前記第2のPCBそれぞれの前記第2の側の前記外部表面を形成する、請求項7に記載の封じ込めデバイス。
- 前記ハウジングリングが生体適合性金属で形成され、前記ハウジングリングは、前記第1の生体適合性基板及び前記第2の生体適合性基板ととともに、前記第1のPCBの前記電子部品および前記第2のPCBの前記電子部品を含む気密的に密閉されたエンクロージャを規定する、請求項8に記載の封じ込めデバイス。
- 前記第1のPCBおよび前記第2のPCBそれぞれの前記生体適合性基板がセラミックである、請求項9に記載の封じ込めデバイス。
- 前記セラミックがアルミナである、請求項10に記載の封じ込めデバイス。
- 前記第2のPCBの第2の側がアンテナを含む、請求項7に記載の封じ込めデバイス。
- 前記第2のPCBの第2の側が、電気的に作動して開くことができる封じ込めリザーバを含む第2のマイクロチップ素子を含む、請求項7に記載の封じ込めデバイス。
- 前記第1のマイクロチップ素子の前記封じ込めリザーバが製剤またはセンサ素子を含むマイクロリザーバである、請求項7〜13のいずれか一項に記載の封じ込めデバイス。
- 前記第1のマイクロチップ素子は、 第1の側と、対向する第2の側と、それらの中に延在する少なくとも1つの孔とを有するシリコン基板であって、前記第1の側が、前記少なくとも1つの孔を塞ぐ導電性のリザーバキャップを含む、シリコン基板と、
高分子またはガラスまたは他のセラミック材料で形成された主基板であって、前記主基板が、閉端部壁と、開端部と、前記閉端部壁と前記開端部との間に延在する少なくとも1つの側壁とによって画定される少なくとも1つのリザーバを有する主基板と、
前記少なくとも1つのリザーバ内に配置されるリザーバ内容物と、を含み、
リザーバ内容物の制御された放出または露出のために前記リザーバの前記開端部が前記少なくとも1つの孔に流体連通するように前記シリコン基板の前記第2の側が前記主基板に気密的に接合する、請求項1に記載の封じ込めデバイス。 - 封じ込めデバイスを組み立てる方法であって、
電気的に作動して開くことができる封じ込めリザーバを含む第1のマイクロチップ素子を用意するステップと、
前記第1のマイクロチップ素子を、生体適合性基板を含む第1の電子プリント回路基板(PCB)の第1の側に固定するステップと、
前記第1のマイクロチップ素子を前記第1のPCBの第2の側に固定された1つまたは複数の電子部品に電気的に接続するステップと、を含み、
前記第1のPCBの前記生体適合性基板は、前記1つまたは複数の電子部品を含む気密的に密閉されたエンクロージャの部分を規定する、方法。 - 前記電気的に接続するステップがワイヤボンディングを含む、請求項16に記載の方法。
- 前記第1のPCBの前記生体適合性基板がセラミックである、請求項16に記載の方法。
- 前記セラミックがアルミナである、請求項18に記載の方法。
- 前記第1のPCBが、前記1つまたは複数の電子部品の少なくとも1つを前記第1のマイクロチップ素子に電気的に接続する少なくとも1つのビアを含む、請求項16に記載の方法。
- 前記少なくとも1つのビアが前記第1のPCBの前記第2の側の金属化導電性表面に電気的に接続されており、前記金属化導電性表面が前記第1のマイクロチップ素子にワイヤボンド接合されている、請求項16に記載の方法。
- 生体適合性基板を含む第2の電子プリント回路基板(PCB)を用意するステップであって、前記第2のPCBが、1つまたは複数の電子部品が固定された第1の側と、前記第1の側に対向する第2の側とを有する、ステップと、
前記第1のPCBの前記第1の側が前記第2のPCBの前記第1の側の方に面して配向された状態でハウジングリングを前記第1のPCBと前記第2のPCBとに固定するステップと、
をさらに含む、請求項16〜21のいずれか一項に記載の方法。 - 前記封じ込めリザーバが製剤またはセンサ素子を含むマイクロリザーバである、請求項22に記載の方法。
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US201161527482P | 2011-08-25 | 2011-08-25 | |
US61/527,482 | 2011-08-25 | ||
PCT/US2012/052463 WO2013029037A2 (en) | 2011-08-25 | 2012-08-27 | Space-efficient containment devices and method of making same |
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WO2013029037A3 (en) | 2013-06-06 |
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US10441765B2 (en) | 2019-10-15 |
CA2845778A1 (en) | 2013-02-28 |
JP6667470B2 (ja) | 2020-03-18 |
SG11201400907PA (en) | 2014-07-30 |
US20130053671A1 (en) | 2013-02-28 |
KR102109870B1 (ko) | 2020-05-28 |
CA2845778C (en) | 2021-12-21 |
AU2017201049A1 (en) | 2017-03-23 |
JP2014524348A (ja) | 2014-09-22 |
AU2012298659B2 (en) | 2017-02-02 |
AU2012298659A1 (en) | 2014-03-06 |
EP2747642A2 (en) | 2014-07-02 |
CN103906466B (zh) | 2017-02-22 |
AU2017201049B2 (en) | 2019-03-07 |
HUE055646T2 (hu) | 2021-12-28 |
DK2747642T3 (da) | 2021-08-02 |
WO2013029037A2 (en) | 2013-02-28 |
EP2747642B1 (en) | 2021-04-28 |
CN107049243A (zh) | 2017-08-18 |
JP2017113619A (ja) | 2017-06-29 |
US20170050009A1 (en) | 2017-02-23 |
MY169202A (en) | 2019-02-27 |
CN103906466A (zh) | 2014-07-02 |
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