JP6029759B2 - 電子部品用の筐体、電子モジュール、電子部品用の筐体の製造方法、および、電子モジュールの製造方法 - Google Patents
電子部品用の筐体、電子モジュール、電子部品用の筐体の製造方法、および、電子モジュールの製造方法 Download PDFInfo
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- JP6029759B2 JP6029759B2 JP2015529000A JP2015529000A JP6029759B2 JP 6029759 B2 JP6029759 B2 JP 6029759B2 JP 2015529000 A JP2015529000 A JP 2015529000A JP 2015529000 A JP2015529000 A JP 2015529000A JP 6029759 B2 JP6029759 B2 JP 6029759B2
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Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49579—Lead-frames or other flat leads characterised by the materials of the lead frames or layers thereon
- H01L23/49586—Insulating layers on lead frames
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49861—Lead-frames fixed on or encapsulated in insulating substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
- H01L21/4839—Assembly of a flat lead with an insulating support, e.g. for TAB
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
- H01L33/483—Containers
- H01L33/486—Containers adapted for surface mounting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
- H01L2224/48471—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area being a ball bond, i.e. wedge-to-ball, reverse stitch
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1204—Optical Diode
- H01L2924/12044—OLED
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
- H01L2933/0008—Processes
- H01L2933/0033—Processes relating to semiconductor body packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
- H01L33/64—Heat extraction or cooling elements
- H01L33/647—Heat extraction or cooling elements the elements conducting electric current to or from the semiconductor body
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K50/00—Organic light-emitting devices
- H10K50/80—Constructional details
- H10K50/805—Electrodes
- H10K50/81—Anodes
- H10K50/814—Anodes combined with auxiliary electrodes, e.g. ITO layer combined with metal lines
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K50/00—Organic light-emitting devices
- H10K50/80—Constructional details
- H10K50/805—Electrodes
- H10K50/82—Cathodes
- H10K50/824—Cathodes combined with auxiliary electrodes
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49121—Beam lead frame or beam lead device
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Led Device Packages (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Lead Frames For Integrated Circuits (AREA)
- Electroluminescent Light Sources (AREA)
Description
MLPQ(Micro Leadframe Package Quad)
MLPM(Micro Leadframe Package Micro)
MLPD(Micro Leadframe Package Dual)
DRMLF(Dual Row Micro Leadframe Package)
DFN(Dual Flat No-lead Package)
TDFN(Thin Dual Flat No-lead Package)
UTDFN(Ultra Thin Dual Flat No-lead Package)
XDFN(eXtreme thin Dual Flat No-lead Package)
QFN‐TEP(Quad Flat No-lead package with Top Exposed Pad)
TQFN(Thin Quad Flat No-lead Package)
VQFN(Very Thin Quad Flat No Leads Package)
クワッドフラットパッケージ(QFP)と似ているが、これと異なるその重要な特徴は、電気的端子(ピン)がプラスチック外被の寸法を超えて側方に突出せず、スズめっきされていない銅端子の形態で筐体の下面に平坦に埋め込まれていることである。このことにより、プリント回路基板上における所要スペースを削減し、パッケージ密度をより高くすることができる。
Claims (8)
- ・導電性材料から成り、かつ、第1の面と、当該第1の面とは反対側の第2の面を有するリードフレーム部(12)と、
・成形材料(14)と
を有する、電子部品(20)用の筐体(10)であって、
前記リードフレーム部(12)は、コンタクト部(28)と、少なくとも1つの収容部(32)とを有し、
前記コンタクト部(28)は前記第1の面に、前記電子部品(20)の電気的コンタクトを行うためのコンタクト領域(26)を有し、
前記収容部(32)は前記第1の面に、前記電子部品(20)を配置するための収容領域(30)を有し、
前記コンタクト部(28)と前記収容部(32)とは、相互に物理的に分離されており、
前記コンタクト部(28)は、前記第1の面に対して垂直方向において、前記収容部(32)より薄く形成されており、
前記成形材料(14)は、前記収容領域(30)と前記コンタクト領域(26)とが露出している収容凹部(18)を有し、
前記成形材料(14)の一部が前記コンタクト部(28)と前記収容部(32)との間に設けられ、前記リードフレーム部(12)の第2の面が前記コンタクト部(28)の領域では前記成形材料(14)により覆われ、かつ、前記収容部(32)の領域では当該リードフレーム部(12)の第2の面に前記成形材料(14)が存在しないように、当該成形材料(14)に当該リードフレーム部(12)が埋め込まれており、
前記成形材料(14)は前記リードフレーム部(12)の第2の面において、前記コンタクト部(28)の領域に少なくとも1つの凹入部(62)を有し、
前記凹入部(62)に電気絶縁性材料(64)が充填されており、
前記凹入部(62)は、部分的に前記コンタクト部(28)の成形要素(80)により充填され、かつ、部分的に電気絶縁性材料(64)が充填されている
ことを特徴とする筐体(10)。 - 前記リードフレーム部(12)の第2の面の、前記コンタクト部(28)の領域にある前記成形材料(14)と、当該リードフレーム部(12)の第2の面の、前記収容部(32)の領域にある当該リードフレーム部(12)とが、平坦な面を形成する、
請求項1記載の筐体(10)。 - 電子部品(20)と、請求項1または2記載の筐体(10)とを備えた電子モジュール(8)であって、
前記電子部品(20)は前記収容領域(30)に配置されており、かつ、前記コンタクト領域(26)に電気的に結合されている
ことを特徴とする電子モジュール(8)。 - 電子部品(20)用の筐体(10)の製造方法であって、
・導電性材料から成り、かつ、第1の面と、当該第1の面とは反対側の第2の面を有するリードフレーム部(12)を準備するステップ
を有し、
前記リードフレーム部(12)は、コンタクト部(28)と、少なくとも1つの収容部(32)とを有し、
前記コンタクト部(28)は前記第1の面に、前記電子部品(20)の電気的コンタクトを行うためのコンタクト領域(26)を有し、
前記収容部(32)は前記第1の面に、前記電子部品(20)を配置するための収容領域(30)を有し、
前記コンタクト部(28)と前記収容部(32)とは、相互に物理的に分離されており、
前記コンタクト部(28)は、前記第1の面に対して垂直方向において、前記収容部(32)より薄く形成されており、
前記製造方法はさらに、
・前記リードフレーム部(12)を成形材料(14)に以下のように埋め込むステップであって、当該成形材料(14)が収容凹部(18)を有し、当該収容凹部(18)内では前記収容領域(30)と前記コンタクト領域(26)とに前記成形材料(14)が存在しない状態のままであり、前記成形材料(14)の一部が前記コンタクト部(28)と前記収容部(32)との間に設けられ、前記リードフレーム部(129)の第2の面が前記コンタクト部(28)の領域では前記成形材料(14)により覆われ、かつ、前記収容部(32)の領域では当該リードフレーム部(129)の第2の面に前記成形材料(14)が存在しない状態に維持されるように埋め込むステップ
を有し、
・前記リードフレーム部(12)を前記成形材料(14)に埋め込むために、第1の成形体(42)と第2の成形体(44)とを有する成形工具(40)を使用し、
・埋め込む対象である前記リードフレーム部(12)の第1の面が前記第1の成形体(42)側に来て、かつ、当該リードフレーム部(12)の第2の面が前記第2の成形体(44)側に来るように、当該リードフレーム部(12)を前記第1の成形体(42)と前記第2の成形体(44)との間に配置し、ここで、前記第2の成形体(44)は前記コンタクト部(28)の領域に少なくとも1つの第1の成形要素(60)を有し、当該第1の成形要素(60)の高さは、前記コンタクト領域(26)における前記リードフレーム部(12)の厚さと、前記収容部(32)における当該リードフレーム部(12)の厚さとの差以上であり、
・前記第1の成形体(42)と前記第2の成形体(44)とを互いに押しつけ合うことにより、前記第1の成形要素(60)は前記コンタクト部(28)を当該第1の成形体(42)に押しつけ、
・前記成形材料(14)を、前記両成形体(42,44)間に供給し、
・前記第1の成形要素(60)によって、前記成形材料(14)内に凹入部(62)を形成し、
前記成形要素(60)の高さは、前記コンタクト部(28)における前記リードフレーム部(12)の厚さと、前記収容部(32)における当該リードフレーム部(12)の厚さとの差より大きく、
前記両成形体(42,44)を互いに押しつけ合うと、前記コンタクト部(28)は前記リードフレーム部(12)の第2の面において、前記第1の成形要素(60)により変形する
ことを特徴とする製造方法。 - 前記リードフレーム部(12)の第2の面の、前記コンタクト部(28)の領域にある前記成形材料(14)と、当該第2の面において前記収容部(32)にある当該リードフレーム部(12)とが、平坦な面を形成するように、前記成形材料(14)を形成する、
請求項4記載の製造方法。 - 前記凹入部(62)に電気絶縁性材料(64)を充填する、
請求項4または5記載の製造方法。 - 前記リードフレーム部(12)と他のリードフレーム部(12)とを有するリードフレームを前記成形材料(14)に埋め込むことにより、当該リードフレーム部(12)を前記成形材料(14)に埋め込んで、筐体複合体を形成し、
前記リードフレームを前記成形材料(14)に埋め込んだ後、前記筐体複合体から複数の筐体(10)を分離する、
請求項4から6までのいずれか1項記載の製造方法。 - 電子モジュール(8)の製造方法であって、
請求項4から6までのいずれか1項記載の製造方法で筐体(10)を作製し、
電子部品(20)を前記収容領域(30)に配置し、かつ、前記コンタクト領域(26)に電気的に結合する
ことを特徴とする製造方法。
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DE102012215449.3 | 2012-08-31 | ||
PCT/EP2013/067773 WO2014033150A1 (de) | 2012-08-31 | 2013-08-28 | Gehäuse für ein elektronisches bauelement, elektronische baugruppe, verfahren zum herstellen eines gehäuses für ein elektronisches bauelement und verfahren zum herstellen einer elektronischen baugruppe |
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